WO2011127867A3 - 一种多层电路板及其制造方法 - Google Patents

一种多层电路板及其制造方法 Download PDF

Info

Publication number
WO2011127867A3
WO2011127867A3 PCT/CN2011/074807 CN2011074807W WO2011127867A3 WO 2011127867 A3 WO2011127867 A3 WO 2011127867A3 CN 2011074807 W CN2011074807 W CN 2011074807W WO 2011127867 A3 WO2011127867 A3 WO 2011127867A3
Authority
WO
WIPO (PCT)
Prior art keywords
circuit board
layer circuit
core
manufacturing
layer
Prior art date
Application number
PCT/CN2011/074807
Other languages
English (en)
French (fr)
Other versions
WO2011127867A2 (zh
Inventor
丁丽
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP11768478.7A priority Critical patent/EP2566306A4/en
Priority to BR112013000765A priority patent/BR112013000765A2/pt
Priority to CN2011800016324A priority patent/CN102301837B/zh
Priority to PCT/CN2011/074807 priority patent/WO2011127867A2/zh
Priority to RU2013100939/07A priority patent/RU2013100939A/ru
Publication of WO2011127867A2 publication Critical patent/WO2011127867A2/zh
Publication of WO2011127867A3 publication Critical patent/WO2011127867A3/zh
Priority to US13/686,057 priority patent/US9018531B2/en

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4638—Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09936—Marks, inscriptions, etc. for information
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

提供了一种多层电路板。所述多层电路板包括：堆叠在一起的多个芯板（1），所述芯板（1）包括贴置在一起的绝缘层和至少一层导体层，所述导体层包括电路，所述芯板（1）在至少一层导体层的边缘设置有至少一个标识导体（11），所述标识导体（11）在所述芯板（1）沿着芯板堆叠方向的侧面形成标识图形，所述多个芯板（1）的标识图形在所述多层电路板沿着芯板堆叠方向的侧面上各不相同。还提供了一种多层电路板的制作方法。
PCT/CN2011/074807 2011-05-27 2011-05-27 一种多层电路板及其制造方法 WO2011127867A2 (zh)

Priority Applications (6)

Application Number Priority Date Filing Date Title
EP11768478.7A EP2566306A4 (en) 2011-05-27 2011-05-27 MULTILAYER PCB AND MANUFACTURING METHOD THEREFOR
BR112013000765A BR112013000765A2 (pt) 2011-05-27 2011-05-27 painel de circuito de múltiplas camadas e método de fabricação do mesmo
CN2011800016324A CN102301837B (zh) 2011-05-27 2011-05-27 一种多层电路板及其制造方法
PCT/CN2011/074807 WO2011127867A2 (zh) 2011-05-27 2011-05-27 一种多层电路板及其制造方法
RU2013100939/07A RU2013100939A (ru) 2011-05-27 2011-05-27 Многослойная печатная плата и способ ее изготовления
US13/686,057 US9018531B2 (en) 2011-05-27 2012-11-27 Multilayer circuit board and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2011/074807 WO2011127867A2 (zh) 2011-05-27 2011-05-27 一种多层电路板及其制造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13/686,057 Continuation US9018531B2 (en) 2011-05-27 2012-11-27 Multilayer circuit board and manufacturing method thereof

Publications (2)

Publication Number Publication Date
WO2011127867A2 WO2011127867A2 (zh) 2011-10-20
WO2011127867A3 true WO2011127867A3 (zh) 2012-05-03

Family

ID=44799084

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2011/074807 WO2011127867A2 (zh) 2011-05-27 2011-05-27 一种多层电路板及其制造方法

Country Status (6)

Country Link
US (1) US9018531B2 (zh)
EP (1) EP2566306A4 (zh)
CN (1) CN102301837B (zh)
BR (1) BR112013000765A2 (zh)
RU (1) RU2013100939A (zh)
WO (1) WO2011127867A2 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104427748A (zh) * 2013-09-03 2015-03-18 北大方正集团有限公司 印刷电路板叠层错误检测方法、检测模块及印刷电路板
CN107041063B (zh) * 2017-06-09 2019-05-03 东莞市威力固电路板设备有限公司 一种多层pcb的加工方法及多层pcb
CN108260305A (zh) * 2018-01-11 2018-07-06 郑州云海信息技术有限公司 一种pcb板自动叠板棕化方法
CN108959995B (zh) * 2018-08-17 2022-10-14 张家港康得新光电材料有限公司 一种基板信息管理方法、装置、电子设备及存储介质
CN109451679B (zh) * 2018-11-22 2021-03-05 奥士康科技股份有限公司 一种多层pcb板叠放方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2582331Y (zh) * 2002-10-24 2003-10-22 倚天资讯股份有限公司 可验证叠层顺序的电路板
US20090087624A1 (en) * 2007-10-02 2009-04-02 Mitsubishi Electric Corporation Laminated structure

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4536239A (en) * 1983-07-18 1985-08-20 Nicolet Instrument Corporation Multi-layer circuit board inspection system
US5010449A (en) * 1990-04-04 1991-04-23 Eastman Kodak Company Multi-layer printed circuit board and a method for assuring assembly in a selected order
US5266380A (en) * 1992-09-08 1993-11-30 Motorola, Inc. Method and apparatus for visual verification of proper assembly and alignment of layers in a multi-layer printed circuit board
JP2638555B2 (ja) * 1995-02-16 1997-08-06 日本電気株式会社 多層プリント配線板
JPH0987400A (ja) * 1995-09-19 1997-03-31 Hitachi Chem Co Ltd 印刷配線板用プリプレグ
US6091026A (en) * 1996-11-30 2000-07-18 Samsung Electro-Mechanics Co. Ltd. Multi-layer printed circuit board with human detectable layer misregistration, and manufacturing method therefor
CN2587131Y (zh) * 2002-10-25 2003-11-19 楠梓电子股份有限公司 多层印刷电路板的对准度及涨缩程度的量测构造
JP2004214472A (ja) * 2003-01-07 2004-07-29 Toppan Printing Co Ltd プリント配線板及びその識別方法
JP2006202978A (ja) * 2005-01-20 2006-08-03 Sharp Corp プリント配線基板およびプリント配線基板の識別方法
CN100490603C (zh) * 2005-09-30 2009-05-20 环隆电气股份有限公司 可验证叠层顺序的电路板
US20090211785A1 (en) * 2008-02-21 2009-08-27 Lovskog J Thomas Printed circuit board with edge markings

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2582331Y (zh) * 2002-10-24 2003-10-22 倚天资讯股份有限公司 可验证叠层顺序的电路板
US20090087624A1 (en) * 2007-10-02 2009-04-02 Mitsubishi Electric Corporation Laminated structure

Also Published As

Publication number Publication date
BR112013000765A2 (pt) 2017-06-06
US9018531B2 (en) 2015-04-28
CN102301837B (zh) 2013-03-20
EP2566306A4 (en) 2013-07-03
WO2011127867A2 (zh) 2011-10-20
US20130081859A1 (en) 2013-04-04
EP2566306A2 (en) 2013-03-06
CN102301837A (zh) 2011-12-28
RU2013100939A (ru) 2014-07-20

Similar Documents

Publication Publication Date Title
WO2012072212A3 (de) Elektronisches bauteil, verfahren zu dessen herstellung und leiterplatte mit elektronischem bauteil
PH12016502502A1 (en) Printed circuit board, electronic component, and method for producing printed circuit board
WO2009037939A1 (ja) プリント配線板及びその製造方法
WO2011159722A3 (en) Method of manufacturing conductive structures
TW200623318A (en) Method for fabricating a multi-layer circuit board with fine pitch
US10321560B2 (en) Dummy core plus plating resist restrict resin process and structure
TW200624001A (en) Printed wiring board and manufacturing method therefor
US9674968B2 (en) Rigid flexible printed circuit board and method of manufacturing the same
KR101966326B1 (ko) 다층 경연성 인쇄회로기판 및 그 제조방법
KR102158068B1 (ko) 임베디드 인쇄회로기판
WO2011127867A3 (zh) 一种多层电路板及其制造方法
WO2012175207A3 (de) Elektronische baugruppe und verfahren zu deren herstellung
WO2012087058A3 (en) Printed circuit board and method for manufacturing the same
WO2012087059A3 (en) Printed circuit board and method for manufacturing the same
IN2014CN01630A (zh)
WO2018035536A3 (en) Method for producing a printed circuit board
US20150189735A1 (en) Rigid flexible printed circuit board and method of manufacturing the same
WO2014107295A1 (en) Flexible printed circuit
WO2007103949A3 (en) Processes for manufacturing printed wiring boards possessing electrically conductive constraining cores
US9992880B2 (en) Rigid-bend printed circuit board fabrication
WO2012087060A3 (en) Printed circuit board and method for manufacturing the same
PH12013000046A1 (en) Laminated inductor
WO2008096464A1 (ja) プリント配線板及びそのプリント配線板の製造方法
WO2012060657A3 (ko) 신규 인쇄회로기판 및 이의 제조방법
TW200610462A (en) Substrate manufacturing method and circuit board

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 201180001632.4

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11768478

Country of ref document: EP

Kind code of ref document: A2

WWE Wipo information: entry into national phase

Ref document number: 9973/CHENP/2012

Country of ref document: IN

REEP Request for entry into the european phase

Ref document number: 2011768478

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2011768478

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2013100939

Country of ref document: RU

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

REG Reference to national code

Ref country code: BR

Ref legal event code: B01A

Ref document number: 112013000765

Country of ref document: BR

ENP Entry into the national phase

Ref document number: 112013000765

Country of ref document: BR

Kind code of ref document: A2

Effective date: 20130111