WO2011125043A1 - Transistors ldmos pour des technologies cmos et procédé de fabrication associé - Google Patents

Transistors ldmos pour des technologies cmos et procédé de fabrication associé Download PDF

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Publication number
WO2011125043A1
WO2011125043A1 PCT/IB2011/051505 IB2011051505W WO2011125043A1 WO 2011125043 A1 WO2011125043 A1 WO 2011125043A1 IB 2011051505 W IB2011051505 W IB 2011051505W WO 2011125043 A1 WO2011125043 A1 WO 2011125043A1
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region
drain
regions
conductivity type
semiconductor device
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PCT/IB2011/051505
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German (de)
English (en)
Inventor
Thomas Uhlig
Lutz Steinbeck
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X-Fab Semiconductor Foundries Ag
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Application filed by X-Fab Semiconductor Foundries Ag filed Critical X-Fab Semiconductor Foundries Ag
Priority to US13/635,535 priority Critical patent/US9224856B2/en
Publication of WO2011125043A1 publication Critical patent/WO2011125043A1/fr
Priority to US14/971,699 priority patent/US20160126350A1/en
Priority to US15/798,792 priority patent/US10388785B2/en

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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Definitions

  • the invention relates to lateral DMOS transistors producible in CMOS processes
  • LDMOS low-density metal-oxide-semiconductor
  • a field effect transistor generally includes so-called drain and source regions separated by a channel region, which in turn is controlled by a gate electrode, to form a controllable current flow between the drain region and the source region.
  • a power field effect transistor is to be understood hereinafter as a field effect transistor which is operated at voltages of 15 V or more and / or at forward currents of approximately 500 mA or more.
  • field effect transistors are also referred to as MOS transistors, regardless of which material is actually used in the gate electrode.
  • CMOS process is to be understood as a process strategy in which complementary field effect transistors, i. p-channel transistors and n-channel transistors, in and over the active semiconductor layer. In the CMOS fabrication strategy, therefore, processes are required that enable the generation of p-type drain and source regions and the generation of n-type drain and source regions.
  • n- and p-type LDMOS transistors both n- and p-type LDMOS transistors (nLDMOS transistors, pLDMOS transistors) required.
  • nLDMOS transistors, pLDMOS transistors Both n- and p-type LDMOS transistors required.
  • the low-cost optimization of both types of lines at the same time presents a special challenge.
  • Breakdown voltage in the locked state (off-breakdown BV 0 ff) and low
  • a special class here are the so-called superjunction transistors, in which extraordinarily high conductivities in the drift region are achieved at high BV 0 ff by means of n / p multilayers.
  • LDMOS transistors have buried (buried) drift paths under the trench isolation region, benefiting from the high quality isolation material of the trench isolation as the upper boundary of the current path.
  • the gate and drain-side involvement of the drift region of such transistors usually requires special design measures, since the current path here without restrictions of
  • WO 2007/103610 A2 Freescale proposes that the drift path of an LD MOS transistor be led only under the trench isolation region on the gate side and the silicization in the thus extended drain side To prevent active area by using a silicide blocker.
  • FIG. 1 shows a schematic sectional view of the conventional power field-effect transistor (LDMOS) 150 from this document WO 2007/103610 A2 in the form of an n-channel transistor having lower-lying p / n layers, which are designated 102, 104 and 106, respectively. That is, layer 102 is n-doped while layers 106, 104 are p-doped. Furthermore, in the slightly p-doped region 106, a p-well 110 is formed, which thus represents the p-doped body region of the transistor 100. In the p-well 110, a heavily n-doped source region 118 is formed in conjunction with a heavily p-doped region 120, which serves as a body terminal.
  • LDMOS conventional power field-effect transistor
  • a drain drift region 108 is provided in conjunction with a heavily doped drain region 122, wherein, as previously explained, a trench isolation region 112 is embedded in the drain drift region 108. Further, over the p-well and a part of the drain drift region 108 and the trench isolation region 112, a gate electrode structure 114 is provided with a
  • Gate dielectric 116 is provided. A silicide formation on exposed
  • the consequence of the structure of the power field effect transistor 150 shown in FIG. 1 is a widened and less steepening current path towards the drain region 122, as a result of which RDS on is reduced. At the same time, due to the reduced current density, the tendency for impact ionization (avalanche) also decreases. Thus, with the same drain current, less bulk current, ie, current in the lower layers of the transistor 150, is generated. This delays the switching on of the internal parasitic bipolar transistor (snap-back in nLDMOS) and thus achieves a higher on-breakdown voltage.
  • the doping profile of the drift zone 108 can not be tailored exclusively to a type of transistor, in this solution due to incomplete depletion in the environment of Drain responsibles 122 often BV 0ff too low.
  • the invention is based, in a semiconductor device, the task
  • a semiconductor device having a lateral power field effect transistor.
  • the lateral power field effect transistor comprises a source region of a first conductivity type, a drain region of the first conductivity type, a drain drift region of the first conductivity type, a trench isolation region at least partially embedded in the drain drift region, and a doped field conduction region of a second, first conductivity type inverse conductivity type.
  • Trench isolation region and in particular the embedded in the drain drift region doped field guide region for a more favorable electric field distribution i. there is a forced guidance of the potential lines in the vicinity of the drain region, without, however, taking place pronounced disturbances of the field profile in the deeper layers of the semiconductor device.
  • RESURF areas remain almost unaffected by the field guidance area and no electrically-chargeable zones are generated.
  • a doped field-guiding region or field-guiding region is to be understood as a region which is counter-doped to the drain drift region and therefore forms a pn junction with it and influences the course of the electric field within the drain drift region.
  • the doped field guide region is provided as an area with freely adjustable potential without electrical connection.
  • a field guide area without electrical connection is also referred to as floating. In this way, there is no influence on the field line guidance by external voltages.
  • At least one further field conduction region of the second conductivity type is provided in the drain drift region.
  • one of the field guiding regions can be directly attached to the
  • Trench isolation area adjacent to an edge which faces the drain area. This measure results in a very favorable field profile, since first the Bottom of the trench isolation area as an efficient means of adjusting the
  • Field course is used and then allows the field guide area a gradual expansion of the electric field in the upper region of the drain drift region.
  • no metal silicide is provided in the surface of the drain drift region. In this way, the advantageous field profile described in connection with FIG. 1 can be improved in such a way that partially depleted regions in the vicinity of the drain region are avoided and thus the breakdown voltage is increased.
  • the lateral power field-effect transistor has a doped body connection region of the second conductivity type adjacent to
  • Source region wherein the field guide region and the doped body lead region have a same dopant profile in the depth direction. So they can
  • the maximum dopant concentration of the field guide region is greater than a maximum dopant concentration of
  • Field control area associated with its size and also with the number of field guide areas can thus achieve an effective control of the field profile in the drain drift area, although standard implantation processes can still be applied. For example, the increased maximum
  • Dopant concentration can be generated by the fact that the field guide area is subjected to at least one implantation process more than about the body connection area in the context of the required implantation processes.
  • the semiconductor device includes a small signal transistor having deep drain and source regions and shallow drain and source extension regions.
  • a small signal transistor is to be understood as a transistor which is designed for operation at voltages of less than (or equal to) 15V. These highly doped regions of the small signal transistor can be almost identical
  • the field guide region can be produced during an implantation for producing shallow drain and source regions, while in other cases the field guide region can be generated when generating deep drain regions. and source regions of the small signal transistor is generated, wherein, if necessary, in the field guide region previously also the implantation for the shallow drain and source regions may have been performed.
  • the small signal transistor has a
  • Gate electrode with a gate length of 200 nm (nanometers) or less.
  • the power field effect transistor can be made on the basis of a technology that can handle very demanding control tasks by providing small signal transistors of the dimensions given above
  • a second lateral power field effect transistor is provided, which is of complementary conductivity type in comparison to the already provided field effect transistor.
  • the above object is achieved by a method for manufacturing a semiconductor device with a lateral power field effect transistor.
  • the method includes generating a trench isolation region and a drain drift region of a first conductivity type such that the trench isolation region is at least partially embedded in the drain drift region.
  • the method further comprises performing one or more ion implantation processes to create deep drain and source regions and / or drain and source extension regions in a small signal transistor of a second conductivity type inverse to the first conductivity type.
  • the method further comprises generating one or more field guide regions in the drain drift region through at least one of the one or more ion implantation processes.
  • Power transistor using implantation processes which are also used for the production of heavily doped areas in small signal transistors. This results in a very efficient production process, since no additional process steps are required.
  • the implantation processes and associated masking schemes for generating complementary small signal transistors can be efficiently used to also create suitable field-guiding regions for complementary power transistors.
  • suitable photolithography masks may be provided which release surface areas of the drain drift region during the respective implantation processes, see above that thereby the lateral structure of the field guidance areas can be adjusted efficiently.
  • the desired field profile in the drain drift region can be determined by default
  • Mask openings which thus determine the number and the lateral shape of the field guide areas, for the particular application set specifically, without requiring a change in the process parameters of the associated implantation processes would be required or other process steps are added.
  • FIG. 1 is a sectional view of a conventional LDMOS
  • FIG. 2 is a sectional view of a semiconductor device during FIG.
  • FIG. 3 is a schematic sectional view of FIG.
  • FIG. 4 is a schematic sectional view of a part of FIG.
  • FIG. 5 is a sectional view of a complementary power field effect transistor that is alternative or in addition to the
  • FIG. 2 shows a schematic sectional view of a semiconductor component 90 which has a small-signal transistor 50K and a lateral power field-effect transistor or DMOS transistor 50P.
  • the component 90 comprises a substrate 30 on which suitable semiconductor layers, for example epitaxially grown silicon layers, are applied.
  • a lightly n-doped layer 4 is provided which serves as the body region of the transistor 50P, thus constituting a p-channel transistor.
  • a p-type body region 10 of the transistor 50K is formed, which is thus an n-channel transistor.
  • the lateral dimension of the small signal transistor 50K is defined by corresponding trench isolation regions 12.
  • a corresponding trench isolation region 12 is also provided in a drain drift region 8 in order thus to obtain a more favorable potential profile, as already explained in connection with the transistor 150 from FIG.
  • the drain Drift region 8 is thus a correspondingly p-doped region in which a heavily doped drain region is to be generated in further manufacturing processes.
  • transistors 50K and 50P have gate electrode structures 14K and 14, respectively, which include respective isolation layers 16K and 16, respectively.
  • an implantation mask 26 is provided which leaves the transistor 50K open in order to generate flat n-doped drain and source extension regions 23 in the body region 10.
  • Field lead region 28E is generated in the drain drift region 8, wherein the lateral size and position of the region 28E are predetermined by the mask opening 27.
  • the lateral dimension 27L of the opening 27 can be suitably adjusted, as shown in dashed lines, in order to produce suitable field guidance or bending of the potential lines depending on the doping profile achieved by an implantation process 25.
  • the implantation process 25 is thus considered a
  • Implantation mask 26 accomplished with the opening 27.
  • the semiconductor device 90 can therefore be fabricated based on standard CMOS processes. That is, before or after the formation of the trench isolation regions 12 based on well-known techniques, the implantation processes for deeper regions of the device 90 such as the drain drift region 8 and the body region 10 may be made appropriate as needed
  • Gate electrode structures 14K and 14 produce.
  • process technologies can be used with which the gate electrode structure 14K is structured with a gate length of 200 nm or less.
  • the mask 26 is produced by suitable lithography processes.
  • FIG. 3 shows the semiconductor device 90 in a more advanced form
  • Manufacturing phase in which a further implantation process 29 is performed on the basis of a mask 30.
  • a further implantation process 29 is performed on the basis of a mask 30.
  • deep drain and source regions 32 are generated in the transistor 50K, which in cooperation with the
  • the mask 30 includes an opening 31 defining the lateral location and size and thus also the shape of a field guide region 28 created by the implantation process 29 in the drain drift region 8.
  • the regions 32 and 28 thus have an approximately equal doping profile in one
  • Depth direction T which is to be understood as the vertical direction in Figure 3.
  • the entire vertical dopant profile is also determined by region 28E due to previously introduced dopants to form region 28E, while in other embodiments (not shown) the dopant profile of region 28 is determined solely by implant 29 or
  • a mask opening 33 may also be provided if a heavily n-doped body connection region 20 is also during the default
  • Implantation process 29 is to be generated. If necessary, a corresponding
  • Opening may also be provided in the implantation process 25 of FIG. 2 if a dopant concentration higher at least on the surface is desired, as is the case for the combination of the regions 23 and 32. So if same
  • Figure 4 shows the semiconductor device 90 in a more advanced
  • Drain region 22 is formed in the p-doped drain drift region 8. Furthermore, one or more field guide regions 28 or 28A are provided in a region of the drift region 8 with a suitable lateral position, size and shape, in order thus to achieve the desired potential line profile in the drift region 8, as also explained above. On the surface of the heavily doped drain region 18, the heavily doped
  • Body connection region 20 the heavily doped source region 22 and, in the embodiment shown, the heavily doped field guide region 28 are corresponding
  • Metal silicide 18S, 20S, 22S, 28 S formed. Further, a metal silicide 14S is also present in the gate electrode structure 14. Furthermore, surface regions of the drift region 8, on which no metal silicide is to be formed, are prevented by a silicide
  • Blocking mask 24 covered.
  • the semiconductor device 90 shown in FIG. 4 can be manufactured on the basis of standard CMOS processes, in particular the heavily doped drain and Source region 18, 22 can be generated in connection with implantation process for p-type small signal transistors, as shown for example for the n-channel transistor 50K in Figures 2, 3 for the generation of the regions 28, 28A and 20, which are inversely doped to That is, the regions 18 and 22 are formed by covering the remaining surface of the region 8 by standard implantation processes for p-channel transistors, while on the other hand, the heavily doped field guide regions 28 and 28A and also the strong doped body connection region 20 are generated during one or more corresponding implantation processes, in which the heavily doped drain and
  • Source regions of n-channel transistors are produced.
  • Silicide blocking mask 24 can be prepared by standard deposition techniques, lithographic processes, and patterning techniques. For this purpose, materials such as silicon dioxide, silicon nitride and the like are suitable. Subsequently, metal silicide is prepared by, for example, depositing a suitable refractory metal and reacting with the silicon in the exposed semiconductor surfaces. After removal of excess metal, the structure shown in Figure 4 is formed.
  • FIG. 5 schematically shows the semiconductor device 90, wherein a transistor 50N is provided, which is manufactured in addition or alternatively to the transistor 50P (see Figures 2-4).
  • the transistor 50 a is an n-channel transistor and is thus one of the
  • the drift region 8 is an n-doped region, while the body region 4 is a p-doped region.
  • the heavily doped drain and source regions 18, 22 are heavily n-doped regions, while the body connection region 20 is a heavily p-doped region. Accordingly, the heavily doped field guide region 28 is a p-doped region.
  • the transistor 50N may also be fabricated based on standard CMOS processes, wherein upon implantation of drain and source regions and / or extension regions of p-type low power transistors, the one or more regions 28 may be partially or fully co-located with the region 20 are generated. Similar processes as previously explained for the transistor 50P may be used, however, the doping modes introduced during the respective implantation processes are to be correspondingly switched.
  • the LDMOS transistors 50P, 50N shown in FIGS. 2 to 4, on the one hand, and FIG. 5, on the other hand, are similar in construction, but differ from each other in the manner of the FIGS. 2 to 4, on the one hand, and FIG. 5, on the other hand, are similar in construction, but differ from each other in the manner of the FIGS. 2 to 4, on the one hand, and FIG. 5, on the other hand, are similar in construction, but differ from each other in the manner of the FIGS. 2 to 4, on the one hand, and FIG. 5, on the other hand, are similar in construction, but differ from each other in the manner
  • nLDMOS 50N is the
  • Drift path from the corresponding part of the n-well 8 and the body region 4 is formed as a well in the drift region 8.
  • Both LDMOS transistors have drift paths that extend partially below the STI region 12, wherein in a preferred embodiment
  • Embodiment at the drain region 22 facing STI edge 12A each one
  • Field guide area 28 is arranged so that a suitable field guidance results in the direction of the surface and the drain region 22.
  • the floating regions 28, 28A ensure suitable field guidance, ie a forced guidance of the potential lines (bending) in the vicinity of the drain region 22, without disturbing the RESURF equilibrium in the depth or forming electrically rechargeable zones.
  • suitable field guidance ie a forced guidance of the potential lines (bending) in the vicinity of the drain region 22, without disturbing the RESURF equilibrium in the depth or forming electrically rechargeable zones.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

Dans un composant semi-conducteur, un transistor à effet de champ de puissance latéral en tant que transistor LDMOS est fabriqué de telle sorte qu'un profil de potentiel amélioré soit obtenu dans une zone de migration de drain (8) du transistor, en association avec une zone d'isolation par tranchées (12) et une zone de guidage de champ fortement dopée (28, 28A). A cet effet, des processus d'implantation normalisés de la technologie CMOS peuvent être mis en place dans des modes de réalisation avantageux sans que des étapes de procédé supplémentaires soient nécessaires.
PCT/IB2011/051505 2010-04-09 2011-04-07 Transistors ldmos pour des technologies cmos et procédé de fabrication associé WO2011125043A1 (fr)

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US14/971,699 US20160126350A1 (en) 2010-04-09 2015-12-16 Ldmos transistors for cmos technologies and an associated production method
US15/798,792 US10388785B2 (en) 2010-04-09 2017-10-31 LDMOS transistors for CMOS technologies and an associated production method

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US20160126350A1 (en) 2016-05-05
US9224856B2 (en) 2015-12-29
US20180166567A1 (en) 2018-06-14
US10388785B2 (en) 2019-08-20
DE102010014370A1 (de) 2011-10-13
DE102010014370B4 (de) 2021-12-02

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