WO2011120806A1 - Verfahren zum ansteuern einer anzahl an modulen - Google Patents
Verfahren zum ansteuern einer anzahl an modulen Download PDFInfo
- Publication number
- WO2011120806A1 WO2011120806A1 PCT/EP2011/053973 EP2011053973W WO2011120806A1 WO 2011120806 A1 WO2011120806 A1 WO 2011120806A1 EP 2011053973 W EP2011053973 W EP 2011053973W WO 2011120806 A1 WO2011120806 A1 WO 2011120806A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- trigger
- circuit arrangement
- modules
- register
- signal
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40026—Details regarding a bus guardian
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/403—Bus networks with centralised control, e.g. polling
- H04L12/4035—Bus networks with centralised control, e.g. polling in which slots of a TDMA packet structure are assigned based on a contention resolution carried out at a master unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40208—Bus networks characterized by the use of a particular bus standard
- H04L2012/40241—Flexray
Definitions
- the invention relates to a method for driving a number of modules, in particular a number of hardware modules or units, and a circuit arrangement for carrying out the method.
- Actuators used in various embedded systems control, inter alia. Actuators and sensors. Actuators are characterized by the fact that they are supplied with signals at certain points in time and in many cases also have to be activated simultaneously in order to perform a function. Such output signals are typically driven by highly complex timer architectures. In this case, a plurality of output signals can be output on the basis of predetermined time stamps, counter values or by triggering the cells with one another.
- the proposed method provides a flexible triggering mechanism
- timebases not only does it work on timebases, it also allows triggering and control of multiple hardware units for signal output simultaneously.
- the proposed trigger mechanism is so flexible that even non-adjacent modules can notify each other, turn on, turn off or trigger the reloading of parameter sets.
- the proposed circuit arrangement consists of a module that implements the flexible triggering mechanism.
- the individual connected modules can be interconnected and different trigger mechanisms (time, CPU access, other output module (s) Certainly can be set. Due to the respective trigger source it is possible to switch the output units off, on, and / or to switch the respective outputs off or on and / or to reload a parameter set in parallel.
- the proposed solution is characterized in that the trigger mechanism can be reprogrammed during runtime. In the case of known approaches, however, this is predefined rigidly in the multiplexers used. Each channel can influence every other channel via the provided internal trigger (feedback).
- the proposed triggering mechanism may be part of a timer platform for the automotive sector. Alternatively, the mechanism can also be used in industrial environments.
- a circuit arrangement for a flexible trigger mechanism is provided for at least two modules, in which these at least two modules for common triggering need not have any topological feature and the common triggering does not have to be on a global time base.
- the trigger mechanism described can be triggered by a time event, a CPU trigger or a trigger event of one or more connected hardware unit (s).
- the output trigger mechanisms can be used in parallel with each other, and the trigger mechanisms can be triggered by both hardware and software.
- a time base unit can be used, which can provide a common time base for the microcontroller.
- the timebase unit or time base submodule is organized in channels, with the number of channels being device independent. At least two channels are implemented within the TBU. Typically, each of the channels has a 24-bit time base register. However, other lengths, such as 16 bits, 32 bits, etc., may also be provided.
- the timebase channels can be operated independently.
- Figure 1 shows a block diagram of an embodiment of the presented
- FIG. 2 shows a block diagram of the connection of hardware modules
- FIG. 1 shows in a block diagram a circuit arrangement 10 which implements a central triggering mechanism.
- the illustration shows a register 12 in which a nominal value ACT_TB is stored, a first AND gate 14, a multiplexer 16 for inputting time bases TBU_TS2 18, TBU_TS1 20 and
- FIG. 1 shows a central trigger mechanism which provides as input signals one or more time bases and / or trigger signals from other modules and / or contains a bus interface for configuration by a central processing unit or CPU. The signals arriving there can be flexibly interconnected by the proposed architecture and execute corresponding actions at the outputs.
- FIG. 2 shows a hardware module TOM 100, which in this case is provided as a timer output module and is connected to a central trigger mechanism. The illustration shows a first trigger channel TGCO 102 and a second trigger channel TGC1 104.
- the trigger channel TGCO 102 is connected to eight module channels TOM_CH0 106 to TOM_CH7 108.
- the trigger channel TGC1 104 is connected to eight module channels TOM_CH8 1 10 to TOM_CH15 1 12. Furthermore, an interface 1 14 is provided for a microcontroller bus.
- time bases TBU_TS0 120, TBU_TS1 122 and TBU_TS2 124 are input as input signals.
- Outputs of the two trigger channels 102 and 104 are the signals OUTEN 130, ENDIS 132, FUPD 134 and UPEN 136.
- a trigger signal TRIG 138 is provided. This trigger signal 138 is to be divided into TRIG_0 140 to TRIG_7 142, TRIG_8 144 to TRIGJ 5
- Other input signals are TOM_TRIG_ [i-1] 150, CMU_FXCLK 152, SPE0JDUT 154 and SPE7JDUT 156 (SPE: Sensor Pattern Evaluation).
- the SPE is a module that evaluates the inputs of sensors, eg Hall sensors.
- Output signals are TOM_CH0 160, TOM_CH0_SOUR 162, TOM_CH8_OUT 164,
- FIG. 1 shows how the hardware modules to be controlled are connected to the flexible trigger mechanism.
- Part of the structure is responsible for taking values from time bases (TBU_TSx) and comparing them with a setpoint (ACT_TB). The setpoint is typically specified by a CPU. This part then generates a corresponding trigger.
- a second part can be described via the bus interface and trigger a trigger (HOST_TRIG).
- Another part combines triggers that can come from hardware units (TOM) (hardware triggers) and derive a common trigger signal from them. This part can flexibly combine the incoming trigger lines, so that the topological position that the hardware units triggering the triggers does not play a role.
- the input triggers valid for the resulting trigger are written in a register specified (INT_TRIG), which is typically described by the CPU.
- the triggering mechanism also has output structures that process the total triggers resulting from the input triggers and trigger corresponding output triggers and actions in the connected hardware modules (TOMs).
- TOMs connected hardware modules
- As an output trigger mechanism it is possible, for example, to switch several hardware units on or off in parallel (ENDIS_CTRL, ENDIS_STAT).
- the control, whether off or on, is realized with a register 42 ENDIS_CTRL, where those hardware units are marked, which should be switched on or off together when the trigger occurs.
- the current state of whether a unit is on or off can be determined by reading register 52 ENDIS_STAT.
- the CPU can switch several channels directly on or off simultaneously via the bus interface by writing directly to register 52 ENDIS_STAT.
- Another output mechanism can turn the hardware unit (TOM) output signals on or off in parallel. In this case, it is again possible to control this via the resulting trigger (OUTEN_CTRL) or from the CPU with the register 50 OUTEN_STAT.
- TOM hardware unit
- Yet another output mechanism is the simultaneously enforced update of parameters in the connected hardware units (FUPD_CTRL). There is entered in the register 38, to which of the connected hardware units, the parameters are to be updated simultaneously.
- the output trigger mechanisms can also be applied to individual hardware modules.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Electronic Switches (AREA)
- Programmable Controllers (AREA)
- Logic Circuits (AREA)
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP20110709918 EP2553589B1 (de) | 2010-03-31 | 2011-03-16 | Verfahren zum ansteuern einer anzahl an modulen |
JP2013501730A JP5676740B2 (ja) | 2010-03-31 | 2011-03-16 | 複数のモジュールを駆動する方法 |
US13/637,727 US9281803B2 (en) | 2010-03-31 | 2011-03-16 | Method for actuating a number of modules |
KR1020127025708A KR101751565B1 (ko) | 2010-03-31 | 2011-03-16 | 복수의 모듈의 작동 방법 |
CN201180016815.3A CN102812449B (zh) | 2010-03-31 | 2011-03-16 | 用于激励多个模块的方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE201010003558 DE102010003558A1 (de) | 2010-03-31 | 2010-03-31 | Verfahren zum Ansteuern einer Anzahl an Modulen |
DE102010003558.0 | 2010-03-31 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2011120806A1 true WO2011120806A1 (de) | 2011-10-06 |
Family
ID=44068435
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2011/053973 WO2011120806A1 (de) | 2010-03-31 | 2011-03-16 | Verfahren zum ansteuern einer anzahl an modulen |
Country Status (7)
Country | Link |
---|---|
US (1) | US9281803B2 (de) |
EP (1) | EP2553589B1 (de) |
JP (1) | JP5676740B2 (de) |
KR (1) | KR101751565B1 (de) |
CN (1) | CN102812449B (de) |
DE (1) | DE102010003558A1 (de) |
WO (1) | WO2011120806A1 (de) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106054758A (zh) * | 2016-08-19 | 2016-10-26 | 上海鲍麦克斯电子科技有限公司 | 一种实现多输入多输出的控制系统及方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102008000561A1 (de) * | 2008-03-07 | 2009-09-10 | Robert Bosch Gmbh | Kommunikationssystem mit einem CAN-Bus und Verfahren zum Betreiben eines solchen Kommunikationssystems |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60135777A (ja) * | 1983-12-24 | 1985-07-19 | Fanuc Ltd | 制御装置の試験方式 |
JPS6232251A (ja) | 1985-05-21 | 1987-02-12 | Nippon Denso Co Ltd | 燃料噴射量制御装置 |
JPS62186034A (ja) | 1986-02-10 | 1987-08-14 | Toyota Motor Corp | 内燃機関の燃料噴射装置 |
JP2583055B2 (ja) * | 1987-05-29 | 1997-02-19 | 株式会社 アドバンテスト | Icテストシステム |
US5448977A (en) | 1993-12-17 | 1995-09-12 | Ford Motor Company | Fuel injector pulsewidth compensation for variations in injection pressure and temperature |
JP3291914B2 (ja) | 1994-06-24 | 2002-06-17 | 国産電機株式会社 | 内燃機関用燃料噴射制御装置 |
JPH08210168A (ja) | 1995-02-02 | 1996-08-20 | Sanshin Ind Co Ltd | エンジンの運転制御装置 |
JPH08210209A (ja) | 1995-02-06 | 1996-08-20 | Zexel Corp | 高圧燃料噴射装置 |
JP3855471B2 (ja) | 1998-07-01 | 2006-12-13 | いすゞ自動車株式会社 | コモンレール式燃料噴射装置 |
JP2001098991A (ja) | 1999-09-30 | 2001-04-10 | Mazda Motor Corp | 火花点火式直噴エンジンの燃料制御装置 |
US6990569B2 (en) * | 2001-10-25 | 2006-01-24 | Arm Limited | Handling problematic events in a data processing apparatus |
JP4089244B2 (ja) | 2002-03-01 | 2008-05-28 | 株式会社デンソー | 内燃機関用噴射量制御装置 |
JP4430281B2 (ja) | 2002-04-23 | 2010-03-10 | トヨタ自動車株式会社 | データマップ作成方法、データマップ作成用情報記録媒体作成方法及び装置 |
US7096139B2 (en) * | 2004-02-17 | 2006-08-22 | Advantest Corporation | Testing apparatus |
US7191079B2 (en) * | 2004-03-23 | 2007-03-13 | Tektronix, Inc. | Oscilloscope having advanced triggering capability |
US7716528B2 (en) | 2004-09-07 | 2010-05-11 | Broadcom Corporation | Method and system for configurable trigger logic for hardware bug workaround in integrated circuits |
JP2007132315A (ja) | 2005-11-14 | 2007-05-31 | Denso Corp | 燃料噴射制御装置 |
JP4424395B2 (ja) | 2007-08-31 | 2010-03-03 | 株式会社デンソー | 内燃機関の燃料噴射制御装置 |
JP4501974B2 (ja) | 2007-08-31 | 2010-07-14 | 株式会社デンソー | 内燃機関の燃料噴射制御装置 |
JP5077012B2 (ja) | 2008-03-26 | 2012-11-21 | トヨタ自動車株式会社 | 内燃機関の燃料噴射制御装置 |
JP2010180824A (ja) | 2009-02-06 | 2010-08-19 | Honda Motor Co Ltd | 燃料噴射制御装置 |
-
2010
- 2010-03-31 DE DE201010003558 patent/DE102010003558A1/de not_active Withdrawn
-
2011
- 2011-03-16 US US13/637,727 patent/US9281803B2/en active Active
- 2011-03-16 JP JP2013501730A patent/JP5676740B2/ja active Active
- 2011-03-16 KR KR1020127025708A patent/KR101751565B1/ko active IP Right Grant
- 2011-03-16 EP EP20110709918 patent/EP2553589B1/de active Active
- 2011-03-16 WO PCT/EP2011/053973 patent/WO2011120806A1/de active Application Filing
- 2011-03-16 CN CN201180016815.3A patent/CN102812449B/zh active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102008000561A1 (de) * | 2008-03-07 | 2009-09-10 | Robert Bosch Gmbh | Kommunikationssystem mit einem CAN-Bus und Verfahren zum Betreiben eines solchen Kommunikationssystems |
Non-Patent Citations (1)
Title |
---|
HARTWICH F ET AL: "CAN Network with Time Triggered Communication", INTERNET CITATION, 16 June 2001 (2001-06-16), XP002242379, Retrieved from the Internet <URL:http://web.archive.org/web/20010615082442/http://www.can.bosch.com/do cu/CiA2000Paper_2.pdf> [retrieved on 20030523] * |
Also Published As
Publication number | Publication date |
---|---|
US20130140909A1 (en) | 2013-06-06 |
KR101751565B1 (ko) | 2017-06-27 |
CN102812449B (zh) | 2016-08-17 |
DE102010003558A1 (de) | 2011-10-06 |
JP2013528842A (ja) | 2013-07-11 |
KR20130022402A (ko) | 2013-03-06 |
CN102812449A (zh) | 2012-12-05 |
JP5676740B2 (ja) | 2015-02-25 |
US9281803B2 (en) | 2016-03-08 |
EP2553589B1 (de) | 2014-11-05 |
EP2553589A1 (de) | 2013-02-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP1495545B1 (de) | Verfahren und vorrichtung zur funktionsprüfung eines analog-digital-wandlers sowie analog-digital-wandler | |
DE2450528C3 (de) | Einrichtung zur Anpassung von Taktsignalen Informationssignale auf Übertragungsleitungen mit unterschiedlichen Laufzeitverhältnissen | |
DE102007044803A1 (de) | Schaltungsanordnung zur Signalaufnahme und -erzeugung sowie Verfahren zum Betreiben dieser Schaltungsanordnung | |
DE102013100465A1 (de) | Mikroprozessor-gesteuerte Steuerungseinrichtung für eine Spritzgiessanlage | |
DE69301632T2 (de) | Verfahren zur Prüfung der Funktionsfähigkeit einer ASIC-Schaltung und darauf bezogene ASIC-Schaltung | |
EP1947568A1 (de) | Verfahren zur Beobachtung eines Steuergeräts | |
EP2707999B1 (de) | Signalverarbeitungssystem und verfahren zur verarbeitung von signalen in einem busknoten | |
DE102010003532A1 (de) | Timermodul und Verfahren zur Überprüfung eines Ausgangssignals | |
EP2553589B1 (de) | Verfahren zum ansteuern einer anzahl an modulen | |
DE60221515T2 (de) | Speichersystem für schleifenbeschleunigung nach wunsch | |
DE102018200379B4 (de) | Sensoranordnung und Verfahren zum Betreiben einer Sensoranordnung | |
DE2647367A1 (de) | Redundante prozessteueranordnung | |
WO2017084779A1 (de) | Verfahren zum betreiben eines steuergeräts sowie zum externen bypassing eingerichtetes steuergerät | |
DE102015213834A1 (de) | Endstufenbaustein | |
DE3827959C2 (de) | ||
DE3429078C2 (de) | ||
DE1914576C3 (de) | Programmgesteuerte Datenverar beitungsanlage, insbesondere fur die Abwicklung von Vermittlungsvorgangen in einer Fernsprechvermittlung | |
DE102018208861A1 (de) | Verfahren zum Plausibilisieren eines Sensorsignals | |
WO2019001836A1 (de) | Integrierte schaltung und asic | |
DE102022131564A1 (de) | Steuervorrichtung für ein Zonensteuergerät, Zonensteuergerät und Verfahren zum Betreiben eines Zonensteuergeräts | |
DE2203526C2 (de) | Anordnung zum Auswerten von Signalen unterschiedlicher Priorität | |
DE2525438A1 (de) | Ueberwachungsanordnung zur ueberwachung zentraler einrichtungen | |
DE10308460A1 (de) | Elektronisches System und elektronisches Gesamtsystem zum Ansteuern einer Brennkraftmaschine | |
DE202021100221U1 (de) | Gerät zum Aufbau der programmierbaren digitalen Mikroprozessor-Systeme | |
DE4039407A1 (de) | Verfahren zur modellierung digitaler bauelemente innerhalb eines simulationsmodells und anordnung zur durchfuehrung des verfahrens |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 201180016815.3 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 11709918 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2011709918 Country of ref document: EP |
|
ENP | Entry into the national phase |
Ref document number: 20127025708 Country of ref document: KR Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2013501730 Country of ref document: JP Ref document number: 8520/DELNP/2012 Country of ref document: IN |
|
WWE | Wipo information: entry into national phase |
Ref document number: 13637727 Country of ref document: US |