WO2011111305A1 - Procédé permettant d'exciter un circuit logique non volatil pour qu'il se comporte comme un circuit ou exclusif - Google Patents

Procédé permettant d'exciter un circuit logique non volatil pour qu'il se comporte comme un circuit ou exclusif Download PDF

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Publication number
WO2011111305A1
WO2011111305A1 PCT/JP2011/000801 JP2011000801W WO2011111305A1 WO 2011111305 A1 WO2011111305 A1 WO 2011111305A1 JP 2011000801 W JP2011000801 W JP 2011000801W WO 2011111305 A1 WO2011111305 A1 WO 2011111305A1
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electrode
input
state
input electrode
logic circuit
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PCT/JP2011/000801
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English (en)
Japanese (ja)
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幸広 金子
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パナソニック株式会社
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Priority to CN201180007856.6A priority Critical patent/CN102742163B/zh
Priority to JP2011513781A priority patent/JP4762379B1/ja
Priority to US13/222,782 priority patent/US8199555B2/en
Publication of WO2011111305A1 publication Critical patent/WO2011111305A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region

Definitions

  • the present invention relates to a method for driving a nonvolatile logic circuit as an exclusive OR circuit.
  • FIGS. 1 to 5 of Patent Document 1 are FIGS. 1 to 5 of Patent Document 1.
  • FIG. 8 to 12 are FIGS. 1 to 5 of Patent Document 1.
  • the semiconductor memory device 10 includes a laminated film composed of a ferroelectric layer 13 and a semiconductor layer 14, and the first electrode 12 is formed on the ferroelectric layer 13 side of the laminated film.
  • a plurality of second electrodes 15a to 15c are formed on the semiconductor layer 14 side of the stacked film. Note that these layers are formed on the substrate 11.
  • FIG. 9A and 9B are diagrams showing an initial state of the semiconductor memory device, where FIG. 9A is a cross-sectional perspective view, and FIG.
  • the semiconductor layer 14 when an n-type semiconductor is used for the semiconductor layer 14, all the polarizations 16 are in the same direction so that the polarization 16 of the ferroelectric layer 13 is coupled with electrons (majority carriers) of the semiconductor layer 14 in the initial state. Make a state of facing. At this time, two-dimensional electrons 17 induced by the polarization charge of the ferroelectric layer 13 are accumulated near the interface between the semiconductor layer 14 and the ferroelectric layer 13, and the semiconductor layer 14 is in a low resistance state. Yes. Therefore, since the semiconductor layer 14 behaves as a passage through which electricity flows like the metal electrode, the semiconductor layer 14 can be regarded as a uniform electrode. At this time, as shown in FIG. 9B, the conductive state between the semiconductor layer 14 and the second electrodes 15a to 15c is short-circuited.
  • a relatively high bias voltage is applied to the arbitrarily selected second electrode 15c with respect to the first electrode 12, so that the second electrode 15c
  • the polarization is directed in the direction in which electrons in the semiconductor layer 14 are eliminated, so that the region of the semiconductor layer 14 in the portion where the second electrode 15c is formed Only (A) is depleted 18 and enters a high resistance state.
  • FIG. 10B the conductive state between the semiconductor layer 14 and the second electrode 15c is open.
  • FIG. 11A and 11B are diagrams showing two resistance states of the semiconductor layer 14 in a portion where the second electrode 15 is formed.
  • FIG. 11A is a cross-sectional view in a low resistance state
  • FIG. 11B is a high resistance state.
  • FIG. 6C is a table showing sheet resistance values between the semiconductor layer 14 and the second electrode 15. As shown in this table, each region (A) of the semiconductor layer 14 in the portion where the second electrodes 15a to 15c are formed has two states with different sheet resistance values due to the polarization assist effect of the ferroelectric layer 13. Can take.
  • FIG. 12 is a diagram showing a result of measuring the resistance value of the semiconductor layer 14 by a four-terminal method, where (a) is a measurement diagram in a low resistance state in which two-dimensional electrons are accumulated, and (b) A measurement diagram in a high resistance state in which two-dimensional electrons are excluded, (c) is a table showing the respective measurement results. As shown in this table, the sheet resistance value of the semiconductor layer 14 in the low resistance state is approximately 1 ⁇ 10 3 ⁇ / ⁇ or less, and the sheet resistance value of the semiconductor layer 14 in the high resistance state is approximately 1 ⁇ 10 6. It was ⁇ / ⁇ or more.
  • Patent Document 1 paragraph numbers [0057] and [0062] to [0067] of Patent Document 1. This corresponds to paragraph numbers 0028 and 0033 to 0038 of Japanese Patent Laid-Open No. 2009-099606.
  • An object of the present invention is to provide a novel method for driving a nonvolatile logic circuit as an exclusive OR circuit using the switching of resistance states shown in FIGS.
  • the method of the present invention is a method for driving a non-volatile logic circuit, and includes the following steps (a) to (c): Preparing the non-volatile logic circuit (a)
  • the nonvolatile logic circuit includes a control electrode, a ferroelectric film, a semiconductor film, and an electrode group, The control electrode, the ferroelectric film, the semiconductor film, and the electrode group are laminated in this order,
  • the electrode group includes a power electrode, an output electrode, a first input electrode, a second input electrode, a third input electrode, and a fourth input electrode,
  • the X direction, the Y direction, and the Z direction are the longitudinal direction of the ferroelectric film, the direction orthogonal to the longitudinal direction, and the stacking direction, respectively.
  • the voltage Vin is changed between the first input electrode, the second input electrode, the third input electrode, and the fourth input during the steps (a) and (b).
  • a step (d) of resetting the nonvolatile logic circuit by applying a voltage Vreset (where Vreset> Vin) to the control electrode and applying a voltage Vreset to the control electrode.
  • a first input signal that is either true or false is input to the first input electrode, and either the true or false is input to the second input electrode.
  • the second input signal is input, the negative of the second input signal is input to the third input electrode, and the negative of the first input signal is input to the fourth input electrode.
  • the high resistance state and the low resistance state correspond to false and true of exclusive OR based on the first input signal and the second input signal, respectively.
  • the present invention provides a novel method for driving a nonvolatile logic circuit as an exclusive OR circuit.
  • FIG. 1A shows a top view of the nonvolatile logic circuit 20 according to the first embodiment.
  • FIG. 1B is a cross-sectional view taken along the line A-A ′ of the nonvolatile logic circuit 20 according to the first embodiment.
  • FIG. 2 shows the relationship between the input electrodes 17a to 17d and the first and second input signals in the first embodiment.
  • FIG. 3 shows a truth table in the first embodiment.
  • FIG. 4 is a table showing the potentials of the input electrodes 17a to 17d at the time of writing.
  • FIG. 5A shows a top view of the input electrodes 17a to 17d in the first state.
  • FIG. 5B shows a top view of the input electrodes 17a to 17d in the second state.
  • FIG. 5C shows a top view of the input electrodes 17a to 17d in the third state.
  • FIG. 5D shows a top view of the input electrodes 17a to 17d in the fourth state.
  • FIG. 6 shows the polarization state of the ferroelectric film 13 and the state of the semiconductor film 14 when ⁇ 10 V and 10 V are applied to the input electrodes 17 a to 17 d.
  • FIG. 7 shows the resistance values calculated in the first state to the fourth state of Example 1.
  • FIG. 8 is FIG.
  • FIG. 9 is FIG. 2 of Patent Document 1.
  • FIG. 10 is FIG. 3 of Patent Document 1.
  • FIG. 11 is FIG. 4 of Patent Document 1.
  • FIG. FIG. 12 is FIG. 5 of Patent Document 1.
  • FIG. 1A is a top view of the nonvolatile logic circuit in the first embodiment.
  • FIG. 1B is a cross-sectional view taken along the line AA ′.
  • the nonvolatile logic circuit 20 includes a substrate 11, a control electrode 12, a ferroelectric film 13, a semiconductor film 14, and an electrode group.
  • the control electrode 12, the ferroelectric film 13, the semiconductor film 14, and the electrode group are stacked in this order.
  • the electrode group includes a power electrode 15, an output electrode 16, a first input electrode 17a, a second input electrode 17b, a third input electrode 17c, and a fourth input electrode 17d.
  • the X direction, the Y direction, and the Z direction are respectively the longitudinal direction of the ferroelectric film 13, the direction orthogonal to the longitudinal direction, and the stacking direction. Means.
  • the first input electrode 17a, the second input electrode 17b, the third input electrode 17c, and the fourth input electrode 17d are sandwiched between the power supply electrode 15 and the output electrode 16.
  • the first input electrode 17a is sandwiched between the power supply electrode 15 and the third input electrode 17c along the X direction.
  • the third input electrode 17c is sandwiched between the first input electrode 17a and the output electrode 16.
  • the second input electrode 17b is sandwiched between the power supply electrode 15 and the fourth input electrode 17d.
  • the fourth input electrode 17d is sandwiched between the second input electrode 17b and the output electrode 16.
  • the first input electrode 17a is adjacent to the second input electrode 17b along the Y direction.
  • the third input electrode 17c is adjacent to the fourth input electrode 17d.
  • the current flowing through the semiconductor film 14 is controlled according to the direction of polarization in the ferroelectric film 13. That is, when the polarization of the ferroelectric film 13 coincides with the + Z direction, the electrons induced in the semiconductor film 14 cause the semiconductor film 14 to have a low resistance. On the other hand, when the polarization coincides with the ⁇ Z direction, the electrons removed from the semiconductor film 14 cause the semiconductor film 14 to have a high resistance.
  • a voltage is applied between the input electrodes 17a to 17d and the control electrode 12, and the resistance value of the semiconductor film 14 is controlled. Thereby, the resistance value between the power supply electrode 15 and the output electrode 16 can be changed.
  • the non-volatile logic circuit 20 performs exclusive OR of 2 inputs and 1 output. As shown in FIG. 2, the first input signal, the second input signal, the negation of the second input signal, and the negation of the first input signal are respectively the first input electrode 17a, the second input electrode 17b, and the third input. The signal is input to the electrode 17c and the fourth input electrode 17d. Based on the truth table shown in FIG. 3, an exclusive OR execution result is output.
  • FIG. 4 shows the potentials of the input electrodes 17a to 17d at the time of writing.
  • a voltage of ⁇ 10V is input as “1” shown in FIG.
  • a voltage of 10V is input as “0”.
  • the voltage of the control electrode 12 is kept constant and is preferably 0V.
  • FIG. 5A shows a top view of the input electrodes 17a to 17d in the first state.
  • FIG. 5B shows a top view of the input electrodes 17a to 17d in the second state.
  • FIG. 5C shows a top view of the input electrodes 17a to 17d in the third state.
  • FIG. 5D shows a top view of the input electrodes 17a to 17d in the fourth state.
  • FIG. 6 shows the polarization state of the ferroelectric film 13 and the state of the semiconductor film 14 when ⁇ 10 V and 10 V are applied to the input electrodes 17 a to 17 d.
  • the semiconductor 31 located under the input electrode 33 to which ⁇ 10 V is applied has a low resistance due to the accumulation of electrons generated by the polarization 30 a of the ferroelectric 13.
  • the semiconductor 32 located under the input electrode 34 to which 10 V is applied has a high resistance due to the retreat of electrons caused by the polarization 30 b of the ferroelectric 13.
  • a reset operation is performed before writing.
  • the voltage Vin is applied to the input electrodes 17a to 17d, and the voltage Vreset that satisfies the relationship Vin ⁇ Vreset is applied to the control electrode 12. More specifically, it is preferable that 10 V is applied to the control electrode 12 while 0 V is applied to the input electrodes 17a to 17d. Thereby, all the polarizations of the ferroelectric film 13 are set upward.
  • This reset operation enables driving of the non-volatile logic circuit 20 with good reproducibility.
  • V1, Va, Vb, Vc, and Vd are applied to the control electrode 12, the first input electrode 17a, the second input electrode 17b, the third input electrode 17c, and the fourth input electrode 17d, respectively.
  • Each portion of the ferroelectric film 13 located under the input electrodes 17a to 17d is polarized. This polarization causes each portion of the semiconductor film 14 located under the input electrodes 17a to 17d to be in a high resistance state or a low resistance state.
  • One state selected from the first to fourth states is written to the nonvolatile logic circuit 20.
  • V1> Vb, V1 ⁇ Vc, and V1 ⁇ Vd More specifically, while V1 is held at 0V, ⁇ 10V Va, ⁇ 10V Vb, + 10V Vc, and + 10V Vd are applied.
  • true (1), true (1), false (0), and false (0) are The signals are input to the fourth input electrodes 17a to 17d, respectively.
  • false (0), true (1), false (0), and true (1) are the first input electrode 17a, the second input electrode 17b, the third input electrode 17c, and the fourth input. Each is input to the electrode 17d.
  • true (1), false (0), true (1), and false (0) are the first input electrode 17a, the second input electrode 17b, the third input electrode 17c, and the fourth input. Each is input to the electrode 17d.
  • false (0), false (0), true (1), and true (1) are the first input electrode 17a, the second input electrode 17b, the third input electrode 17c, and the fourth input. Each is input to the electrode 17d.
  • the resistance between the power electrode 15 and the output electrode 16 is high. In the second state and the third state, the resistance between the power supply electrode 15 and the output electrode 16 is low.
  • the first input signal 17a is either true or false. Is entered.
  • a second input signal that is either true or false is input to the second input electrode 17b.
  • the negative of the second input signal is input to the third input electrode 17c.
  • the negative of the first input signal is input to the fourth input electrode 17d.
  • the potential difference applied between the power supply electrode 15 and the output electrode 16 is preferably 1/5 or less of the voltage applied to the input electrodes 17a to 17d at the time of writing.
  • An example of the potential difference between the power supply electrode 15 and the output electrode 16 is 0.1V.
  • the resistance value is determined according to the current value. That is, based on the measured current, it is determined whether the nonvolatile logic circuit 20 has a high resistance state or a low resistance state. As described above, the first state and the fourth state correspond to the high resistance state. The second state and the third state correspond to the low resistance state.
  • the high resistance state and the low resistance state respectively correspond to false and true of exclusive OR based on the first input signal and the second input signal.
  • the nonvolatile logic circuit 20 functions as a nonvolatile exclusive OR circuit.
  • a titanium film having a thickness of 5 nm and a platinum film having a thickness of 30 nm were formed in this order by using an electron gun vapor deposition method. Further, a SrRuO 3 (hereinafter, SRO) film having a thickness of 10 nm was formed by a pulse laser deposition method. In this way, the control electrode 12 was formed on the silicon substrate 11.
  • SRO SrRuO 3
  • a ferroelectric film 13 made of Pb (Zr, Ti) O 3 having a thickness of 450 nm was formed in a PLD chamber using a pulse laser deposition (PLD) method.
  • the temperature of the substrate was set to 400 ° C., and the semiconductor film 14 made of ZnO having a thickness of 30 nm was formed in the PLD chamber.
  • a resist pattern was formed on the semiconductor film 14 by photolithography. Thereafter, the portion of the semiconductor film 14 not covered with the resist (the portion of the semiconductor film 14 located between the cells) was removed by etching using nitric acid.
  • a resist was formed on the semiconductor film 14 by photolithography, and unnecessary portions of the resist were removed.
  • a Ti film having a thickness of 5 nm and a Pt film having a thickness of 30 nm were formed thereon by an electron gun vapor deposition method.
  • the resist was removed by the lift-off method, and the power supply electrode 15, the output electrode 16, the logic setting electrodes 18a to 18d, and the input electrodes 17a to 17d were formed.
  • the obtained non-volatile logic circuit 20 had input electrodes 17a to 17d of 100 micrometers square and an electrode interval of 10 micrometers.
  • One state selected from the first state to the fourth state based on FIGS. 4 and 5 is written in the nonvolatile logic circuit 20. Thereafter, a potential difference of 0.1 V was applied between the power supply electrode 15 and the output electrode 16, and the resistance value of the nonvolatile logic circuit 20 was calculated based on the current flowing between the power supply electrode 15 and the output electrode 16.
  • FIG. 7 shows the resistance values calculated in the first state to the fourth state.
  • the nonvolatile logic circuit 20 in the first state or the fourth state, the nonvolatile logic circuit 20 has a high resistance value.
  • the nonvolatile logic circuit 20 in the second state or the third state, the nonvolatile logic circuit 20 has a low resistance value.
  • control electrode 12 was provided with a laminated film of SRO / Pt / Ti.
  • the electrodes 15 to 17 were provided with a Pt / Ti laminated film. Other materials can also be used.
  • ferroelectric film 13 Another example of the material of the ferroelectric film 13 is Sr (Bi, Ta) O x or BiTiO x .
  • Another example of the material of the semiconductor film 14 is GaN or InGaZnO x .
  • the present invention provides a novel method for driving a nonvolatile logic circuit as an exclusive OR circuit.
  • Substrate 12 Control electrode 13 Ferroelectric film 14 Semiconductor film 15 Power supply electrode 16 Output electrode 17a First input electrode 17b Second input electrode 17c Third input electrode 17d Fourth input electrode 20

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

En contact avec une couche semi-conductrice (14), le circuit logique non volatil ci-décrit possède une électrode d'alimentation électrique (15), une électrode de sortie (16), et, dans la région située entre elles, une matrice d'électrodes d'entrée 2 × 2 (17). Ledit circuit logique non volatil est également doté d'une électrode de commande (11) formée sur une surface principale du semi-conducteur, une couche ferroélectrique (13) étant placée entre elles. Les signaux appliqués aux quatre électrodes d'entrée consistent en un premier signal d'entrée, un second signal d'entrée, la négation logique du premier signal, et la négation logique du second signal. Pour chaque paire d'électrodes voisines le long de l'axe qui relie l'électrode d'alimentation électrique et l'électrode de sortie, les signaux appliqués sont respectivement l'un des signaux d'entrée et la négation logique de l'autre signal d'entrée. Pour chaque paire d'électrodes voisines en diagonale, les signaux appliqués sont respectivement l'un des signaux d'entrée et la négation logique de ce même signal d'entrée.
PCT/JP2011/000801 2010-03-10 2011-02-14 Procédé permettant d'exciter un circuit logique non volatil pour qu'il se comporte comme un circuit ou exclusif WO2011111305A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201180007856.6A CN102742163B (zh) 2010-03-10 2011-02-14 驱动非易失性逻辑电路作为“异”电路的方法
JP2011513781A JP4762379B1 (ja) 2010-03-10 2011-02-14 排他的論理和回路として不揮発論理回路を駆動する方法
US13/222,782 US8199555B2 (en) 2010-03-10 2011-08-31 Nonvolatile logic circuit and a method for operating the same as an exclusive-OR (XOR) circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010-052665 2010-03-10
JP2010052665 2010-03-10

Related Child Applications (1)

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US13/222,782 Continuation US8199555B2 (en) 2010-03-10 2011-08-31 Nonvolatile logic circuit and a method for operating the same as an exclusive-OR (XOR) circuit

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US (1) US8199555B2 (fr)
JP (1) JP4762379B1 (fr)
CN (1) CN102742163B (fr)
WO (1) WO2011111305A1 (fr)

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WO2013118449A1 (fr) * 2012-02-07 2013-08-15 パナソニック株式会社 Procédé de commande d'un dispositif semi-conducteur non volatile
US9036394B2 (en) 2012-06-04 2015-05-19 Panasonic Intellectual Property Management Co., Ltd. Method of driving nonvolatile semiconductor device
CN109302175A (zh) * 2017-07-25 2019-02-01 原子能与替代能源委员会 电容式逻辑单元

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WO2012029211A1 (fr) * 2010-09-02 2012-03-08 パナソニック株式会社 Procédé d'excitation d'un circuit logique non volatil
US8427202B2 (en) * 2010-11-04 2013-04-23 Panasonic Corporation Nonvolatile logic circuit and a method for operating the same
CN108493255B (zh) * 2018-02-26 2021-03-02 上海电力学院 一种电场可控的二维材料肖特基二极管
KR102652757B1 (ko) * 2018-11-02 2024-04-02 브이메모리 주식회사 변동 저저항 라인 비휘발성 메모리 소자 및 이의 동작 방법
KR102059485B1 (ko) * 2018-12-31 2019-12-27 브이메모리 주식회사 변동 저저항 영역 기반 메모리 소자 및 이의 제어 방법
KR102218663B1 (ko) * 2019-06-27 2021-02-23 브이메모리 주식회사 전기장을 이용한 전류 경로 제어 방법 및 전자 소자
KR102272521B1 (ko) * 2019-08-14 2021-07-06 브이메모리 주식회사 변동 저저항 영역 기반 전자 소자, 이의 제조 방법 및 이의 제어 방법
KR102642566B1 (ko) * 2019-08-14 2024-03-04 브이메모리 주식회사 변동 저저항 영역 기반 전자 소자 및 이의 제어 방법
KR102642562B1 (ko) * 2019-08-14 2024-03-04 브이메모리 주식회사 변동 저저항 영역 기반 전자 소자 및 이의 제어 방법
KR102246249B1 (ko) * 2019-08-14 2021-04-30 브이메모리 주식회사 변동 저저항 영역 기반 전자 소자 및 이의 제어 방법
KR102246248B1 (ko) * 2019-08-14 2021-04-30 브이메모리 주식회사 변동 저저항 영역 기반 전자 소자 및 이의 제어 방법
KR102271382B1 (ko) * 2019-12-10 2021-07-01 브이메모리 주식회사 변동 저저항 라인 기반 전자 소자 및 이의 제어 방법

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WO2004086625A1 (fr) * 2003-03-26 2004-10-07 Japan Science And Technology Agency Circuit logique reconfigurable utilisant un transistor ayant une caracteristique de transmission dependant du spin
US20090097299A1 (en) * 2007-10-12 2009-04-16 Hiroyuki Tanaka Semiconductor memory device, method for fabricating the same and semiconductor switching device

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WO2013118449A1 (fr) * 2012-02-07 2013-08-15 パナソニック株式会社 Procédé de commande d'un dispositif semi-conducteur non volatile
JP5406415B1 (ja) * 2012-02-07 2014-02-05 パナソニック株式会社 不揮発性半導体装置を駆動する方法
US8830723B2 (en) 2012-02-07 2014-09-09 Panasonic Corporation Method of driving nonvolatile semiconductor device
US9036394B2 (en) 2012-06-04 2015-05-19 Panasonic Intellectual Property Management Co., Ltd. Method of driving nonvolatile semiconductor device
CN109302175A (zh) * 2017-07-25 2019-02-01 原子能与替代能源委员会 电容式逻辑单元
CN109302175B (zh) * 2017-07-25 2024-03-01 原子能与替代能源委员会 电容式逻辑单元

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CN102742163B (zh) 2014-12-03
JP4762379B1 (ja) 2011-08-31

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