WO2011104795A1 - Tranche de silicium polycristallin - Google Patents

Tranche de silicium polycristallin Download PDF

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Publication number
WO2011104795A1
WO2011104795A1 PCT/JP2010/006734 JP2010006734W WO2011104795A1 WO 2011104795 A1 WO2011104795 A1 WO 2011104795A1 JP 2010006734 W JP2010006734 W JP 2010006734W WO 2011104795 A1 WO2011104795 A1 WO 2011104795A1
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Prior art keywords
wafer
polycrystalline silicon
ingot
crystal
silicon wafer
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PCT/JP2010/006734
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English (en)
Japanese (ja)
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渉 杉村
貴裕 安部
貴文 北村
竜介 横山
藤原　俊幸
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株式会社Sumco
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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B15/00—Single-crystal growth by pulling from a melt, e.g. Czochralski method
    • C30B15/08—Downward pulling
    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01B—NON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
    • C01B33/00—Silicon; Compounds thereof
    • C01B33/02—Silicon
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B28/00—Production of homogeneous polycrystalline material with defined structure
    • C30B28/04—Production of homogeneous polycrystalline material with defined structure from liquids
    • C30B28/10—Production of homogeneous polycrystalline material with defined structure from liquids by pulling from a melt
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0368—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including polycrystalline semiconductors
    • H01L31/03682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including polycrystalline semiconductors including only elements of Group IV of the Periodic System
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/546—Polycrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a polycrystalline silicon wafer used for a solar cell, and more particularly to a polycrystalline silicon wafer that can obtain a high photoelectric conversion efficiency when applied to a solar cell and has few subgrain boundaries.
  • subgrain boundaries refer to a plurality of grains partitioned by a plurality of networks formed by proliferating dislocations in a crystal grain.
  • Photovoltaic power generation is a power generation method in which solar energy is directly converted into electric power using a solar cell, and a polycrystalline silicon wafer is mainly used as a substrate of the solar cell.
  • a polycrystalline silicon wafer for solar cells is manufactured by slicing a unidirectionally solidified polycrystalline silicon ingot, and slicing the ingot. For this reason, in order to promote the spread of solar cells, it is necessary to secure the quality of the silicon wafer and reduce the cost, and it is required to manufacture a high-quality silicon ingot at a low cost in the previous stage.
  • an EMC method Electromagnetic Casting Method
  • an EMC method Electromagnetic Casting Method
  • FIG. 1 is a schematic diagram showing a configuration of a typical continuous casting apparatus (hereinafter referred to as “EMC furnace”) used in the EMC method.
  • the EMC furnace includes a chamber 1.
  • the chamber 1 is a water-cooled container having a double wall structure in which the inside is isolated from the outside air and maintained in an inert gas atmosphere suitable for casting.
  • a raw material supply device (not shown) is connected to the upper wall of the chamber 1 via an openable / closable shutter 2.
  • the chamber 1 is provided with an inert gas inlet 5 on the upper side wall and an exhaust port 6 on the lower side wall.
  • a bottomless cooling crucible 7, a high-frequency coil 8, an after heater 9 and a soaking tube 10 are arranged.
  • the bottomless cooling crucible 7 functions not only as a melting vessel but also as a mold, and is a rectangular tube made of metal (for example, copper) excellent in thermal conductivity and electrical conductivity, and is suspended in the chamber 1. ing.
  • the bottomless cooling crucible 7 is divided into a plurality of strip-shaped pieces in the circumferential direction, leaving the upper part, and is forcibly cooled by cooling water flowing inside.
  • the high-frequency coil 8 is concentrically provided with the bottomless cooling crucible 7 so as to surround the bottomless cooling crucible 7 and is connected to a power supply device (not shown).
  • a plurality of after-heaters 9 are connected to the bottom of the bottomless cooling crucible 7 so as to be concentric with the bottomless cooling crucible 7 and heat the ingot 3 pulled down from the bottomless cooling crucible 7 so that an appropriate temperature gradient in the axial direction thereof give.
  • the soaking tube 10 is arranged below the after heater 9 and concentrically with the after heater 9, and cools the ingot 3 to room temperature over a long period of time.
  • a raw material introduction pipe 11 is attached below the shutter 2 connected to the raw material supply device. As the shutter 2 is opened and closed, the granular or lump silicon raw material 12 is supplied from the raw material supply device into the raw material introduction tube 11 and charged into the bottomless cooling crucible 7.
  • a drawing port 4 for extracting the ingot 3 is provided below the soaking cylinder 10, and a gas seal portion is provided in the drawing port 4.
  • the ingot 3 is pulled down while being supported by a support base 15 that descends through the drawer port 4.
  • a plasma torch 14 is provided above the bottomless cooling crucible 7 so as to be movable up and down.
  • the plasma torch 14 is connected to one pole of a plasma power supply device (not shown), and the other pole is connected to the ingot 3 side.
  • the plasma torch 14 is inserted into the bottomless cooling crucible 7 in a lowered state.
  • the silicon raw material 12 is charged into the bottomless cooling crucible 7, an alternating current is applied to the high-frequency coil 8, and the lowered plasma torch 14 is energized.
  • an eddy current is generated in each piece due to electromagnetic induction by the high-frequency coil 8, and no The eddy current on the inner wall side of the bottom cooling crucible 7 generates a magnetic field in the bottomless cooling crucible 7.
  • the silicon raw material 12 in the bottomless cooling crucible 7 is melted by electromagnetic induction heating, and a molten silicon 13 is formed.
  • a plasma arc is generated between the plasma torch 14 and the silicon raw material 12, and further, the molten silicon 13, and the silicon raw material 12 is heated and melted by the Joule heat to reduce the burden of electromagnetic induction heating.
  • the molten silicon 13 is efficiently formed.
  • the molten silicon 13 has a force (in the normal direction of the surface of the molten silicon 13) due to the interaction between the magnetic field generated along with the eddy current on the inner wall of the bottomless cooling crucible 7 and the current generated on the surface of the molten silicon 13 ( Therefore, the bottomless cooling crucible 7 is held in a non-contact state.
  • the support 15 for supporting the molten silicon 13 is gradually lowered while melting the silicon raw material 12 in the bottomless cooling crucible 7, the induction magnetic field decreases as the distance from the lower end of the high-frequency coil 8 increases. The force is reduced, and further, the molten silicon 13 is solidified from the outer peripheral portion by the cooling from the bottomless cooling crucible 7.
  • the support base 15 is lowered, the silicon raw material 12 is continuously charged, and melting and solidification are continued, so that the molten silicon 13 is solidified in one direction and the ingot 3 is continuously cast. it can.
  • the present invention has been made in view of the above knowledge, and an object of the present invention is to provide a polycrystalline silicon wafer that can form a solar cell with less formation of subgrain boundaries and high photoelectric conversion efficiency.
  • the present inventors further studied the relationship between the amount of sub-boundary of the polycrystalline silicon wafer and the photoelectric conversion efficiency of the solar cell to which the polycrystalline silicon wafer was applied.
  • the polycrystalline silicon wafer is immersed in a mixed acid solution composed of 1.0% by volume of nitric acid, 10% by volume of acetic acid and 1.0% by volume of hydrofluoric acid. It has been found that good photoelectric conversion efficiency can be obtained when the grain boundary occupancy is 10% or less.
  • the present invention has been completed on the basis of this finding, and is immersed in a mixed acid solution composed of nitric acid, acetic acid and hydrofluoric acid, and when dislocations are manifested, the occupancy ratio of subgrain boundaries observed on the wafer surface
  • the gist of the present invention is a polycrystalline silicon wafer characterized in that is 10% or less.
  • occupation ratio refers to the ratio of the area occupied by the observed subgrain boundaries to the surface of the polycrystalline silicon wafer.
  • the occupancy ratio of the subgrain boundaries is 6% or less.
  • the polycrystalline silicon wafer of the present invention has a sub-grain boundary occupancy of 10% or less observed on the surface, high photoelectric conversion efficiency can be obtained by applying it to a solar cell.
  • FIG. 1 is a schematic diagram showing the configuration of an EMC furnace.
  • FIG. 2 is a schematic diagram showing the cooling behavior of molten silicon in a bottomless cooling crucible.
  • FIG. 3 is a cross-sectional photograph of an ingot cut perpendicular to the casting direction.
  • FIG. 4 is a schematic view of an ingot being heated by an after heater.
  • FIG. 5 is a defect image on the surface of the polycrystalline silicon wafer after the etching process
  • FIG. 5A shows an image observed by the image photographing apparatus
  • FIG. 5B shows a binarized image.
  • FIG. 6 is a schematic diagram showing the position where the ingot (EMC crystal) is divided.
  • FIG. 7 is a process diagram showing a procedure for preparing a sample for measuring photoelectric conversion efficiency.
  • FIG. 7 is a process diagram showing a procedure for preparing a sample for measuring photoelectric conversion efficiency.
  • FIG. 7A is a cut-out wafer
  • FIG. 7B is a wafer from which a damaged layer is removed
  • FIG. 7C Is a wafer on which an n + layer and a PSG film are formed
  • FIG. 7D is a wafer with a protective film
  • FIG. 7E is a wafer with silicon exposed
  • FIG. 7F is an aluminum electrode deposited.
  • 7 (g) shows a wafer coated with a silver electrode
  • FIG. 7 (h) shows a wafer fired with a silver electrode.
  • the occupancy ratio of the subgrain boundaries observed on the wafer surface is 10%. It is characterized by the following.
  • the present inventors examined a method for suppressing the formation of subgrain boundaries in an ingot being cast by the EMC method.
  • FIG. 2 is a schematic diagram showing the cooling behavior of molten silicon in a bottomless cooling crucible.
  • the ingot 3 is locally cooled with a bottomless cooling crucible 7 that is water-cooled. Therefore, in the ingot 3 coexisting with the molten silicon 13 (solid-liquid coexistence state), the temperature difference between the outer peripheral portion and the central portion inevitably increases, and the shape of the solid-liquid interface 16 is as shown in FIG. A large downward convex state is obtained.
  • the growth direction of the crystal grains forming the ingot 13 changes within the crystal plane (in the same plane perpendicular to the casting direction).
  • the vicinity of the outer periphery of the ingot 13 is nearly horizontal (perpendicular to the casting direction), and the closer to the center of the ingot 13, the closer to the vertical direction (the opposite direction to the casting direction).
  • fine crystals (chill crystals) having a small crystal grain size are formed, and columnar crystals having a slightly large crystal grain diameter are formed in the center.
  • FIG. 3 is a cross-sectional photograph of an ingot cut perpendicular to the casting direction.
  • the crystal grain growth direction changes in the crystal plane as described above, and as shown in the figure, microcrystals (chill crystals) are formed on the outer periphery of the ingot. And columnar crystals are formed at the center.
  • the solidified ingot 3 is slowly drawn downward in the growth axis, and after cooling into the soaking cylinder, is cooled to room temperature over a long period of time. Since crystal defects in the ingot 3 are formed during this cooling process, the crystal defects can be reduced by controlling the thermal history after solidification.
  • the main crystal defects present in the polycrystal are dislocations.
  • the dislocations generated in the crystal grains constituting the polycrystal propagate in the crystal grains using the thermal stress generated by the temperature difference between the inside and outside of the crystal grains as a driving force, and eventually stop at the crystal grain boundaries.
  • the dislocations generated in the crystal grains grow and eventually form a small network.
  • a plurality of dislocation networks are formed in crystal grains, a plurality of grains partitioned by dislocations are formed in one crystal grain, which is crystallographically called a sub-grain boundary.
  • the present inventors have found that the smaller the sub-boundary in the polycrystalline silicon wafer applied to the solar cell, the higher the photoelectric conversion efficiency. Therefore, in the following, a method for suppressing the generation of dislocations, which is a source of subgrain boundaries, will be considered.
  • FIG. 4 is a schematic diagram of an ingot being heated by an after heater. Since the sub-boundary is formed by the elementary process of dislocation propagation and multiplication, the sub-boundary is not formed unless the dislocation is propagated more than necessary.
  • the driving force for dislocation propagation during continuous casting of the ingot is thermal stress in the crystal plane. Therefore, if the temperature difference between the outer peripheral portion 3a and the central portion 3b of the ingot 3 after solidification shown in the figure is reduced, the thermal stress in the crystal plane can be reduced and the propagation of dislocations can be suppressed.
  • Another method for reducing the thermal stress in the crystal plane is to gradually cool a high-temperature zone (temperature range from the melting point of silicon to 1200 ° C.) near the solid-liquid interface where dislocations propagate easily, that is, the dislocation propagation speed is large.
  • a method is mentioned. Specifically, by controlling the temperature and calorific value of the afterheater used for temperature control near the solid-liquid interface of silicon, the surface temperature of the ingot is intentionally increased to reduce the thermal stress in the crystal plane. It is a method to do. According to this method, it is possible to reduce the thermal stress in the crystal plane and suppress the propagation of dislocations which are the subgrain boundary formation source.
  • Dislocations propagate even in a temperature zone below 1200 ° C, which is lower than the high temperature zone. However, in this temperature zone, the propagation speed of dislocation is smaller than that in the high temperature zone, and as a result, the effect of reducing defects by slow cooling cannot be obtained.
  • the temperature in the vicinity of the solid-liquid interface of silicon is a factor that is controlled as a measure for preventing leakage and reducing cracks, and is conventionally controlled to reduce crystal defects, particularly subgrain boundaries. There wasn't.
  • the following method can be applied to confirm the effect of reducing crystal defects, that is, to measure the occupancy ratio of subgrain boundaries on the surface of a polycrystalline silicon wafer cut out from an ingot.
  • FIG. 5 is a defect image on the surface of the polycrystalline silicon wafer after the etching process.
  • FIG. 5A shows an image observed by an image photographing apparatus
  • FIG. 5B shows a binarized image.
  • a polycrystalline silicon wafer is immersed in a mixed acid solution of nitric acid, acetic acid and hydrofluoric acid, which is an etching solution for polycrystalline applications, and an etching process is performed.
  • the polycrystalline silicon wafer subjected to the etching process is observed with an image photographing apparatus, as shown in FIG. 5A, the higher the defect density, the whiter the region, and the lower the region, the blacker the black.
  • this defect can be confirmed to be an aggregate of subgrain boundaries.
  • the image obtained by the image photographing device is binarized into black and white as shown in FIG. 5B, and the ratio of the white portion occupying the surface of the polycrystalline silicon wafer is calculated. Can be calculated.
  • EMC crystals Test Method Four ingots (hereinafter referred to as “EMC crystals”) were continuously cast by the EMC method.
  • the charge amount was 2.8 m
  • the casting length was 7 m
  • the target value of the resistance of the top portion was 1.5 ⁇ cm.
  • the set temperature of the after heater that controls the temperature near the solid-liquid interface of the crystal at the time of casting each EMC crystal was the value shown in Table 1.
  • FIG. 6 is a schematic diagram showing the position where the EMC crystal is divided. As shown in FIG. 6, the EMC crystal 20 was divided into two vertically and three horizontally on a plane perpendicular to the casting direction, thereby forming six divided crystals 21 having the casting direction as the longitudinal direction. In the present example, the test was performed using the divided crystal 21 at the position with hatching.
  • the crystal A was cast at a conventional temperature (1275 ° C.) with the set temperature of the after heater, using the manufacturing method as Method 1.
  • Crystals B to F were produced by methods 2 to 6, and the set temperatures of the after heater were 1270 ° C., 1265 ° C., 1260 ° C., 1280 ° C. and 1300 ° C., respectively. Wafers were cut out from the positions of 2500 mm from the bottom side of the crystals A to F thus cast.
  • the cut wafer was immersed in a mixed acid solution (1.0% by volume of nitric acid, 10% by volume of acetic acid and 1.0% by volume of hydrofluoric acid) for 1 minute. Thereafter, a defect image on the wafer surface as shown in FIG. 5 was obtained by an image photographing apparatus. By performing image analysis on the defect image on the wafer surface obtained by the image capturing apparatus, the occupancy ratio of the subgrain boundaries (white region in the defect image) was calculated.
  • wafers cut from crystals A to F were introduced into an actual solar cell process, and the photoelectric conversion efficiency was measured.
  • FIG. 7 is a process diagram showing a procedure for preparing a sample for measuring photoelectric conversion efficiency.
  • FIG. 7A is a cut wafer
  • FIG. 7B is a wafer from which a damaged layer is removed
  • FIG. ) Is a wafer on which an n + layer and a PSG film are formed
  • FIG. 8D is a wafer with a protective film
  • FIG. 8E is a wafer with silicon exposed
  • FIG. 8F is an aluminum electrode.
  • the vapor-deposited wafer FIG. 11G shows a wafer coated with a silver electrode
  • FIG. 11H shows a wafer fired with a silver electrode.
  • the damage layer 41 formed on the surface of the cut-out wafer 40 shown in FIG. 7A was removed using a cleaning solution as shown in FIG. 7B.
  • the wafer 40 was introduced into a phosphorus (P) deposition furnace, and phosphorus diffusion was performed using POCl 3 as a diffusion source.
  • P phosphorus
  • an n + layer 42 was formed on the surface layer of the wafer 40 and a PSG film 43 was formed on the surface as shown in FIG.
  • a protective film 44 was applied to the front surface of the wafer 40, and in this state, the n + layer 42 was removed by etching.
  • the back surface of the wafer 40 was exposed to silicon.
  • an aluminum (Al) electrode 45 is deposited on the exposed back surface of the wafer 40, and as shown in FIG. A silver (Ag) electrode 46 was applied.
  • the paste-like silver electrode 46 was baked by heat treatment. Thereby, since the filler contained in the silver electrode 46 penetrates the PSG film 43, the silver electrode 46 and the n + layer 42 are connected.
  • the reason why the aluminum electrode 45 on the back surface of the wafer 40 is formed first is to prevent junction breakdown due to silver diffusion.
  • the photoelectric conversion efficiency of the sample prepared by such a method was measured using a solar simulator and a curve tracer measuring instrument.
  • Test results Table 2 shows the occupancy ratio and photoelectric conversion efficiency of subgrain boundaries observed on the wafer surface for each EMC crystal.
  • crystals A to C, E, and F had a sub-boundary occupancy of 10% or less, and satisfied the conditions of the present invention in which the sub-boundary occupancy was 10% or less.
  • Crystal D had a sub-boundary occupancy of 12% and did not satisfy the conditions of the present invention.
  • the photoelectric conversion efficiency was an excellent value of 16.0% or more in the wafer cut from the crystals E and F, in which the subgrain boundary occupancy was 6% or less.
  • a high value of 16.3% was obtained in a wafer cut out from the crystal D having the smallest occupancy ratio of subgrain boundaries.
  • the value was as low as 12.9%.
  • the polycrystalline silicon wafer of the present invention has a sub-grain boundary occupancy of 10% or less observed on the surface, high photoelectric conversion efficiency can be obtained by applying it to a solar cell.

Abstract

L'invention concerne une tranche de silicium polycristallin à efficacité de conversion photo-électrique élevée lorsqu'on l'utilise dans une cellule solaire. La tranche précitée est caractérisée en ce que, si elle est immergée dans une solution d'acides mélangés comprenant de l'acide nitrique, de l'acide acétique et de l'acide hydrofluorique rendant les dislocations apparentes, les joints sous-granulaires observés ne représentent pas plus de 10% de la surface de la tranche. De préférence, les joints sous-granulaires ne représentent pas plus de 6% de la surface de la tranche, ce qui permet d'améliorer l'efficacité de conversion photo-électrique.
PCT/JP2010/006734 2010-02-24 2010-11-17 Tranche de silicium polycristallin WO2011104795A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016142611A1 (fr) * 2015-03-12 2016-09-15 Snecma Procédé de fabrication de pièces de turbomachine, ébauche et pièce finale

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JP2001019594A (ja) * 1999-07-01 2001-01-23 Sumitomo Sitix Of Amagasaki Inc シリコン連続鋳造方法
JP2007051026A (ja) * 2005-08-18 2007-03-01 Sumco Solar Corp シリコン多結晶の鋳造方法
WO2009130786A1 (fr) * 2008-04-25 2009-10-29 テイーアンドエス インベストメント リミテッド Procédé de fabrication d'une matière à base de silicium pour cellule solaire

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001019594A (ja) * 1999-07-01 2001-01-23 Sumitomo Sitix Of Amagasaki Inc シリコン連続鋳造方法
JP2007051026A (ja) * 2005-08-18 2007-03-01 Sumco Solar Corp シリコン多結晶の鋳造方法
WO2009130786A1 (fr) * 2008-04-25 2009-10-29 テイーアンドエス インベストメント リミテッド Procédé de fabrication d'une matière à base de silicium pour cellule solaire

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016142611A1 (fr) * 2015-03-12 2016-09-15 Snecma Procédé de fabrication de pièces de turbomachine, ébauche et pièce finale
FR3033508A1 (fr) * 2015-03-12 2016-09-16 Snecma Procede de fabrication de pieces de turbomachine, ebauche et piece finale
CN107405681A (zh) * 2015-03-12 2017-11-28 赛峰航空器发动机 用于制造涡轮机部件、坯件以及最终部件的方法
RU2712203C2 (ru) * 2015-03-12 2020-01-24 Сафран Эйркрафт Энджинз Способ изготовления компонентов турбомашины, заготовка и готовый компонент
US10760153B2 (en) 2015-03-12 2020-09-01 Safran Aircraft Engines Method for manufacturing turbomachine components, blank and final component
CN107405681B (zh) * 2015-03-12 2020-12-22 赛峰航空器发动机 用于制造涡轮机部件、坯件以及最终部件的方法

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