WO2011083719A1 - Procédé et appareil pour la gravure d'une partie de couche de surface d'une tranche de silicium, et procédé pour l'analyse de contamination de métal dans une tranche de silicium - Google Patents

Procédé et appareil pour la gravure d'une partie de couche de surface d'une tranche de silicium, et procédé pour l'analyse de contamination de métal dans une tranche de silicium Download PDF

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WO2011083719A1
WO2011083719A1 PCT/JP2010/073592 JP2010073592W WO2011083719A1 WO 2011083719 A1 WO2011083719 A1 WO 2011083719A1 JP 2010073592 W JP2010073592 W JP 2010073592W WO 2011083719 A1 WO2011083719 A1 WO 2011083719A1
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gas
etching
silicon wafer
acid
surface layer
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PCT/JP2010/073592
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English (en)
Japanese (ja)
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崇史 山下
モハマッド.ビー.シャバニー
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株式会社Sumco
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01NINVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N1/00Sampling; Preparing specimens for investigation
    • G01N1/28Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q
    • G01N1/32Polishing; Etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching

Definitions

  • the present invention relates to an etching method and an etching apparatus for a silicon wafer surface layer, and more specifically, a silicon wafer surface layer suitable as a method and apparatus for etching the surface layer of the silicon wafer in order to analyze metal contamination of the silicon wafer.
  • the present invention relates to an etching method and an etching apparatus. Furthermore, the present invention relates to a method for analyzing metal contamination of a silicon wafer using the etching method or the etching apparatus.
  • an atomic absorption photometer (AAS) or an inductively coupled plasma mass spectrometer is prepared by dissolving the silicon wafer surface layer with an acid solution and diluting or concentrating the acid solution.
  • a method of quantitative analysis by (ICP-MS) was used (hereinafter referred to as “liquid phase etching method”).
  • ICP-MS quantitative analysis by
  • the metal impurity concentration is diluted by a large amount of acid solution, the sensitivity decrease due to insufficient sensitivity or increase in analysis background due to carry-in contamination from the acid solution itself is high in the semiconductor manufacturing field where ultra-trace metal impurity evaluation is required. This hindered sensitivity analysis.
  • the silicon wafer surface layer is decomposed with acid vapor (etching gas), and the decomposition residue is collected and quantitatively analyzed by AAS or ICP-MS (hereinafter, “ (Referred to as Japanese Patent No. 3832204, the entire description of which is specifically incorporated herein by reference).
  • the above-mentioned gas phase etching method has been studied on the merits that a small amount of acid solution may be used for etching and the amount of contamination brought in from the acid solution itself is very small compared to liquid phase etching.
  • the vapor phase etching method has a very slow reaction rate between the acid (acid vapor) and the semiconductor substrate as compared with the liquid phase etching method. Therefore, there is a problem that the analysis sensitivity is low because the etching amount in a certain time is small. Although it is possible to increase the etching amount by performing an etching reaction for a long time, it takes a long time for the analysis, resulting in a significant decrease in productivity.
  • a first object of the present invention is to provide means for enabling high-sensitivity analysis by short-time etching processing in silicon wafer surface layer analysis by vapor phase etching.
  • an acid vapor obtained by vaporizing a mixed acid of hydrofluoric acid and nitric acid (that is, a mixed gas of hydrogen fluoride gas and nitric acid gas) is mainly used as an etching gas.
  • a mixed acid of hydrofluoric acid and nitric acid that is, a mixed gas of hydrogen fluoride gas and nitric acid gas
  • the present inventors have newly found that the reaction rate of gas phase decomposition can be greatly increased by mixing nitrogen oxide gas with the acid vapor. . This makes it possible to etch a quantity of silicon wafer that can be analyzed with high sensitivity even with an etching time equivalent to that of the conventional method. The inventors presume this reason as follows.
  • NOx gas nitrogen oxide gas
  • etching rate reaction rate of the gas phase decomposition
  • One embodiment of the present invention provides: A method for etching a silicon wafer surface layer portion, wherein the silicon wafer surface layer portion is etched by bringing the silicon wafer surface into contact with an etching gas, Using the mixed gas of hydrogen fluoride gas, nitric acid gas, and nitrogen oxide gas as the etching gas, It is about.
  • the etching method may include generating the nitrogen oxide gas and the nitric acid gas from a mixed acid of nitric acid and hydrofluoric acid containing silicon pieces (hereinafter referred to as “mixed acid A”).
  • the silicon piece may be a silicon wafer piece.
  • the hydrogen fluoride gas can be generated from a mixed acid of hydrofluoric acid and sulfuric acid (hereinafter referred to as “mixed acid B”) or hydrofluoric acid heated to 30 ° C. to 50 ° C.
  • mixed acid B a mixed acid of hydrofluoric acid and sulfuric acid
  • the mixed gas causes nitrogen oxide gas and nitric acid gas generated by bubbling a carrier gas to the mixed acid A to bubble the carrier gas to the mixed acid B or hydrofluoric acid heated to 30 ° C. to 50 ° C. It can prepare by mixing with the hydrogen fluoride gas generated by this.
  • the Si compound (Si residue) generated on the silicon wafer to be evaluated by the vapor phase etching reaction becomes a disturbing substance in the quantitative evaluation in AAS and ICP-MS and prevents accurate quantitative evaluation.
  • the detection sensitivity is insufficient as a method for analyzing metal contamination of silicon wafers that require high-sensitivity analysis of ultra-trace metal components.
  • a second object of the present invention is to provide means for analyzing with high sensitivity the metal impurities on the surface layer of the silicon wafer that adversely affect the device characteristics.
  • the present inventors can reduce Si residue by heating a silicon wafer from above and below in a reaction chamber in a gas phase etching method.
  • trace metal impurities in a silicon wafer can be analyzed with high sensitivity.
  • One embodiment of the present invention has been completed based on the above findings.
  • One embodiment of the present invention provides: An etching method for the surface layer of a silicon wafer, A silicon wafer surface layer portion is formed in a reaction chamber having a support base in which a silicon wafer is disposed on a support portion, and a closed space formed by closing an open portion on the support portion side on the support base with a closing member.
  • Etching Performing the etching by introducing an etching gas into the enclosed space and bringing the gas into contact with the silicon wafer surface; and During the etching, the inside of the enclosed space is heated by the heating means provided on the closing member, and the silicon wafer disposed on the support portion is heated by the heating means provided on the support base, Including the etching method, It is about.
  • the etching gas may include hydrogen fluoride gas, nitric acid gas, and nitrogen oxide gas.
  • the silicon wafer can be rotated in the circumferential direction.
  • the etching gas can be introduced in a state where the closed space is maintained in the range of atmospheric pressure to positive pressure.
  • the etching gas can be introduced by spraying an etching gas from a gas spray port provided at the tip of a cylindrical body protruding vertically upward from the support base.
  • the cylindrical body can have a height control mechanism, and the distance between the gas spray port and the silicon wafer surface can be controlled by the mechanism.
  • a plurality of the cylindrical bodies can be installed.
  • An etching apparatus for the surface layer of a silicon wafer A support base having a support portion for placing the silicon wafer; A closing member that closes the open part on the support part side on the support base to form a closed space; Gas introduction means for introducing an etching gas into the closed space;
  • the etching apparatus wherein the closing member has a heating means for heating the inside of the closed space, and the support base has a heating means for heating a silicon wafer disposed on the support portion; It is about.
  • the support base may have a rotation mechanism that rotates a silicon wafer disposed on the support portion in a circumferential direction.
  • the etching apparatus may have a pressure control means for controlling the inside of the closed space to a positive pressure.
  • the gas introduction means may protrude vertically upward from the support base and may include a cylindrical body having a gas spray port for spraying an etching gas at the tip.
  • the cylindrical body can have a height control mechanism.
  • the etching apparatus can have a plurality of the cylindrical bodies.
  • Yet another aspect of the present invention provides: Etching the silicon wafer surface layer by the etching method or using the etching apparatus; Collecting the metal components on the surface of the silicon wafer after etching in the recovered liquid, and analyzing the metal components in the recovered liquid;
  • the present invention relates to a method for analyzing metal contamination of silicon wafers containing silicon.
  • the silicon wafer may be a wafer for grasping process contamination.
  • metal contamination of a silicon wafer that adversely affects device characteristics can be evaluated in a short time with high sensitivity.
  • a silicon wafer for grasping the process contamination it is possible to grasp the metal contamination of the process, thereby providing a high-quality silicon wafer.
  • FIG. 1 is a schematic view of an etching apparatus according to the present invention.
  • FIG. 2 is a graph showing the relationship between the heating temperature of the blocking member (reaction dome) and the amount of Si residue generated.
  • FIG. 3 is a graph showing the relationship between the height of the etching gas ejection tower and the amount of Si residue generated.
  • FIG. 4 is a graph showing the relationship between the amount of positive pressure in the enclosed space (reaction dome) and the amount of etching on the surface layer of the silicon wafer.
  • One embodiment of the present invention relates to a silicon wafer surface layer portion etching method (hereinafter, also simply referred to as “etching method”) in which the silicon wafer surface layer portion is etched by bringing the silicon wafer surface into contact with an etching gas.
  • etching method silicon wafer surface layer portion etching method
  • etching method 1 a mixed gas of hydrogen fluoride gas, nitric acid gas, and nitrogen oxide gas is used as an etching gas for etching the surface layer portion of the silicon wafer.
  • the reaction rate (etching rate) of the gas phase decomposition can be increased, so that the etching amount per unit time can be increased, resulting in a long etching process.
  • An etching amount sufficient for high sensitivity analysis can be realized without performing the analysis.
  • etching method 2 In another aspect of the etching method of the present invention (hereinafter referred to as “etching method 2”), a support base in which a silicon wafer is disposed on a support portion, and an opening portion on the support portion side on the support base are closed by a closing member. And etching the silicon wafer surface layer in a reaction chamber having a closed space formed by introducing an etching gas into the closed space, the gas and the silicon wafer surface, And a silicon wafer disposed on the support portion by the heating means provided on the support base while heating the inside of the closed space by the heating means provided on the closing member during the etching. Is to heat.
  • a support base having a support portion on which a silicon wafer is disposed, a closing member that closes an open portion on the support portion on the support base to form a closed space, and an etching gas in the closed space
  • a silicon wafer surface layer etching apparatus (hereinafter also simply referred to as an “etching apparatus”).
  • the closing member has a heating means for heating the inside of the closed space
  • the support base has a heating means for heating the silicon wafer disposed on the support portion. is there.
  • the etching apparatus of the present invention can be used for carrying out the etching method 2 of the present invention.
  • a support base and a blocking member are used to heat the silicon wafer from above and below when the etching gas and the silicon wafer surface are brought into contact with each other and the substrate surface layer portion is etched. And heating means are provided respectively. Thereby, the amount of Si residue generated by the vapor phase etching reaction and causing a decrease in measurement sensitivity can be reduced. The inventors presume this reason as follows.
  • HNO 3 hydrogen fluoride gas
  • Oxidation of Si with 3 gases (1) and removal of SiO 2 with HF gas (2) are performed simultaneously.
  • the NO gas produced by the reaction reacts with oxygen immediately after the reaction, as shown in (3) below.
  • Si is usually decomposed by 97% or more to form SiF 4 , while 3% or less forms diammonium hexafluorosilicate ((NH 4 ) 2 SiF 6 ).
  • NH 3 gas generated slightly in the reaction (1) reacts with HF gas contained in the etching gas and SiF 4 generated by the reaction of (2) as shown in the following formula (5).
  • the etching gas used is not limited to the one used in the etching method 1 (mixed gas of hydrogen fluoride gas, nitric acid gas, and nitrogen oxide gas).
  • hydrogen fluoride gas A mixed gas of (HF) and nitric acid gas (HNO 3 ) can also be used as an etching gas.
  • a mixed gas of hydrogen fluoride gas (HF) and nitric acid gas (HNO 3 ) is used, the above formula (1) is obtained by the NO 2 gas and HF gas generated in the above formulas (3) and (4), respectively.
  • Etching of the surface layer portion of the silicon wafer proceeds as Si is decomposed and sublimated by repeating the reaction of formula (2).
  • the mixed gas of hydrogen fluoride gas and nitric acid gas can be generated, for example, by the method described in paragraph [0010] of Japanese Patent No. 3832204. From the viewpoint of the etching rate, also in the etching method 2, as in the etching method 1, it is preferable to use a mixed gas of hydrogen fluoride gas, nitric acid gas and NOx gas as the etching gas.
  • the etching method 1, the etching method 2, and the etching apparatus of the present invention can be used alone or in appropriate combination.
  • the present invention will be described in more detail.
  • the silicon wafer surface layer portion is etched by bringing a mixed gas (etching gas) of hydrogen fluoride gas, nitric acid gas, and nitrogen oxide gas into contact with the surface of the silicon wafer.
  • etching gas can be brought into contact with the surface of the silicon wafer by introducing the etching gas into a chamber in which the silicon wafer is disposed.
  • the etching apparatus of the present invention can be used as an etching apparatus provided with such a chamber.
  • the etching apparatus of the present invention can be used as an etching apparatus provided with such a chamber.
  • the etching apparatus of the present invention can be used.
  • the etching apparatus according to the present invention will be described with reference to FIG. 1, but the etching apparatus used in the present invention is not limited to the apparatus shown in FIG. 1, and the etching method 1 and the etching method 2 can be performed. If it has a simple structure, it can be used without any limitation.
  • FIG. 1 is a schematic view of an etching apparatus according to the present invention.
  • 1 is a cross-sectional view of the device, and the lower view of FIG. 1 is a bird's-eye view of the device.
  • the support base 1 has a support portion 1 a on which the silicon wafer 2 is arranged.
  • the closing member (hereinafter also referred to as “reaction dome”) 3 forms a closed space by closing the opening portion of the support base 1 on the support portion 1a side.
  • the silicon wafer 2 disposed in the closed space is heated from above and below by the heating means 5-1 provided in the reaction dome 3 and the heating means 5-2 provided in the support portion 1a.
  • the heating means is not particularly limited, and heating can be performed by various heating methods such as energization heating and induction heating. From the viewpoint of heating efficiency, it is preferable to employ energization heating. For example, by heating the heating means 5-1 in the range of 40 to 100 ° C. and heating the heating means 5-2 in the range of 20 to 40 ° C., the etching reaction can be promoted and the amount of Si residue can be reduced. . Moreover, it is preferable to provide a rotation mechanism on the support base 1 to rotate the silicon wafer in the circumferential direction during the introduction of the etching gas. Thereby, the in-plane uniformity of the etching reaction can be enhanced.
  • the rotation speed is preferably set within a range in which the silicon wafer disposed on the support portion is not displaced by rotation, for example, a tangential speed of 10 to 100 mm / sec. It is preferable to set the degree.
  • it is not essential to heat the inside of the chamber in which the etching reaction is performed, and it is of course possible to use an etching apparatus that does not have the heating means.
  • it is also possible to provide a heating means only in one of the support portion and the reaction dome and heat the inside of the chamber by the heating means.
  • the wafer can be cooled to about 10 ° C. to 20 ° C. by providing a cooling means in the support portion. By this cooling, the etching rate in the surface layer portion of the silicon wafer can be improved.
  • the silicon wafer After the silicon wafer is arranged as described above, an etching gas is introduced into the enclosed space. When the introduced etching gas comes into contact with the surface of the silicon wafer, the surface layer portion of the silicon wafer is etched.
  • the etching gas introduced in the etching method 1 is a mixed gas of hydrogen fluoride gas, nitric acid gas and NOx gas.
  • a mixed gas of hydrogen fluoride gas, nitric acid gas and NOx gas can be obtained by mixing the above three gases at an arbitrary ratio.
  • a mixed gas of nitric acid gas and NOx gas generated by bubbling a carrier gas in a mixed acid of nitric acid and hydrofluoric acid (hereinafter referred to as “mixed acid A”) in which a silicon piece is immersed is converted into hydrogen fluoride.
  • the mixed gas can be obtained by mixing a mixed acid of acid and sulfuric acid (hereinafter referred to as “mixed acid B”) with hydrogen fluoride gas generated by bubbling a carrier gas.
  • mixed acid B mixed acid of sulfuric acid
  • a mixed gas of nitric acid gas and NOx gas generated by bubbling nitrogen gas as a carrier gas in the sealed container 8 containing the mixed acid A, and a carrier gas in the sealed container 7 containing the mixed acid B are used.
  • a mixed gas of hydrogen fluoride gas, nitric acid gas and NOx gas is obtained by mixing with hydrogen fluoride gas generated by bubbling nitrogen gas.
  • the acid solution used to prepare the mixed acid A and the mixed acid B include hydrofluoric acid (HF) having a concentration of 40 to 50% by mass, sulfuric acid (H 2 SO 4 ) having a concentration of 50 to 98% by mass, and a concentration of 50 to 50%. Mention may be made of 70% by mass of nitric acid (HNO 3 ).
  • an inert gas such as nitrogen gas is suitable as the carrier gas used for bubbling in the present invention. Bubbling is preferable because a constant amount of gas can be always supplied.
  • the bubbling amount is not particularly limited, for example, 0.1 to 2 L / min. The degree is preferred.
  • the mixing ratio of the mixed gas is not particularly limited, and can be adjusted by, for example, the flow rate of the carrier gas used for bubbling.
  • the reason for heating hydrofluoric acid here is to increase the etching rate on the wafer surface. If the hydrofluoric acid is not heated, the amount of hydrogen fluoride gas generated per unit time is small as compared with the case of heating, and the etching rate on the wafer surface becomes low. From the viewpoint of the etching rate, hydrofluoric acid is preferably heated to a liquid temperature of 30 ° C. or higher.
  • the optimum liquid temperature of hydrofluoric acid is 40 ° C., and temperature control is relatively easy and preferable.
  • the etching rate was about 10 ⁇ m / hr and the temperature was less than 30 ° C.
  • the wafer surface was etched using hydrogen fluoride gas generated from hydrofluoric acid, the etching rate was less than half that when heated at 40 ° C. Therefore, when hydrofluoric acid is used as the hydrogen fluoride gas generation source, it is preferable to heat the liquid to a temperature of 30 ° C.
  • the etching rate on the wafer surface is the etching rate when hydrogen fluoride gas generated by heating hydrofluoric acid to 40 ° C. is used. Did not improve. This is thought to be because the etching reaction on the wafer surface is rate limiting.
  • the heating temperature of hydrofluoric acid is preferably 50 ° C. or lower.
  • the hydrofluoric acid contained in the container 7 is heated by an electric heater (not shown in FIG. 1) and a temperature sensor is installed to control the output of the heater.
  • nitrogen gas as a carrier gas while maintaining the temperature (as described above, preferably 30 to 50 ° C.)
  • hydrogen fluoride gas can be generated from heated hydrofluoric acid.
  • a constant amount is constantly or periodically fixed while bubbling a mixed acid of nitric acid and hydrofluoric acid in which silicon pieces are immersed with a carrier gas. It is preferable to add hydrofluoric acid.
  • hydrofluoric acid hydrofluoric acid aqueous solution
  • nitrogen gas as a carrier gas into nitric acid containing silicon pieces and hydrofluoric acid (sealed container 8).
  • the silicon piece used here it is preferable to use a high-purity silicon piece in order to prevent the inside of the system from being contaminated by the decomposition of the silicon piece.
  • high-purity silicon pieces include silicon wafer pieces obtained by cutting a silicon wafer, preferably a silicon wafer that has been subjected to final cleaning for manufacturing a silicon substrate.
  • the amount of silicon piece used is not particularly limited as long as a desired amount of gas can be generated. For example, about 80 g of a 68% by mass nitric acid aqueous solution and about 6 g of a 50% by mass hydrofluoric acid aqueous solution are used. About 3 to 5 g of silicon pieces are immersed in the mixed acid, and 50% by mass hydrofluoric acid is added to the mixed acid in an amount of 0.1 to 1.0 g / min. Can be added in an amount.
  • the mixed gas of hydrogen fluoride gas, nitric acid gas, and NOx gas is obtained by joining the flow path of the gas generated from the container 8 containing the mixed acid A containing silicon pieces serving as the supply source.
  • the container 9 is provided in front of the reaction chamber to improve the uniformity of the mixed gas, but the present invention is not limited to the embodiment shown in FIG.
  • the containers 7 to 9 it is preferable to use those made of a fluorine-based resin in order to prevent corrosion by acid or gas.
  • the etching gas is preferably, for example, 100 to 2000 ml / min.
  • the gas ejection tower 4 connected with this gas flow path is protruded vertically upward from the support part 1a.
  • a predetermined distance can be provided between the silicon wafer and the etching gas spraying port, so that the etching gas sprayed from the gas spraying port is the silicon wafer.
  • the reactions of the above formulas (1) and (2) are further promoted, and gel-like orthosilicic acid (H 4 SiO 4 ) and diammonium hexafluorosilicate ((NH 4 ) 2 SiF 6 ) that become Si residues. ) Can be more effectively suppressed.
  • the distance between the silicon wafer surface (surface to be etched) and the gas spray port is preferably 5 cm or more in the vertical direction, preferably 15 cm or more. More preferably, it is more preferably in the range of 15 to 30 cm.
  • the upper part of the gas ejection tower is L-shaped, and a gas spray port is provided at the tip.
  • the number of gas ejection towers is preferably at least 1, preferably 2 or more, and more preferably 5 or more. Although the upper limit of the number is not specifically limited, For example, it is 10 or less.
  • the plurality of gas reaction towers be installed at equal intervals so as to surround the silicon wafer as shown in FIG. Moreover, it is preferable to provide a height control mechanism in the gas ejection tower so that the distance between the gas spray port and the silicon wafer surface can be freely adjusted.
  • a pressure adjustment valve 11 is provided to control the pressure in the closed space.
  • the pressure control means in this manner so that the enclosed space is in the range of atmospheric pressure to positive pressure during etching.
  • the pressure in the enclosed space during etching is preferably a positive pressure in the range of, for example, atmospheric pressure (that is, atmospheric pressure outside the enclosed space) to atmospheric pressure + 0.050 MPa.
  • the pressure adjusting valve 11 is opened and appropriately exhausted.
  • the etching time may be set according to the amount of etching gas introduced and the desired etching amount, and is not particularly limited.
  • the metal impurity contained in the etched surface layer portion remains on the surface of the silicon wafer after the etching process. Therefore, by collecting and quantifying the metal component from the surface of the etched silicon wafer, the metal impurity concentration contained in the etched surface layer portion, that is, the amount of metal contamination in the surface layer portion can be obtained.
  • the moisture contained in the etching gas and the moisture generated by the reaction usually remain as droplets on the surface layer portion after etching. Therefore, it is preferable to dry the droplets by heating the silicon wafer using a heating device such as a hot plate before collecting the metal component.
  • the metal component can be collected in the recovered liquid by scanning the recovered liquid on the surface of the etched silicon wafer.
  • the recovered liquid includes pure water, a mixed solution of hydrofluoric acid and hydrogen peroxide; pure water, a mixed solution of hydrogen peroxide and hydrochloric acid; pure water, hydrofluoric acid, hydrogen peroxide and hydrochloric acid A mixed solution of, etc. can be used.
  • the recoverable liquid that can be used reference can be made to, for example, JP-A-2005-265718, the entire description of which is specifically incorporated herein by reference.
  • the recovery amount supplied and scanned on the silicon wafer surface is preferably about 50 to 250 ⁇ l.
  • a method of scanning the recovery liquid on the surface of the silicon wafer for example, a method of tilting and rotating the wafer so that the solution dripped onto the surface of the silicon wafer can be applied to the entire surface can be used. This method may be performed manually or automatically.
  • the qualitative analysis and quantitative analysis of the metal component contained in the substrate surface portion removed by etching can be performed.
  • the analysis of the metal component can be performed by a known method capable of analyzing the metal component in the solution. Such methods can include atomic absorption spectrometry (AAS) and inductively coupled plasma mass spectrometry (ICP-MS). AAS and ICP-MS are preferable because trace metal components can be analyzed with high sensitivity. Examples of metals that can be analyzed include various metals such as Ag, Cu, Li, Na, Mg, Al, K, Ca, Cr, Fe, Ni, and Zn.
  • the surface layer of the silicon wafer is etched by the etching method of the present invention or using the etching apparatus of the present invention, and the metal components on the surface of the silicon wafer after etching are captured in the recovered liquid. Collecting the silicon component and analyzing the metal component in the recovered liquid. The details are as described above.
  • Metal impurities are easily diffused to the surface layer of the substrate in various heat treatments such as oxidation and diffusion during the silicon wafer manufacturing process, and crystal defects such as precipitates, dislocations, oxygen-induced stacking faults (OSF), There is a possibility that the lifetime of minority carriers is reduced, the leakage current is increased, and the dielectric breakdown voltage of the oxide film is deteriorated. Therefore, in order to reduce metal contamination in manufacturing processes such as heat treatment processes, the process contamination amount of the heating furnace to be used is usually evaluated on a trial basis using an evaluation substrate before heat treating the product. After improving the contamination based on this, full-scale product heat treatment is performed.
  • the metal contamination analysis method of the present invention can be used as a wafer evaluation method for grasping process contamination as described above.
  • the surface layer to be etched for metal contamination analysis refers to the depth direction from the surface of the silicon wafer.
  • the depth to be etched differs depending on the use of the silicon wafer and the required physical properties, but it is generally used for device fabrication.
  • it is preferable to analyze the metal contamination by etching the surface layer portion having a depth of about 5.0 to 30.0 ⁇ m from the surface.
  • the surface may be washed to remove metal impurities on the surface.
  • an acidic solution or the like used as the recovery liquid described above can be used.
  • the silicon wafer whose surface layer metal contamination is analyzed according to the present invention may be a p-type semiconductor substrate or an n-type semiconductor substrate.
  • the thickness is, for example, 600 to 1000 ⁇ m, but is not particularly limited.
  • the analysis method of the present invention can be applied to wafers of any diameter such as ⁇ 200 mm, ⁇ 300 mm, and ⁇ 450 mm.
  • Example 1 Five p-type silicon wafers (resistivity: 10 ⁇ ⁇ cm) having a diameter of 200 mm with front and back surfaces mirror-finished were prepared. In order to completely remove metal impurities on the surface of each silicon wafer, the silicon wafer was cleaned with a cleaning solution of hydrofluoric acid / hydrogen peroxide solution / hydrochloric acid / pure water. After washing, the water was completely removed and dried. Next, the silicon wafer was placed in the etching apparatus shown in FIG. 1 according to the following procedure. First, the first silicon wafer 2 was placed on the support portion 1 a of the support base 1. After the installation, the reaction dome 3 was placed on the support base 1 and closed to prevent the reaction gas from leaking.
  • the temperature of the heating means 5-1 (electric heating) provided on the reaction dome 3 is controlled to about 80 ° C.
  • the heating means (electric heating) 5-2 provided on the support base 1 is controlled to 30 ° C.
  • the support base 1 is moved at a tangential speed of about 50 mm / sec. And rotated. The vertical distance (height) between the lower end of the gas spray port and the silicon wafer surface was adjusted to 20 cm by the height adjustment mechanism of the gas ejection tower.
  • Container 7 was fed at 250 ml / min (container 8) and bubbled. By bubbling, hydrogen fluoride gas is generated from the container 7, and nitric acid gas and NOx gas are generated from the container 8, and after passing through an empty container 9 made of fluorine resin, from the reaction gas spraying port 4 in the reaction dome 3. Sprayed.
  • the reaction gas sprayed from the reaction gas spraying port filled the inside of the reaction dome and etched silicon on the surface of the silicon wafer 2. The silicon wafer was left in the reaction dome 3 for about 30 minutes from the start of nitrogen gas bubbling. After 30 minutes, nitrogen bubbling was stopped.
  • the reaction dome was opened, the silicon wafer 2 was taken out so that the surface was not contaminated, and placed on a hot plate heated to 250 ° C. to dry the droplets. After drying, it was stored in a storage box so that the etched surface was not contaminated. Subsequently, a second silicon wafer is placed on the support base 1. After the installation, the reaction dome 3 was covered as in the first sheet, and the surface was etched in the same manner as in the first sheet. During the etching of the second silicon wafer, 100 ⁇ l of 5% hydrofluoric acid / 10% hydrochloric acid / 5% hydrogen peroxide aqueous acidic recovery solution was dropped on the surface of the first etched silicon wafer to be evaluated.
  • the entire surface of the wafer was scanned to recover metal impurities.
  • the recovered solution was made up to 1000 ⁇ l with ultrapure water, and then quantitative evaluation was performed by a double-convergence type high-sensitivity ICP-MS.
  • the etching reaction of the second silicon wafer is completed, nitrogen bubbling is stopped in the same manner as in the first wafer, taken out from the reaction dome, and heated on a hot plate in the same manner as in the first silicon wafer. After drying, it was stored in a storage box. Thereafter, the same operation was repeated and a total of five silicon wafers were etched and analyzed. Table 1 shows the results of quantification of metal impurities recovered from these five silicon wafers. In addition, the etching amount of each silicon wafer is also shown in Table 1.
  • Example 2 Eight p-type silicon wafers having a diameter of 200 mm (resistivity: 10 ⁇ ⁇ cm) with mirror-finished front and back surfaces were prepared. In order to completely remove metal impurities on the surface of each silicon wafer, the silicon wafer was cleaned with a cleaning solution of hydrofluoric acid / hydrogen peroxide solution / hydrochloric acid / pure water. After washing, the water was completely removed and dried. Using six of the eight silicon wafers after drying, the contamination amount of Fe, Ni, and Cu in the surface layer portion is 1 ⁇ 10 11 atoms / cm 3 or 1 ⁇ 10 13 atoms / cm 3 , respectively. One by one known contamination. Two silicon wafers without known contamination and six known contaminated silicon wafers were etched and analyzed in the same procedure as in Example 1. The results are shown in Table 2.
  • Example 3 Comparative Example 1
  • a total of three silicon wafers were etched in the same procedure as in Example 1 (Example 3). Separately, a total of three silicon wafers were etched by the same procedure as in Example 1 except that 100 g of 50% hydrofluoric acid was put in the container 7 and 80 g of 68% nitric acid was put in the container 8 (Comparative Example 1). ). The amounts of etching in Example 3 and Comparative Example 1 are shown in Table 3.
  • Comparative Example 1 is an example in which hydrogen fluoride gas and nitric acid gas were used as the etching gas, but as shown in Table 3, the etching could not be performed in the same etching time as in Example 1.
  • the surface layer portion of the silicon wafer is etched by about 10 ⁇ m within the same time. I was able to. If the etching amount is about 10 ⁇ m, the metal contamination of the wafer surface layer can be analyzed with high accuracy as shown in Tables 1 and 2. From the above comparison between Example 3 and Comparative Example 1, it was shown that according to the present invention, metal contamination of the surface layer portion of the silicon wafer can be analyzed with high sensitivity by a short etching process.
  • Example 1 (heating temperature of heating means 5-1: 80 ° C.) except that heating temperature of heating means 5-1 provided in the reaction dome was set to 27 ° C., 40 ° C. and 60 ° C., respectively.
  • the process up to the step of scanning the recovered liquid on the surface of the silicon wafer after etching was carried out by the same method as described above.
  • the amount of Si in the collected liquid obtained after etching at Example 1 and the above heating temperature was quantitatively analyzed by double convergence ICP-MS, and the ratio to the etched Si was calculated. The results are shown in FIG. From the results shown in FIG. 2, it can be confirmed that the Si residue is reduced as the heating temperature of the heating means 5-1 is increased.
  • the amount of Si residue compound generated relative to etched Si is preferably 1.0% by mass or less. Therefore, from the results shown in FIG. 2, it can be confirmed that the heating temperature of the heating means 5-1 is preferably 40 ° C. or higher. Also, from the results shown in FIG. 2, it can be confirmed that the amount of Si residue produced is substantially 0% when the heating temperature of the heating means 5-1 is around 100 ° C. Therefore, the heating temperature of the heating means 5-1 for effectively reducing the generation of Si residue is sufficient to be 100 ° C. or less. From the above results, it can be confirmed that the heating temperature of the heating means 5-1 is preferably set in the range of 40 to 100 ° C.
  • the height is preferably 5 cm or more.
  • the amount of Si residue generated is 0.5% by mass or less. Therefore, from the results shown in FIG. 3, the height of the gas spray port is 15 cm or more. It can be confirmed that it is more preferable. Further, in FIG. 3, since the amount of Si residue generated is less than 0.5% by mass at a height of 20 to 30 cm, a steady state is obtained. From the results shown in FIG. 3, a gas for effectively reducing Si residue generation is obtained. It can be said that it is sufficient that the height of the spray port is 30 cm or less. From the above results, it can be confirmed that the height of the gas spray port is preferably 5 cm or more and 30 cm or less, and more preferably 15 cm or more and 30 cm or less.
  • FIG. 4 shows the relationship between the pressure in the enclosed space and the etching amount per unit time. From the results shown in FIG. 4, it can be confirmed that the etching reaction rate increases and the etching amount increases as the pressure is increased.
  • the present invention is useful in the field of manufacturing semiconductor substrates.

Abstract

L'invention porte sur un procédé pour la gravure d'une partie de couche de surface d'une tranche de silicium, lequel procédé comprend le fait d'amener la surface de la tranche de silicium en contact avec un gaz de gravure afin de graver la partie de couche de surface de la tranche de silicium. Dans le procédé, un gaz mélangé d'un gaz de fluorure d'hydrogène, d'un gaz d'acide nitrique et d'un gaz d'oxyde d'azote peut être utilisé comme gaz de gravure.
PCT/JP2010/073592 2010-01-06 2010-12-27 Procédé et appareil pour la gravure d'une partie de couche de surface d'une tranche de silicium, et procédé pour l'analyse de contamination de métal dans une tranche de silicium WO2011083719A1 (fr)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015063679A (ja) * 2013-08-30 2015-04-09 学校法人東京電機大学 発光材料の製造方法
RU2631544C1 (ru) * 2016-10-10 2017-09-25 Публичное Акционерное Общество "Корпорация Всмпо-Ависма" Способ изготовления стандартных образцов лигатур на основе алюминия
EP3229262A1 (fr) * 2016-04-05 2017-10-11 Siltronic AG Procédé pour la gravure en phase vapeur d'une tranche de semi-conducteur pour l'analyse de traces de métaux
JP6399141B1 (ja) * 2017-04-17 2018-10-03 株式会社Sumco シリコンウェーハの金属汚染分析方法およびシリコンウェーハの製造方法
CN110223927A (zh) * 2018-03-01 2019-09-10 胜高股份有限公司 硅晶片的金属污染分析方法
JP2020174070A (ja) * 2019-04-08 2020-10-22 信越半導体株式会社 半導体基板の気相分解方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05211223A (ja) * 1991-11-29 1993-08-20 Nec Corp 半導体基板表面の不純物の分析方法
JPH08330271A (ja) * 1995-06-02 1996-12-13 Shin Etsu Handotai Co Ltd シリコンウエーハ表面のエッチング方法及び装置
JP2001129798A (ja) * 1999-08-28 2001-05-15 Robert Bosch Gmbh 表面マイクロマシニング型構造体の製法
JP2004028787A (ja) * 2002-06-25 2004-01-29 Fujitsu Ltd 全反射蛍光x線分析方法、全反射蛍光x線分析前処理装置及び全反射蛍光x線分析装置
JP2008130696A (ja) * 2006-11-17 2008-06-05 Shin Etsu Handotai Co Ltd シリコンウェーハ表面の珪素脱離方法、シリコンウェーハ表層下領域の液体サンプル採取方法及びその金属不純物分析方法
JP2008182201A (ja) * 2006-12-27 2008-08-07 Siltronic Ag シリコンエッチング方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05211223A (ja) * 1991-11-29 1993-08-20 Nec Corp 半導体基板表面の不純物の分析方法
JPH08330271A (ja) * 1995-06-02 1996-12-13 Shin Etsu Handotai Co Ltd シリコンウエーハ表面のエッチング方法及び装置
JP2001129798A (ja) * 1999-08-28 2001-05-15 Robert Bosch Gmbh 表面マイクロマシニング型構造体の製法
JP2004028787A (ja) * 2002-06-25 2004-01-29 Fujitsu Ltd 全反射蛍光x線分析方法、全反射蛍光x線分析前処理装置及び全反射蛍光x線分析装置
JP2008130696A (ja) * 2006-11-17 2008-06-05 Shin Etsu Handotai Co Ltd シリコンウェーハ表面の珪素脱離方法、シリコンウェーハ表層下領域の液体サンプル採取方法及びその金属不純物分析方法
JP2008182201A (ja) * 2006-12-27 2008-08-07 Siltronic Ag シリコンエッチング方法

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015063679A (ja) * 2013-08-30 2015-04-09 学校法人東京電機大学 発光材料の製造方法
KR20200086386A (ko) * 2016-04-05 2020-07-16 실트로닉 아게 미량 금속 분석을 위한 반도체 웨이퍼의 기상 에칭을 위한 방법
EP3229262A1 (fr) * 2016-04-05 2017-10-11 Siltronic AG Procédé pour la gravure en phase vapeur d'une tranche de semi-conducteur pour l'analyse de traces de métaux
WO2017174371A1 (fr) 2016-04-05 2017-10-12 Siltronic Ag Procédé de gravure en phase vapeur d'une tranche de semi-conducteur destiné à une analyse de métaux-traces
KR102237913B1 (ko) * 2016-04-05 2021-04-09 실트로닉 아게 미량 금속 분석을 위한 반도체 웨이퍼의 기상 에칭을 위한 방법
US10861704B2 (en) 2016-04-05 2020-12-08 Siltronic Ag Method for the vapour phase etching of a semiconductor wafer for trace metal analysis
CN109075056A (zh) * 2016-04-05 2018-12-21 硅电子股份公司 用于痕量金属分析的半导体晶片的气相腐蚀方法
JP2019511839A (ja) * 2016-04-05 2019-04-25 ジルトロニック アクチエンゲゼルシャフトSiltronic AG 微量金属分析のための半導体ウェハの気相エッチングのための方法
RU2631544C1 (ru) * 2016-10-10 2017-09-25 Публичное Акционерное Общество "Корпорация Всмпо-Ависма" Способ изготовления стандартных образцов лигатур на основе алюминия
JP6399141B1 (ja) * 2017-04-17 2018-10-03 株式会社Sumco シリコンウェーハの金属汚染分析方法およびシリコンウェーハの製造方法
KR20190128221A (ko) * 2017-04-17 2019-11-15 가부시키가이샤 사무코 실리콘 웨이퍼의 금속 오염 분석 방법 및 실리콘 웨이퍼의 제조 방법
US10727071B2 (en) 2017-04-17 2020-07-28 Sumco Corporation Method of analyzing metal contamination of silicon wafer and method of manufacturing silicon wafer
JP2018179822A (ja) * 2017-04-17 2018-11-15 株式会社Sumco シリコンウェーハの金属汚染分析方法およびシリコンウェーハの製造方法
WO2018193714A1 (fr) * 2017-04-17 2018-10-25 株式会社Sumco Procédé d'analyse de contamination métallique de tranche de silicium, et procédé de fabrication de tranche de silicium
KR102299861B1 (ko) 2017-04-17 2021-09-07 가부시키가이샤 사무코 실리콘 웨이퍼의 금속 오염 분석 방법 및 실리콘 웨이퍼의 제조 방법
CN110223927A (zh) * 2018-03-01 2019-09-10 胜高股份有限公司 硅晶片的金属污染分析方法
JP2020174070A (ja) * 2019-04-08 2020-10-22 信越半導体株式会社 半導体基板の気相分解方法
JP7092087B2 (ja) 2019-04-08 2022-06-28 信越半導体株式会社 半導体基板の気相分解方法

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