WO2011083512A1 - Élément émetteur d'électrons et dispositif de capture d'image le comprenant - Google Patents

Élément émetteur d'électrons et dispositif de capture d'image le comprenant Download PDF

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Publication number
WO2011083512A1
WO2011083512A1 PCT/JP2010/000069 JP2010000069W WO2011083512A1 WO 2011083512 A1 WO2011083512 A1 WO 2011083512A1 JP 2010000069 W JP2010000069 W JP 2010000069W WO 2011083512 A1 WO2011083512 A1 WO 2011083512A1
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WIPO (PCT)
Prior art keywords
layer
electrode layer
electron
insulator layer
emission
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PCT/JP2010/000069
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English (en)
Japanese (ja)
Inventor
吉成正樹
秋山周哲
中井淳
Original Assignee
パイオニア株式会社
パイオニア・マイクロ・テクノロジー株式会社
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Application filed by パイオニア株式会社, パイオニア・マイクロ・テクノロジー株式会社 filed Critical パイオニア株式会社
Priority to PCT/JP2010/000069 priority Critical patent/WO2011083512A1/fr
Priority to JP2011548857A priority patent/JP5328939B2/ja
Priority to CN201080060892.4A priority patent/CN102696089B/zh
Publication of WO2011083512A1 publication Critical patent/WO2011083512A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J31/00—Cathode ray tubes; Electron beam tubes
    • H01J31/08—Cathode ray tubes; Electron beam tubes having a screen on or from which an image or pattern is formed, picked up, converted, or stored
    • H01J31/10—Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes
    • H01J31/12—Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes with luminescent screen
    • H01J31/123—Flat display tubes
    • H01J31/125—Flat display tubes provided with control means permitting the electron beam to reach selected parts of the screen, e.g. digital selection
    • H01J31/127—Flat display tubes provided with control means permitting the electron beam to reach selected parts of the screen, e.g. digital selection using large area or array sources, i.e. essentially a source for each pixel group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J29/00—Details of cathode-ray tubes or of electron-beam tubes of the types covered by group H01J31/00
    • H01J29/46—Arrangements of electrodes and associated parts for generating or controlling the ray or beam, e.g. electron-optical arrangement
    • H01J29/467—Control electrodes for flat display tubes, e.g. of the type covered by group H01J31/123

Definitions

  • the present invention relates to an electron-emitting device having a focusing electrode that focuses electrons emitted from a surface emitting portion, and an imaging apparatus including the electron-emitting device.
  • the electron-emitting device when being incorporated into an imaging device at the time of mounting, the electron-emitting device is disposed facing the substrate having the anode electrode and the photoelectric conversion layer through a vacuum space, and the emitted electrons are emitted from the holes of the photoelectric conversion layer.
  • the combined current is detected as a video signal.
  • the gate electrode layer and the focusing electrode layer are electrically connected by the carbon layer formed on the inner peripheral surface of the emission recess at the end of the manufacturing process. As a result, the gate electrode layer and the focusing electrode layer are at the same potential, so that a sufficient potential difference cannot be generated between them, and there is a problem that electrons cannot be focused.
  • the present invention provides a surface emission type electron-emitting device in which a gate electrode layer and a focusing electrode layer are not conducted by a carbon layer even when a focusing electrode layer is provided, and an imaging apparatus including the same The task is to do.
  • An electron-emitting device includes an electron-emitting layer that emits electrons from a surface-emitting portion, a gate electrode layer formed on the surface of the electron-emitting layer via a first insulator layer, and a second insulator layer.
  • an electron-emitting layer that emits electrons from a surface-emitting portion
  • a gate electrode layer formed on the surface of the electron-emitting layer via a first insulator layer, and a second insulator layer.
  • the focusing electrode layer and the gate electrode layer are not electrically connected through the carbon layer due to the discontinuous portion of the carbon layer, so that a voltage having a different potential from the gate electrode layer is applied to the focusing electrode layer.
  • the electrons emitted from the surface emitting portion can be efficiently focused.
  • the gate electrode layer and the focusing electrode layer are preferably made of tungsten (W), and other metals such as Si, Al, Ti, TiN, Cu, Ag, Cr, Au, Pt, and C are also used. It may consist of.
  • the electron emission layer is preferably made of amorphous silicon.
  • the emission recess is formed by etching the upper emission recess formed by etching the focusing electrode layer and the second insulator layer, and the gate electrode layer and the first insulator layer coaxially with the upper emission recess and with a small diameter. And a lower discharge recess formed in the above manner.
  • the focusing electrode layer and the second insulator layer constituting the upper emission concave portion do not obstruct the trajectory of the emitted electrons (attenuation of the electron beam), and efficiently emit electrons. can do.
  • the second insulator layer is formed on the upper insulator layer formed on the focusing electrode layer side and on the gate electrode layer side, and is formed of a material having a higher etching rate than the upper insulator layer. It is preferable that the discontinuous portion is constituted by a non-depositionable portion where the layer end of the lower insulator layer etched beyond the layer end of the upper insulator layer faces.
  • the layer end of the lower insulator layer retreats with respect to the layer end of the upper insulator layer, and the non-depositionable portion is formed, so that the carbon layer is automatically formed in a single film formation.
  • a discontinuous portion can be formed.
  • an electron-emitting device in which the focusing electrode layer and the gate electrode layer do not conduct via the carbon layer can be easily manufactured.
  • the focusing electrode layer can be protected when the lower insulator layer is preferentially etched.
  • the upper insulator layer is made of PTEOS and the lower insulator layer is made of PSIN, and the lower insulator layer is preferentially etched by isotropic etching using a CDE (Chemical Dry Etching) method. .
  • CDE Chemical Dry Etching
  • the second insulator layer is made of a material having a high etching rate with respect to the focusing electrode layer, and the discontinuous portion is a layer of the second insulator layer etched beyond the layer end of the focusing electrode layer. It is preferable that the end face is formed of a non-film forming portion.
  • the layer end of the second insulator layer recedes with respect to the layer end of the focusing electrode layer, and the non-depositionable portion is formed.
  • a discontinuous portion can be formed.
  • the insulator layer which comprises a 2nd insulator layer may be single, the film-forming process number of an insulator layer can be reduced.
  • the second insulator layer is preferably made of PSIN, and the second insulator layer is preferably etched preferentially by isotropic etching using the CDE method.
  • the second insulator layer includes an upper insulator layer formed on the focusing electrode layer side, a lower insulator layer formed on the gate electrode layer side, an upper insulator layer, and a lower insulator.
  • An intermediate insulator layer formed of a material having a high etching rate with respect to the upper insulator layer and the lower insulator layer, and the discontinuous portion is a layer of the upper insulator layer. It is preferable that the intermediate insulating layer is etched so as to face the end of the intermediate insulating layer beyond the end and the lower insulating layer.
  • the layer end of the intermediate insulator layer retreats with respect to the layer end of the upper insulator layer, and the non-depositionable portion is formed, so that the carbon layer is automatically formed in a single film formation.
  • a discontinuous portion can be formed.
  • the second insulator layer is composed of three insulator layers, the insulator layer can be thickened and leakage current (leakage) between the focusing electrode layer and the gate electrode can be suppressed. be able to.
  • the upper insulator layer and the lower insulator layer are made of PTEOS, the intermediate insulator layer is made of PSIN, and the intermediate insulator layer is preferably etched preferentially by isotropic etching using the CDE method. .
  • Another electron-emitting device of this embodiment includes an electron-emitting layer that emits electrons from the surface-emitting portion, a gate electrode layer formed on the surface of the electron-emitting layer through the first insulator layer, and a surface-emitting portion.
  • a plurality of insulating support columns partially formed on the surface of the first insulator layer, an electrode support layer formed between the support columns, a gate electrode layer, A focusing electrode layer for focusing the emitted electrons, and the electrode supporting layer, the focusing electrode layer, the gate electrode layer, and the first insulator layer.
  • the surface of the surface emitting portion is provided with an emitting recess that opens in a concave shape, and a carbon layer formed from the surface of the electrode support layer to the inner peripheral surface of the emitting recess, and the carbon layer is an insulating space.
  • the film forming portion of the discharge recess facing the end has an annular discontinuous portion.
  • the non-film forming part is formed by the insulating space, so that the discontinuous part can be automatically formed in the carbon layer by one film formation. For this reason, an electron-emitting device in which the focusing electrode layer and the gate electrode layer are not electrically connected via the carbon layer can be easily manufactured. In addition, since an insulating space exists between the focusing electrode layer and the gate electrode layer, leakage current (leakage) through the insulator layer can be prevented.
  • the insulating space is preferably formed by removing a sacrificial layer formed between the gate electrode layer and the focusing electrode layer by etching.
  • an insulating space can be formed between the focusing electrode layer and the gate electrode layer with a simple process.
  • the sacrificial layer is removed by wet etching (thermal phosphoric acid etching method), and the sacrificial layer is preferably made of a material having a high etching rate with respect to the insulating support portion, for example, PSIN. .
  • the emission recess is etched so that the upper emission recess formed by etching the focusing electrode layer together with the sacrifice layer and the gate electrode layer and the first insulator layer are coaxial with the upper emission recess and have a small diameter. And a lower discharge recess formed as described above.
  • the end of the focusing electrode layer constituting the upper emission concave portion does not obstruct the trajectory of the emitted electrons (attenuation of the electron beam), and can efficiently emit electrons.
  • a voltage is applied so that the potential of the focusing electrode layer is lower than the potential of the gate electrode layer.
  • the focusing electrode can function at a voltage lower than that of the gate electrode layer, an electron-emitting device that emits electrons at a low voltage as a whole can be realized. Further, when the potential of the gate electrode layer is set to 20V, the potential difference between the gate electrode layer and the focusing electrode layer is preferably 0 to 13V.
  • An imaging device includes an electron emission substrate portion having the electron emission element and the cathode electrode, and a light receiving substrate portion facing the electron emission substrate portion with a vacuum space and having a photoelectric conversion layer and an anode electrode. And.
  • the emitted electrons can be efficiently focused on the surface of the photoelectric conversion layer, and a high-detection power-saving imaging device can be provided.
  • FIG. 1 is a schematic cross-sectional view illustrating a configuration of an imaging apparatus according to a first embodiment. It is an expanded sectional view around the emission recess of the electron-emitting device according to the second embodiment. It is a figure showing the formation process of the emission recessed part of the electron emission element which concerns on 2nd Embodiment. It is a figure showing the formation process of the emission recessed part of the electron emission element which concerns on 2nd Embodiment. It is a figure showing the formation process of the emission recessed part of the electron emission element which concerns on 2nd Embodiment.
  • This electron-emitting device is a so-called surface-emitting type electron-emitting device having a cold-cathode type electron source, and the imaging device has a vacuum space in an electron-emitting device array in which a plurality of electron-emitting devices are arranged in a matrix.
  • the photoelectric conversion film is opposed to each other.
  • an electron-emitting device 1 includes a cathode electrode layer 2, an electron-emitting layer 3 stacked on the cathode electrode layer 2 and made of amorphous silicon (a-Si), and an electron-emitting layer 3 And a plurality of electrode layers and an electrode layer portion 4 having an insulator layer formed between them.
  • the electrode layer portion 4 is formed on the first insulator layer 5 formed on the electron emission layer 3, the gate electrode layer 6 formed on the first insulator layer 5, and on the gate electrode layer 6.
  • the focusing electrode layer 8 formed on the second insulator layer 7.
  • the electrode layer portion 4 is formed with a concave electron emission concave portion 10 that penetrates each layer and exposes the electron emission layer 3 at the bottom.
  • the surface emission portion 9, that is, an exposed portion of the electron emission layer 3, An emission site is configured.
  • an imaging element 113 pixel
  • an imaging element 113 is configured by an array of electron-emitting devices 1 (electron-emitting recesses 10) (see FIG. 6).
  • the carbon layer 11 formed on the surface of the gate electrode layer 6 and the inner peripheral surface of the electron emission recess 10 electrically connects the gate electrode layer 6 and the surface emission part 9 and excites electron emission.
  • the carbon layer 11 enhances the electron emission performance of the surface emission part 9 in cooperation with the electron emission layer 3 made of amorphous silicon.
  • the carbon layer 11 of the present embodiment has an annular discontinuous portion 11 a on the inner peripheral surface of the electron emission recess 10, so that the focusing electrode layer 8 is connected to the gate electrode layer 6 via the carbon layer 11. Conduction is prevented (details will be described later).
  • the electron emission recess 10 includes the upper emission recess 10a surrounded by the layer ends of the focusing electrode layer 8 and the second insulator layer 7 formed thereon, and the layer ends of the gate electrode layer 6 and the first insulator layer 5. And a lower discharge recess 10b surrounded by two, which are formed by two etchings described later.
  • the upper emission recess 10a is formed such that the layer ends of the focusing electrode layer 8 and the second insulator layer 7 recede from the layer ends of the gate electrode layer 6 and the first insulator layer 5, and the electron emission recess 10a. 10, the upper part is formed so as to expand with respect to the lower part as a whole. Thereby, the layer end of the focusing electrode layer 8 is prevented from protruding (obstructing) on the trajectory of the electrons emitted from the surface emitting portion 9.
  • the second insulator layer 7 has an upper insulator layer 7a formed on the focusing electrode layer 8 side and a lower insulator layer 7b formed on the gate electrode layer 6 side.
  • the layer end of the focusing electrode layer 8 recedes from the layer end of the upper insulator layer 7a
  • the layer end of the lower insulator layer 7b recedes from the layer ends of the focusing electrode layer 8 and the upper insulator layer 7a.
  • an eaves portion 12 is formed between the gate electrode layer 6 and the upper insulator layer 7a by retreating the layer end of the lower insulator layer 7b.
  • the lower side of the eaves portion 12 is a “film formation impossible portion” as defined in the claims.
  • the carbon layer 11 is formed on the inner peripheral surface of the electron emission recess 10 on the inner peripheral surface of the electron emission recess 10 except for the layer end of the lower insulator layer 7 b by the eaves portion 12.
  • a discontinuous portion 11a is formed at a portion facing the layer end of the lower insulator layer 7b of the carbon layer 11 formed on the surface. Since the carbon layer 11 has the discontinuous portion 11a, the focusing electrode layer 8 and the gate electrode layer 6 do not conduct through the carbon layer 11, and the focusing electrode layer 8 is connected to the gate electrode layer 6.
  • a voltage having a low potential can be applied, and the electrons emitted from the surface emitting portion 9 can be efficiently focused. Note that the carbon layer 11 is not formed on the surface emitting portion 9 in order to suppress unwanted leakage current (leakage) and heat generation by the carbon layer 11.
  • the gate electrode layer 6 is made of tungsten (W) and has a thickness of 100 nm (1000 mm). Similar to the gate electrode layer 6, the focusing electrode layer 8 is made of tungsten, is thinner than the gate electrode layer 6, and is formed to a thickness of 50 nm (500 mm).
  • the film thicknesses of both the gate electrode layer 6 and the focusing electrode layer 8 are preferably formed within a range of 10 to 200 nm (100 to 2000 mm). Further, the gate electrode layer 6 and the focusing electrode layer 8 may use metals such as Si, Al, Ti, TiN, Cu, Ag, Cr, Au, Pt, and C in addition to tungsten.
  • the upper insulator layer 7a of the second insulator layer 7 is made of tetraethoxysilane (PTEOS) formed by a plasma CVD method, and is formed to a film thickness of 50 nm (500 mm).
  • the lower insulator layer 7b is made of silicon nitride (PSIN) formed by a plasma CVD method, and is formed to a film thickness of 100 nm (1000 mm). That is, the film thickness that insulates between the gate electrode layer 6 and the focusing electrode layer 8 (the film thickness of the second insulator layer 7) is 150 nm (1500 mm).
  • the first insulator layer 5 is preferably formed with the same material (PTEOS) as the upper insulator layer 7a of the second insulator layer 7, and is formed with a film thickness of 350 nm (3500 mm). In order to sufficiently insulate between the gate electrode layer 6 and the electron emission layer 3, the first insulator layer 5 is formed to be considerably thicker than the second insulator layer 7. It should be noted that the film thicknesses of both the first insulator layer 5 and the second insulator layer 7 are preferably in the range of 50 to 1000 nm (500 to 10000 mm).
  • the surface emitting portion 9 is considered to be heated and oxidized by the generated strong electric field, but the first insulator layer 5 made of oxide PTEOS is made of amorphous silicon.
  • the surface emission part 9 is oxidized and the electron emission performance of the surface emission part 9 is improved.
  • the eaves portion 12 is formed by performing isotropic etching using a CDE (Chemical-Dry-Etching) method on the inner peripheral surface of the upper discharge recess 10a and preferentially etching the lower insulator layer 7b. (Details will be described later). Specifically, the lower insulator layer 7b is etched by 100 nm (1000 mm) larger than the upper insulator layer 7a, and the depth of the eaves part 12 becomes 100 nm (1000 mm).
  • CDE Chemical-Dry-Etching
  • the etching rate of each layer constituting the upper emission recess 10a in the CDE method is about 40 nm / min (400 ⁇ / min) for tungsten constituting the focusing electrode layer 8 and about 11 nm / min for PTEOS constituting the upper insulator layer 7a.
  • the PSIN constituting the lower insulator layer 7b is approximately 85 nm / min (850 ⁇ / min). That is, the lower insulator layer 7b that forms the eaves portion 12 is formed of a material that is most easily etched.
  • the voltage applied to the focusing electrode layer 8 is set lower than the voltage applied to the gate electrode layer 6 (carbon layer 11).
  • the potential of the gate electrode layer is set to 20V, both Is preferably 0 to 13V. In this way, the voltage is applied so that the focusing electrode layer 8 has a sufficiently lower potential than the gate electrode layer 6, and the applied voltage to the electron-emitting device 1 can be suppressed as a whole.
  • FIG. 2 shows a manufacturing process of the upper discharge recess 10a.
  • amorphous silicon to be an electron emission layer 3 PTEOS to be a first insulator layer 5, tungsten to be a gate electrode layer 6, a second insulator layer 7 is formed in this order by sputtering and plasma CVD, using PSIN to be the lower insulator layer 7b, PTEOS to be the upper insulator layer 7a of the second insulator layer 7, and tungsten to be the focusing electrode layer 8. (Refer figure (a)).
  • Each layer is formed so that the thickness is 50 nm and the thickness of the focusing electrode layer 8 is 50 nm.
  • a photoresist layer 20 is applied by spin coating on the focusing electrode layer 8 formed on the uppermost portion, and after an exposure / development process, an opening of the upper emission recess 10a is formed at the position where the electron emission recess 10 is formed.
  • a resist pattern 21 having a resist removal portion having the same dimension as that of the dimension is formed (see FIG. 5B).
  • a plurality of resist removal portions are formed in a matrix to form an array of electron-emitting devices 1.
  • RIE Reactive Ion Etching
  • Etching is performed by the method (anisotropic etching). Thereby, only a part (circular portion) of the focusing electrode layer 8, the upper insulator layer 7a, and the lower insulator layer 7b is removed on the gate electrode layer 6 to form an opening 22 that becomes the upper emission recess 10a. (See (c) in the figure).
  • the opening 22 formed on the gate electrode layer 6 is etched by the CDE method (isotropic etching).
  • a layer made of a material having a high etching rate in the CDE method of each layer is preferentially etched, and irregularities are formed on the inner peripheral surface of the opening 22.
  • the layer end of the focusing electrode layer 8 recedes from the layer end of the upper insulator layer 7a, and the layer end of the lower insulator layer 7b is the focusing electrode layer 8 and the upper insulator.
  • a space is formed between the gate electrode layer 6 and the upper insulator layer 7a by the layer end of the lower insulator layer 7b which is receded from the layer end of the layer 7a and is most receded in the three layers, and becomes an eaves portion 12. .
  • the etching operation is controlled so that the size of the eaves portion 12 (the difference between the layer end of the upper insulator layer 7a and the layer end of the lower insulator layer 7b) is 100 nm (1000 mm). Thereafter, only the photoresist layer 20 is removed.
  • FIG. 3 shows a manufacturing process of the lower discharge recess 10b.
  • FIG. 5A shows a state where the photoresist layer 20 is removed and an upper discharge recess 10a is formed.
  • a photoresist layer 30 is applied on the surface of the focusing electrode layer 8 and the exposed gate electrode layer 6 by a spin coating method, and the resist removal having the same dimension as the opening dimension of the lower discharge recess 10b is performed through an exposure / development process.
  • a resist pattern 31 having a portion is formed. At this time, the resist pattern 31 is formed so as to be coaxial (concentric) with the upper discharge recess 10a and to have a smaller diameter (see FIG. 5B).
  • the gate electrode layer 6 and the first insulator layer 5 are etched by the RIE method through the formed resist pattern 31 (anisotropic etching). Thereby, the opening 32 from which the gate electrode layer 6 and the first insulator layer 5 are removed is formed on the electron emission layer 3. That is, the lower emission concave portion 10b is formed, and the electron emission layer 3 (surface emission portion 9) is exposed at the bottom thereof (see FIG. 5C). Thereafter, only the photoresist layer 30 is removed (see FIG. 4D). Finally, the carbon layer 11 is formed by sputtering or the like over the surface of the focusing electrode layer 8 and the inner peripheral surface of the electron emission recess 10 (see FIG. 1).
  • the carbon layer 11 is not formed on the lower side of the eaves portion 12 where the lower insulator layer 7b is preferentially etched and relatively protruded, and the annular discontinuity is automatically formed in the carbon layer 11.
  • a portion 11a (a non-film forming portion) is formed.
  • the electron emission recessed part 10 which formed the carbon layer 11 into a film is formed.
  • the discontinuity can be easily formed in the carbon layer by a single film formation by the eaves formed by retreating the layer end of the lower insulator layer 7b with respect to the layer end of the upper insulator layer 7a. Can do. Further, when the upper insulator layer 7a preferentially etches the lower insulator layer 7b, the focusing electrode layer 8 can be protected.
  • FIG. 4 shows an electron-emitting device 1 according to a first modification of the present embodiment.
  • the second insulator layer 7 according to this modification includes an upper insulator layer 7a formed on the focusing electrode layer 8 side and a lower insulator layer 7b formed on the gate electrode layer 6 side. And an intermediate insulator layer 7c formed between the upper insulator layer 7a and the lower insulator layer 7b.
  • the upper insulator layer 7a and the lower insulator layer 7b are made of PTEOS, and the intermediate insulator layer 7c is made of PSIN.
  • the intermediate insulator layer 7c made of a material having a high etching rate is preferentially etched by isotropic etching by the CDE method when the upper discharge recess 10a is formed, and the inner peripheral surface of the upper discharge recess 10a is uneven. Is formed.
  • the layer end of the focusing electrode layer 8 recedes from the layer ends of the upper insulator layer 7a and the lower insulator layer 7b, and the layer end of the intermediate insulator layer 7c is the focusing electrode layer 8 and the upper insulating layer 7b.
  • An eaves portion 12 is formed between the upper insulator layer 7a and the lower insulator layer 7b by the layer end of the intermediate insulator layer 7c that has receded from the layer ends of the body layer 7a and the lower insulator layer 7b. Has been.
  • the eaves portion 12 forms a discontinuous portion 11 a of the carbon layer 11.
  • each layer is 50 nm (500 mm), and the thickness of the second insulator layer 7 as a whole is 150 nm (1500 mm).
  • the second insulator layer 7 according to this modification is preferentially formed by forming the intermediate insulator layer 7c between the upper insulator layer 7a and the lower insulator layer 7b. When etching 7c, the focusing electrode layer 8 and the gate electrode layer 6 can be protected.
  • FIG. 5 shows an electron-emitting device 1 according to a second modification of the present embodiment.
  • the second insulator layer 7 according to the present modification does not have a plurality of layers with different etching rates, but is a single layer made of PSIN. Therefore, the second insulator layer 7 is preferentially etched with respect to the focusing electrode layer 8 and the gate electrode layer 6 by isotropic etching by the CDE method at the time of forming the upper discharge recess 10a.
  • An eaves portion 12 is formed between the focusing electrode layer 8 and the gate electrode layer 6 by the layer end of the second insulating layer 7 that has receded, and the eaves portion 12 forms a discontinuous portion 11 a of the carbon layer 11.
  • the film thickness of the second insulator layer 7 is 150 nm (1500 mm).
  • FIG. 6 is a cross-sectional view schematically showing the imaging device 100.
  • the imaging device 100 includes an electron emission substrate 110 in which a plurality of electron emission elements 1 are formed, and an electron emission substrate.
  • the light receiving substrate part 120 which is disposed opposite to the part 110 in a vacuum space and serves as a target for the emitted electrons, and is spaced between the electron emitting substrate part 110 and the light receiving substrate part 120, And a mesh electrode 130 for controlling the trajectory.
  • the electron emission substrate unit 110 includes a silicon substrate 111, a drive circuit layer 112 formed on the silicon substrate 111, and a plurality of imaging elements 113 formed in a matrix on the drive circuit layer 112.
  • Each image sensor 113 functions as one pixel, and is configured by an electron emitter array 114 in which a plurality of electron emitters 1 are arranged in a matrix. That is, the electron-emitting device array 114 constituting one imaging device 113 is driven as a unit.
  • the imaging device 112 is a drive circuit comprising a substrate made of silicon as a material, a MOS transistor array (switch) for driving the electron-emitting device array 114 (electron-emitting device 1), and a horizontal and vertical scanning circuit for controlling the MOS transistor array. (Illustration omitted) is made up and configured.
  • the plurality of electron-emitting device arrays 114 (imaging devices 113) are dot-sequentially driven (scanned) by a driving circuit.
  • the light receiving substrate portion 120 includes a transparent glass substrate 121, an anode electrode layer 122 (transparent electrode) laminated on the back surface of the glass substrate 121, and a photoelectric conversion layer 123 laminated on the back surface of the anode electrode layer 122. is doing.
  • a voltage is applied to the anode electrode layer 122, holes generated in the photoelectric conversion layer 123 are accelerated by incident light from the glass substrate 121 side, and a positive light corresponding to an incident light image near the back surface of the photoelectric conversion layer 123 is accelerated.
  • a hole pattern (not shown) is formed.
  • the mesh electrode 130 is disposed between the electron emission substrate unit 110 and the light receiving substrate unit 120 in order to control the trajectory of the emitted electrons and absorb surplus electrons.
  • the light receiving substrate unit 120 includes a circuit for supplying signals and voltages necessary for driving the light receiving substrate unit 120, a circuit for outputting a detected video signal, and the like.
  • this imaging device 100 electrons emitted from the electron emission recess 10 of the electron emission substrate portion 110 pass through the holes 131 of the mesh electrode 130 and grow near the surface of the photoelectric conversion layer 123 of the light receiving substrate portion 120.
  • the image is picked up by combining with the pattern and detecting the current at the time of combining as a video signal. That is, in the photoelectric conversion layer 123, a different video signal is detected from the difference in the accumulated amount of holes for each image sensor 113 by the hole pattern reflecting the incident light image, and the strength of this video signal is detected as light and dark.
  • the present embodiment is configured to minimize the insulator layer interposed between the focusing electrode layer 8 and the gate electrode layer 6 with respect to the first embodiment.
  • the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
  • the electron-emitting device 1 includes a cathode electrode layer 2, an electron-emitting layer 3 stacked on the cathode electrode layer 2, and an electrode formed on the electron-emitting layer 3. And a layer portion 4.
  • the electrode layer section 4 is separated from the first insulator layer 5 formed on the electron emission layer 3, the gate electrode layer 6 formed on the first insulator layer 5, and the gate electrode layer 6.
  • the focusing electrode layer 8 formed (via the spacing portion 50), a plurality of insulating support columns 51 penetrating from the first insulator layer 5 through the gate electrode layer 6 and the focusing electrode layer 8, and the focusing electrode layer 8 And an insulating electrode support layer 52 that is formed on the plurality of support portions 51 and supports the focusing electrode layer 8 on the back surface.
  • the plurality of support columns 51 are formed at four corners of a virtual square (corresponding to a pixel) surrounding the plurality of electron emission recesses 10 (see FIG. 8).
  • the electrode layer portion 4 is formed with an electron emission concave portion 10 that penetrates each layer and exposes the surface emission portion 9 at the bottom at a position avoiding the support column portion 51.
  • the carbon layer 11 is formed on the surface of the electrode support layer 52 and the inner peripheral surface of the electron emission recess 10.
  • the carbon layer 11 has an annular discontinuous portion 11 a at the separation portion 50 between the focusing electrode layer 8 and the gate electrode layer 6.
  • the discontinuous portion 11 a prevents the focusing electrode layer 8 from conducting with the gate electrode layer 6 through the carbon layer 11.
  • the separation portion 50 corresponds to an “insulating space” in the claims, and further to a “film formation impossible portion”.
  • the electron emission recess 10 is surrounded by the layer ends of the electrode support layer 52 and the focusing electrode layer 8, the upper emission recess 10 a surrounded by the separation portion 50, and the layer ends of the gate electrode layer 6 and the first insulator layer 5. And a lower discharge recess 10b.
  • the upper emission recess 10a is formed such that the layer ends of the electrode support layer 52 and the focusing electrode layer 8 recede from the layer ends of the gate electrode layer 6 and the first insulator layer 5, and the electron emission recess 10 As a whole, the upper part is widened with respect to the lower part. Thereby, it is suppressed that the layer end of the focusing electrode layer 8 protrudes on the trajectory of the electrons emitted from the surface emitting portion 9.
  • the carbon layer 11 is formed on the inner peripheral surface of the electron emission recess 10 except for the separation portion 50 on the inner peripheral surface of the electron emission recess 10, and an annular discontinuous portion 11 a that faces the separation portion 50 is formed. . Since the carbon layer 11 has the discontinuous portion 11a, the focusing electrode layer 8 and the gate electrode layer 6 do not conduct through the carbon layer 11, and the focusing electrode layer 8 is connected to the gate electrode layer 6. A voltage having a low potential can be applied, and the electrons emitted from the surface emitting portion 9 can be efficiently focused. Further, the separation portion 50 functions as an insulating space between the focusing electrode layer 8 and the gate electrode layer 6 and can effectively prevent leakage current (leakage). Note that the carbon layer 11 is not formed on the surface emitting portion 9 in order to suppress unwanted leakage current (leakage) and heat generation by the carbon layer 11.
  • each layer deposited on the electrode layer portion 4 is the same as that of the first embodiment, and the column portion 51 and the electrode support layer 52 that only the electrode layer portion 4 according to this embodiment has are: It consists of PTEOS. Further, the sacrificial layer 53 (see FIG. 10) that is removed when the separation portion 50 is formed is made of tungsten that constitutes the gate electrode layer 6 and the focusing electrode layer 8, and PTEOS that constitutes the column portion 51 and the electrode support layer 52. It is composed of PSIN having a high etching rate in hot phosphoric acid etching. The thickness of each layer is the same as that of the first embodiment, but it is preferable to configure the column portion 51 so that the thickness of the separation portion 50 is 150 nm (1500 mm). This is to sufficiently maintain the insulating property of the support column 51 between the focusing electrode layer 8 and the gate electrode layer 6.
  • FIGS. 8 and 9 Each drawing shows a top view (right view) of the electron-emitting device 1 and a cross-sectional view taken along line AA in the top view (left view). A square portion surrounded by a dotted line in the top view (right diagram) corresponds to one electron-emitting device 1.
  • FIG. 8 shows a process of forming the columnar portion 51 and the electrode support layer 52 that support the focusing electrode layer 8 separately from the gate electrode layer 6.
  • amorphous silicon to be the electron emission layer 3 PTEOS to be the first insulator layer 5, tungsten to be the gate electrode layer 6, and the separation portion 50 are formed.
  • PSIN to be the sacrificial layer 53 and tungsten to be the focusing electrode layer 8 are sequentially formed by a sputtering method and a plasma CVD method (see FIG. 8A).
  • a photoresist layer 60 is applied onto the focusing electrode layer 8 by a spin coating method, and a resist removing portion having the same dimensions as the cross section of the column portion 51 is provided at the position where the column portion 51 is formed through an exposure / development process.
  • a resist pattern 61 is formed. As shown in FIG. 4B, four resist patterns 61 are formed at the four corners of the electron-emitting device 1 in a cross shape with each vertex as the center. In the actual process, a plurality of resist removal portions are formed in a matrix to form an array of electron-emitting devices 1.
  • the focusing electrode layer 8, the sacrificial layer 53, and the gate electrode layer 6 are etched by the RIE method through the formed resist pattern 61 (anisotropic etching). Thereafter, only the photoresist layer 60 is removed. Subsequently, PTEOS to be the support column 51 and the electrode support layer 52 is formed on the surface of the formed support column forming opening 62 and the focusing electrode layer 8 by a plasma CVD method (see FIG. 8C).
  • FIG. 9 shows a manufacturing process of the electron emission recess 10.
  • a photoresist layer 20 is applied onto the formed electrode support layer 52 by spin coating, and after exposure and development processes, a resist removal portion having the same dimensions as the opening of the upper emission recess 10a is formed at the position where the electron emission recess 10a is formed.
  • the resist pattern 21 is formed, and the electrode support layer 52, the focusing electrode layer 8 and the sacrificial layer 53 are etched by RIE (anisotropic etching) (see FIG. 5A). Thereafter, only the photoresist layer 20 is removed.
  • RIE anisotropic etching
  • a photoresist layer 30 is applied on the sacrificial layer 53 and the exposed gate electrode layer 6 by a spin coating method, and a resist removal portion having the same dimensions as the opening of the lower emission recess 10b is obtained through an exposure / development process.
  • a resist pattern 31 is formed, and the gate electrode layer 6 and the first insulator layer 5 are etched by RIE (anisotropic etching) (see FIG. 5B).
  • the resist pattern 31 is formed coaxially (concentrically) with the upper discharge recess 10a and having a smaller diameter.
  • the gate electrode layer 6 and the first insulator layer 5 are opened on the electron emission layer 3, and the electron emission layer 3 (surface emission portion 9) is exposed at the bottom. Thereafter, only the photoresist layer 30 is removed.
  • FIG. 10 shows a process of forming the separation portion 50.
  • FIG. 4A shows a state in which the photoresist layer 30 is removed and the electron emission recess 10 is formed.
  • the sacrificial layer 53 formed between the focusing electrode layer 8 and the gate electrode layer 6 is selectively etched using a hot phosphoric acid etching method, which is wet etching, to form a separation portion 50 (see FIG. (See (b)).
  • a hot phosphoric acid etching method which is wet etching
  • the carbon layer 11 is formed by sputtering or the like over the surface of the electrode support layer 52 and the inner peripheral surface of the electron emission recess 10 (see FIG. 7). At this time, the carbon layer 11 is not formed in the separation portion 50 where the sacrificial layer 53 is selectively etched, and an annular discontinuous portion 11 a is formed in the carbon layer 11.
  • the insulating space (separating portion 50) between the focusing electrode layer 8 and the gate electrode layer 6 enables the discontinuous portion to be automatically formed in the carbon layer by one film formation, and the insulator. Leakage current (leakage) through the layer can be prevented.
  • the separation portion 50 is selectively etched, the sacrificial layer 53 is composed of a material having a high etching rate in the hot phosphoric acid etching method with respect to the support portion 51. However, it also functions as a surplus for overetching.
  • the carbon film 11 cannot be formed between the focusing electrode layer 8 and the gate electrode layer 6 (eave portion 12 or spaced apart) on the inner peripheral surface of the electron emitting recess 10. Part 50), an annular discontinuous portion 11a is formed in the carbon layer 11, and the focusing electrode layer 8 and the gate electrode layer 6 do not conduct through the carbon layer 11. As a result, a voltage having a potential different from that of the gate electrode layer 6 can be applied to the focusing electrode layer 8, and the electron trajectory can be efficiently focused. And the imaging device 100 provided with the electron-emitting device 1 can efficiently focus the emitted electrons on the surface of the photoelectric conversion layer 123, which is a power-saving type and has high detection accuracy.
  • Electron emission element 2 Cathode electrode layer 3
  • Electron emission layer 5 1st insulator layer 6
  • Surface emission Part 10 Electron emission concave part 10a Upper part emission concave part 10b Lower part emission concave part 11 Carbon layer 11a Discontinuous part 12
  • Imaging device 110 Electron emission substrate part 120 Light receiving substrate part 122

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  • Cold Cathode And The Manufacture (AREA)
  • Electrodes For Cathode-Ray Tubes (AREA)
  • Image-Pickup Tubes, Image-Amplification Tubes, And Storage Tubes (AREA)

Abstract

L'invention concerne un élément émetteur d'électrons (1) du type à émission de surface dans lequel, même lorsqu'il comporte une couche d'électrode de focalisation (8), une couche d'électrode de grille (6) et la couche d'électrode de focalisation ne sont pas connectées électriquement par une couche de carbone (11). L'invention concerne également un dispositif de capture d'image comportant l'élément émetteur d'électrons. L'invention concerne plus précisément un élément émetteur d'électrons qui comprend : une couche émettrice d'électrons (3) afin d'émettre des électrons depuis une partie d'émission de surface (9) ; une couche d'électrode de grille formée sur la surface de la couche émettrice d'électrons, une première couche isolante (5) étant disposée entre elles ; une couche d'électrode de focalisation formée sur la surface de la couche d'électrode de grille et focalisant les électrons émis, une seconde couche isolante (7) étant disposée entre elles ; un renfoncement d'émission (10) qui pénètre dans la couche d'électrode de focalisation, dans la seconde couche isolante, dans la couche d'électrode de grille et dans la première couche isolante, et qui forme une ouverture en forme de renfoncement à la surface de la partie d'émission de surface ; et une couche de carbone qui est formée depuis la surface de la couche d'électrode de focalisation jusqu'à la surface interne du renfoncement d'émission. La couche de carbone comprend une partie discontinue annulaire (11a) au niveau de la partie de formation de film du renfoncement d'émission à laquelle fait face une extrémité de couche de la seconde couche isolante.
PCT/JP2010/000069 2010-01-07 2010-01-07 Élément émetteur d'électrons et dispositif de capture d'image le comprenant WO2011083512A1 (fr)

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PCT/JP2010/000069 WO2011083512A1 (fr) 2010-01-07 2010-01-07 Élément émetteur d'électrons et dispositif de capture d'image le comprenant
JP2011548857A JP5328939B2 (ja) 2010-01-07 2010-01-07 電子放出素子およびこれを備えた撮像装置
CN201080060892.4A CN102696089B (zh) 2010-01-07 2010-01-07 电子发射元件以及具备该电子发射元件的摄像装置

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PCT/JP2010/000069 WO2011083512A1 (fr) 2010-01-07 2010-01-07 Élément émetteur d'électrons et dispositif de capture d'image le comprenant

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JPWO2012168970A1 (ja) * 2011-06-08 2015-02-23 パイオニア株式会社 電子放出素子およびこれを備えた撮像装置

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JP2003123625A (ja) * 2001-10-05 2003-04-25 Hewlett Packard Co <Hp> 改良された電子電界エミッタスピント型先端構造体及びそれを製造するための方法
JP2005228556A (ja) * 2004-02-12 2005-08-25 Pioneer Electronic Corp 電子放出素子を用いた光電変換装置および撮像装置
WO2006064634A1 (fr) * 2004-12-17 2006-06-22 Pioneer Corporation Element d'ejection d'electrons et son procede de fabrication
WO2007114103A1 (fr) * 2006-03-31 2007-10-11 Pioneer Corporation élément d'émission d'électrons, dispositif d'affichage utilisant UN élément d'émission d'électrons, et méthode de fabrication d'un élément d'émission d'électrons
WO2007119524A1 (fr) * 2006-03-31 2007-10-25 Pioneer Corporation élément émettant des électrons, méthode de fabrication dudit élément, élément de conversion photoélectrique utilisant l'élément émettant des électrons, appareil d'imagerie et AFFICHAGE D'écran plat.
JP2008078161A (ja) * 2007-12-12 2008-04-03 Hitachi Ltd 冷陰極型フラットパネルディスプレイ

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Publication number Priority date Publication date Assignee Title
JP2002260546A (ja) * 2001-02-27 2002-09-13 Hewlett Packard Co <Hp> 平坦な放射領域と集束構造を有する電子源
JP2003123625A (ja) * 2001-10-05 2003-04-25 Hewlett Packard Co <Hp> 改良された電子電界エミッタスピント型先端構造体及びそれを製造するための方法
JP2005228556A (ja) * 2004-02-12 2005-08-25 Pioneer Electronic Corp 電子放出素子を用いた光電変換装置および撮像装置
WO2006064634A1 (fr) * 2004-12-17 2006-06-22 Pioneer Corporation Element d'ejection d'electrons et son procede de fabrication
WO2007114103A1 (fr) * 2006-03-31 2007-10-11 Pioneer Corporation élément d'émission d'électrons, dispositif d'affichage utilisant UN élément d'émission d'électrons, et méthode de fabrication d'un élément d'émission d'électrons
WO2007119524A1 (fr) * 2006-03-31 2007-10-25 Pioneer Corporation élément émettant des électrons, méthode de fabrication dudit élément, élément de conversion photoélectrique utilisant l'élément émettant des électrons, appareil d'imagerie et AFFICHAGE D'écran plat.
JP2008078161A (ja) * 2007-12-12 2008-04-03 Hitachi Ltd 冷陰極型フラットパネルディスプレイ

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JPWO2012168970A1 (ja) * 2011-06-08 2015-02-23 パイオニア株式会社 電子放出素子およびこれを備えた撮像装置

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