WO2011070837A1 - Dispositif à semi-conducteur et système de mémoire - Google Patents

Dispositif à semi-conducteur et système de mémoire Download PDF

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Publication number
WO2011070837A1
WO2011070837A1 PCT/JP2010/066464 JP2010066464W WO2011070837A1 WO 2011070837 A1 WO2011070837 A1 WO 2011070837A1 JP 2010066464 W JP2010066464 W JP 2010066464W WO 2011070837 A1 WO2011070837 A1 WO 2011070837A1
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WO
WIPO (PCT)
Prior art keywords
symbol
data
coding
generation unit
random number
Prior art date
Application number
PCT/JP2010/066464
Other languages
English (en)
Inventor
Kunihiko Yamagishi
Toshitada Saito
Original Assignee
Kabushiki Kaisha Toshiba
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US13/514,736 priority Critical patent/US8781024B2/en
Priority to CN201080056003.7A priority patent/CN102652299B/zh
Priority to KR1020127014714A priority patent/KR101431930B1/ko
Priority to EP10835759.1A priority patent/EP2510419B1/fr
Application filed by Kabushiki Kaisha Toshiba filed Critical Kabushiki Kaisha Toshiba
Publication of WO2011070837A1 publication Critical patent/WO2011070837A1/fr
Priority to US14/292,180 priority patent/US9111048B2/en
Priority to US14/797,970 priority patent/US9471527B2/en
Priority to US15/257,666 priority patent/US9720870B2/en
Priority to US15/627,821 priority patent/US9996493B2/en
Priority to US15/978,272 priority patent/US10482052B2/en
Priority to US16/593,508 priority patent/US10877917B2/en
Priority to US17/100,161 priority patent/US11176079B2/en
Priority to US17/500,581 priority patent/US11762800B2/en
Priority to US18/364,970 priority patent/US20230376440A1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03828—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7201—Logical to physical mapping or translation of blocks or pages
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0012—High speed serial bus, e.g. IEEE P1394
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/38—Universal adapter
    • G06F2213/3804—Memory card connected to a computer port directly or by means of a reader/writer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/38—Universal adapter
    • G06F2213/3854—Control is performed at the peripheral side

Definitions

  • Embodiments described herein relate generally to a semiconductor device and memory system and, for
  • a method for communication between a memory system and a host device is described.
  • a transmission amount of data between the host device such as a digital camera or the like and a memory device or the like that records data continues to increase.
  • a high-speed serial transmission system based on a small amplitude differential signal is generally used from the viewpoint of simplifying connection cables, suppressing the power consumption and reducing EMI radiation noise.
  • FIG. 1 is a block diagram of a memory system according to a first embodiment
  • FIG. 2 is a diagram showing assignment of signals to signal pins in a memory card according to the first embodiment
  • FIG. 3 is a block diagram of a memory controller according to the first embodiment
  • FIG. 4 is a diagram showing symbols according to the first embodiment
  • FIG. 5 is. a timing chart for illustrating the state of communication according to the first
  • FIG. 6 is a flowchart for illustrating the operation of a symbol generation unit according to the first embodiment
  • FIG. 7 is a graph showing a frequency spectrum at the communication time
  • FIGS. 8 to 10 are graphs each showing a frequency spectrum according to the first embodiment
  • FIG. 11 is a block diagram of a memory controller according to a second embodiment
  • FIG. 12 is a timing chart for illustrating the state of communication according to the second
  • FIG. 13 is a flowchart for illustrating the operation of a memory system according to the second embodiment ;
  • FIG. 14 is a graph showing a frequency spectrum according to the second embodiment
  • FIG. 15 is a timing chart for illustrating the state of communication according to a modification of the second embodiment.
  • FIGS. 16 and 17 are timing charts each for illustrating the state of communication according to a third embodiment.
  • the semiconductor device capable of communicating with a host apparatus includes: a symbol generation unit; a coding unit; and a transmission unit.
  • the symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit.
  • the coding unit performs 8b/10b coding for the symbol.
  • the transmission unit transmits the symbol coded by the 8b/10b coding unit to the host apparatus.
  • a semiconductor device and memory system according to a first embodiment will be explained by taking an SD memory card (hereinafter simply referred to as a memory card) as an example.
  • FIG. 1 is a block diagram of a memory card according to the present embodiment .
  • a memory card 1 is communicable with a host device 2 such as a personal computer, digital camera and the like, for example.
  • the host device 2 includes software and hardware used for accessing the memory card 1 connected thereto via a bus interface 14.
  • the memory card 1 is operated in response to reception of power supply when it is connected to the host device 2 and performs a process corresponding to access from the host device 2.
  • the memory card 1 transfers information with respect to the host device 2 via the bus interface 14.
  • the memory card 1 includes a NAND flash memory chip (also simply referred to as a NAND flash memory or flash memory) 11, a memory controller 12 that controls the NAND flash memory chip 11 and a plurality of signal pins (first to seventeenth pins) 13.
  • the plural signal pins 13 are electrically connected
  • FIG. 2 is a table showing the first to seventeenth pins and signals assigned to them.
  • Data 0 to data 3 are respectively assigned to the seventh, eighth, ninth and first pins.
  • the first pin is also assigned to a card detection signal.
  • the second pin is assigned to command CMD, the third and sixth pins to ground potential GND, the fourth pin to power source potential VDD, and the fifth pin to clock signal CLK.
  • the tenth, thirteenth, fourteenth and seventeenth pins are assigned to supply voltage VDD or ground potential GND. Further, data (D1+) and data
  • D1- data (D0+) and data (DO-) that make pairs of differential signals are respectively assigned to the eleventh, twelfth, fifteenth and sixteenth pins.
  • the above pins are terminals for complementary signals in small amplitude differential signals.
  • a signal pair of D0+ and DO- is used for signal
  • a signal pair of D1+ and Dl- is used for signal transmission from the memory card 1 to the host device 2.
  • the memory card 1 is formed to be removably inserted with respect to a slot formed in the host device 2.
  • a host controller (not shown) provided in the host device 2 communicates various signals and data items with the memory controller 12 in the memory card
  • the controller transmits a write command as a serial signal to the memory controller 12 via the eleventh and twelfth pins. At this time, the memory controller 12 fetches write commands supplied to the eleventh and twelfth pins in response to a clock signal supplied to the seventh and eighth pins.
  • the write commands are serially input to the memory controller 12 by using only the eleventh and twelfth pins.
  • the eleventh and twelfth pins assigned to the command inputs are arranged as shown in FIG. 2 and a plurality of signal pins 13 and the bus interface 14 (SD interface) corresponding thereto are used to permit the memory card 1 and the host controller in the host device 2 to communicate with each other.
  • the NAND flash memory 11 and the memory controller 12 are connected by input/output (I/O) lines of 8 bits, for example, although not shown in the drawing here.
  • the memory controller 12 when the memory controller 12 writes data in the NAND flash memory 11, the memory controller 12 sequentially inputs a data input command 80H, column address, page address, data, and program command ' 1OH to the flash memory 11 via the I/O lines.
  • "H" of command 80H indicates a hexadecimal number and, in practice, signals of 8 bits of "10000000" are supplied in parallel to the I/O lines of 8 bits. That is, commands of a plurality of bits are supplied in parallel to the interface for the NAND flash memory.
  • the command and data for the NAND flash memory 11 commonly utilize the same I/O lines and are
  • the interface via which the host controller in the host device 2 and the memory card 1 communicate and the interface via which the NAND flash memory 11 and the memory controller 12 communicate are different.
  • the NAND flash memory 11 has the known configuration, and therefore, the explanation thereof is omitted.
  • the memory controller 12 manages the internal physical state of the NAND flash memory 11 (for example,
  • the memory controller 12 performs the operation of reading data from the NAND flash memory 11 according to a reguest of the host device 12, transferring the same to the host device 2 and writing write data supplied from the host device 2 in the NAND flash memory 11.
  • FIG. 3 is a block diagram of the memory controller 12. As shown in the drawing, the memory controller 12 includes a flash controller 21, buffer 22, command/data control unit 23, symbol generation unit 24, 8b/10b coding unit 25, host interface module 26, micro
  • MPU processing unit
  • ROM read-only memory
  • RAM random access memory
  • the flash controller 21 performs an interface process between the memory controller 12 and the NAND flash memory 11 based on control of the MPU 27. For example, at the data read time, it receives read data transferred from the NAND flash memory 11 and stores the same in the buffer 22.
  • the buffer 22 temporarily holds the read data and outputs the same to the command/data control unit 23.
  • the symbol generation unit 24 includes a random number generation circuit 32, issues various symbols (also called commands or control signals) required for communication with the host device 2 based on control of the MPU 27 and outputs the same to the command/data control unit 23.
  • a random number generation circuit 32 for example, a linear feedback shift register can be used. Of course, it is not limited to this.
  • the symbol generation unit 24 can issue a symbol indicating an idle state at the data non-communication time. Then, the symbol generation unit 24 can generate a plurality of types of symbols as the symbol
  • the command/data control unit 23 selects one of read data from the buffer 22 and a symbol from the command/data control unit 23 and outputs the same to the 8b/10b coding unit 25 according to control of the MPU 27.
  • the 8b/10b coding unit 25 performs 8b/10b coding for a signal (read data or symbol) supplied from the command/data control unit 23 and outputs the result to the host interface module 26.
  • the 8b/10b coding is a process for coding a signal of 8 bits to 10 bits. The coding is performed by use of a certain table and the coding result is expressed by symbol Dxx.x. That is, 8-bit data of "00H" to "FFH" is expressed by one of symbols of DOO.O to D31.7. The symbols are
  • the host interface module 26 performs an interface process with respect to the host device 2. As shown in FIG. 3, the host interface module 26 includes a
  • the parallel-to-serial conversion unit 30 converts 10-bit parallel data supplied from the 8b/10b coding unit 25 to serial data and outputs the same to the serial output port 31.
  • the serial output port 31 transmits the received serial data to the host device 2 via the bus interface 1 .
  • the MPU 27 controls the whole operation of the memory card 1.
  • the MPU 27 forms various tables on the RAM 29 by reading firmware (control program) stored in the ROM 28 on the RAM 29 and
  • the MPU. 27 receives a write command, read command and erase command from the host device 2 and controls the operations of the flash controller 21, command/data control unit 23, symbol generation unit 24, 8b/10b coding unit 25 and host interface module 26 according to the received command .
  • the ROM 28 stores a control program and the like executed by the MPU 27.
  • the RAM 29 is used as a work area of the MPU 27 and stores control programs and various tables. ⁇ Symbols Generated by Symbol Generation Unit 24> Next, some of symbols generated by the symbol generation unit 24 are explained with reference to FIG. 4.
  • FIG. 4 is a table showing symbol names of symbols generated by the symbol generation unit 24, the functions thereof and codes obtained by 8b/10b coding.
  • the symbol generation unit 24 can generate symbols SYN, COM, LIDLO and LIDLl.
  • Symbol SYN is a signal used to attain synchronization with the host device and coded to symbol D31.5 by
  • Symbol COM is a signal indicating comma (i.e. delimiter or division between the symbols) and coded to symbol K28.5 by 8b/10b coding.
  • Symbols LIDLO and LIDLl are signals indicating an idle state in which no data communication is performed between the memory card 1 and the host device 2.
  • Symbol LIDLO is a signal coded to symbol K28.3 by 8b/10b coding and symbol LIDLl is a signal coded to symbol D13.2, D19.2 or D18.5.
  • FIG. 5 is a timing chart of signals transmitted from the memory card 1 to the host device 2.
  • the memory card 1 As shown in the drawing, the memory card 1
  • symbol set SYNC used to set up synchronization with the host device 2 to the host device 2.
  • Symbol set SYNC is a combination of symbol COM and symbol SYN.
  • One symbol set SYNC including symbols COM, SYN is continuously transmitted (times tO to tl) until synchronization with the host device 2 is attained.
  • the operation of the memory controller 21 in a period of times tO to tl is as follows. That is, when detecting connection to the host device 2, the MPU instructs the symbol generation unit 24 to generate symbols COM, SYN. In response to this, the symbol generation unit 24 repeatedly generates symbols COM, SYN and outputs the same to the command/data control unit 23. Further, the command/data control unit 23 transfers symbols COM, SYN supplied from the symbol generation unit 24 to the 8b/10b coding unit 25
  • the 8b/10b coding unit 25 respectively codes received symbols COM, SYN to symbols K28.5, D31.5 according to the instruction of the MPU 27 and outputs the same to the host interface module 26. Then, the host interface module 26 transmits received symbols K28.5, D31.5 to the host device 2.
  • synchronization with the host device 2 is set up at time tl, data communication is performed. That is, as shown by times tl to t2 of FIG. 5, a data signal is transmitted from the memory card 1 to the host device 2.
  • the data signal is a series of D-codes obtained by 8b/10b coding.
  • the operation of the memory controller 12 in a period of times tl to t2 is as follows. That is, when receiving a data read command and address from the host device 2, the MPU 27 issues a read command and address with respect to the NAND flash memory 11 and instructs the NAND flash memory 11 to read data via the flash controller 21. Then, read data corresponding to the transmitted address is received by the flash controller 21 and stored in the buffer 22. Subsequently, the command/data control unit 23 transfers read data from the buffer 22 to the 8b/10b coding unit 25 according to the instruction of the MPU 27. Then, the 8b/10b coding unit 25 codes the received data to a corresponding D- code according to the instruction of the MPU 27 and outputs the result to the host interface module 26. After this, the host interface module 26 transmits the received D-code to the host device 2.
  • the memory card 1 When data communication is completed at time t2, the memory card 1 is set to an idle state and transmits symbol set IDL indicating the idle state to the host device 2.
  • Symbol set IDL is a combination of symbol COM and symbol LIDLO or LIDLl.
  • LIDLx 0 or 1 .
  • One symbol set IDL containing symbols COM and LIDLx is continuously transmitted (times t2 to t3) until next data
  • the operation of the memory controller 12 in a period from times tl to t2 is as follows. That is, when detecting that non-transmitted data to the host device 2 is no more present in the buffer 2, the MPU 27 instructs the symbol generation unit 24 to generate symbols COM and LIDLx. In response to this, the symbol generation unit 24 repeatedly generates symbols COM and LIDLx and outputs the same to the command/data control unit 23. Further, the command/data control unit 23 transfers symbols COM and LIDLx supplied from the symbol generation unit 24 to the 8b/10b coding unit 25 according to the instruction of the MPU 27. Then, the 8b/10b coding unit 25 codes received symbol COM to symbol K28.5 according to the instruction of the MPU 27. Further, when receiving symbol LIDLO, it codes the same to symbol K28.3 and when receiving symbol LIDLl, it codes the same to symbol D13.2, D19.2 or D18.5.
  • the host interface module 26 transmits the received symbol to the host device 2.
  • Symbol set IDL is repeatedly transmitted to the host device 2 until data communication is later started again with respect to the host device 2.
  • FIG. 6 is a flowchart for illustrating the operation of the symbol generation unit 24.
  • the symbol generation unit 24 first issues symbol COM (step Sll) . Subsequently, the symbol generation unit 24 confirms a random number generated from the random number generation circuit 32. Then, if the random number is a predetermined value ("first value") (YES in step S13) , it issues symbol LIDL0 (step S14) . On the other hand, if it is not the first value (NO in step S13) , it issues symbol LIDL1 (step S15) .
  • the probability of issuing symbol LIDL0 is the same as the probability of issuing symbol LIDL1. In that, the probability of issuing symbol LIDL0 is 50%, and the probability of issuing symbol LIDL1 also is 50%.
  • the above operation is repeatedly performed until connection with the host device 2 is broken (YES in step S16) or data transmission timing is reached (YES in step S10).
  • the random number generation circuit 32 may always generate a random number and generate the same only in a period while the MPU 27 gives an
  • synchronization is continuously transmitted at the dat transmission start time. After synchronization is set up, data transmission is started.
  • the idle symbol is a symbol to maintain synchronization with the host device.
  • symbol K28.3 (hereinafter referred to as symbol LIDL) can be used.
  • K28.3 is a code of w 001111_0010" or "110000_1101” in the binary notation and is a signal having "0" or "1" successively generated. Therefore, when symbol set COM+LIDL is successively transmitted, a signal having or 1 successively in a specified pattern is repeatedly transmitted. Then, there occurs a problem that the peak of a certain spectrum becomes large and this causes occurrence of noise, particularly, EMI noise by repeating a specified pattern of symbol set COM+LIDL. The state is shown in FIG. 7.
  • FIG. 7 The state is shown in FIG. 7.
  • FIG. 7 is a graph showing a frequency spectrum obtained as the result of simulation of a case wherein LIDL is used as the idle symbol, the abscissa represents the frequency in MHz and the ordinate represents the intensity in dB. As shown in the drawing, the frequency spectrum discretely occurs and the intensity thereof is relatively high and reaches 65 dB, particularly, around 200 MHz.
  • LIDL0, LIDL1 are used as the idle symbol.
  • LIDL among them is symbol K28.3 that is the same as LIDL, but LIDL1 is a symbol
  • LIDL0 different from LIDL0. Whether LIDL0 or LIDL1 is used as the idle symbol is randomly selected according to a random number generated by the random number generation circuit 32. As a result, the same "0"/"l" pattern is suppressed from being successively generated in the successive symbol set and radiation of harmonics contained in the pattern can be suppressed. Thus, occurrence of noise can be effectively suppressed while maintaining synchronization with the host device 2.
  • FIG. 8 is a graph showing a frequency spectrum obtained as the result of simulation of a case wherein D13.2 is used as LIDL1.
  • the peaks of the frequency spectrum are more successive (it is not discrete) in comparison with the example of FIG. 7 and, as a result, the intensity of each peak becomes low.
  • the peak intensity around 200 MHz is 50 dB and is lower than that of FIG. 7 by 15 dB.
  • a lowering of 15 dB corresponds to 1/30 in terms of electric power.
  • noise can be reduced by lowering the peak intensity.
  • FIGS. 9 and 10 are graphs showing
  • RD disparity
  • symbols are selected so that RD+ and RD- alternately appear in successive symbols.
  • RD of a next symbol is selected as a successor of immediately prior RD.
  • a symbol string that is 8b/10b-coded and transmitted utilizes a system in which codes of RD+ and RD- are alternately generated in order to maintain the DC balance.
  • codes of RD+ and RD- are alternately generated in order to maintain the DC balance.
  • LIDL symbols are transmitted like an IDL symbol set transmitted in the idle state, inversion of RD periodically occurs in a case where a method of creating a random form
  • RD is inverted for each symbol and a fixed pattern of 2-symbol period is transmitted. If such a periodic fixed pattern is transmitted, strong EMI noise occurs in the period and harmonic noise depending on the pattern occurs in frequencies that are integral multiple of the period.
  • inversion of RD occurs once in the IDL symbol set of COM, LIDL1 by using symbol D13.2, D19.2 or D18.5 that is set to RD ⁇ 0 as LIDL1.
  • an RD+ symbol is obtained by inverting the value of each bit of the RD- symbol. Therefore, in the symbol set in which RD is inverted, spectral components are set in a phase-inverted relationship. Therefore, if the IDL symbol sets of COM and LIDLO that sandwich the IDL symbol set configured by COM and LIDL1 are transmitted, spectral components of the IDL symbol sets of COM and LIDLO cancel each other and the effect of suppressing harmonic noise depending on. the pattern can be
  • LIDL symbols D13.2, D19.2 and D18.5 explained in the above embodiment are each set to a symbol that becomes RD ⁇ 0 and the EMI noise
  • suppressipn effect can be attained by a combination with LIDLO (K28.3). Further, the above symbols are symbols in which it is confirmed that the suppression effect is large by simulation among a plurality of LIDLl symbol candidates that become RD ⁇ 0.
  • random number data is included in a symbol set instead of using plural types of symbols as an idle symbol.
  • FIG. 11 is a block diagram of a memory controller 12 according to the present embodiment. As shown in the drawing, the memory controller 12 according to the present embodiment is formed with the configuration in which a scramble data generation unit 33 is further provided in the configuration of FIG. 3 explained in the first embodiment.
  • the scramble data generation unit 33 includes a random number generation circuit 34. Then, it
  • An 8b/10b coding unit 25 has a function of performing 8b/10b coding for scramble data SRDi
  • a symbol generation unit 24 issues one type of symbol LIDL as an idle symbol.
  • Symbol LIDL is K28.3, for example. That is, the configuration in which only LIDLO can be issued as the idle symbol in the first embodiment is provided.
  • FIG. 12 is a timing chart of signals transmitted from the memory card 1 to the host device 2 and corresponds to FIG. 5 in the first embodiment.
  • the memory card 1 When data communication is completed at time t2, the memory card 1 is set into an idle state and
  • symbol set IDL is a combination of symbol COM, symbol LIDL and a symbol corresponding to scramble data SRDi generated by the scramble data generation unit 33. Since
  • scramble data SRDi is a random number generated by the random number generation circuit 34, the value of scramble data SRDi varies each time symbol set IDL is generated.
  • One symbol set IDL containing symbols COM, LIDL and SRDi is successively transmitted (times t2 to t3) until next data communication is started (time t3) .
  • the operation of the memory controller 12 in a period of times t2 to t3 is as follows. That is, when detecting that non-transmitted data to the host device
  • the MPU 27 instructs the symbol generation unit 24 to generate symbols COM and LIDL. In response to this, the symbol generation unit 24 repeatedly generates symbols COM and LIDL and outputs the same to a command/data control unit 23. Further, the MPU 27 instructs the scramble data generation unit 33 to generate scramble data SRDi. In response to this, the scramble data generation unit 33 generates scramble data SRDi using the random number generation circuit 34 and outputs the same to the command/data control unit 23. Then, the command/data control unit 23 transfers symbols COM and LIDL supplied from the symbol generation unit 24 and scramble data SRDi supplied from the scramble data generation unit 33 to the 8b/10b coding unit 25 according to the
  • the 8b/10b coding unit 25 performs 8b/10b coding for received symbols COM, LIDL and scramble data SRDi according to the instruction of the MPU 27.
  • a host interface module 26 transmits the received symbols to the host device 2.
  • Symbol set IDL is repeatedly transmitted to the host device 2 until data communication is later started again with respect to the host device 2.
  • FIG. 13 is a flowchart for illustrating the operations of the symbol generation unit 24 and
  • step S10 the symbol generation unit 24 first issues symbol COM (step Sll) and subsequently issues symbol LIDL (step S20) . Further, the scramble data generation unit 33 generates scramble data SRDi (step S21) .
  • the above operation is repeatedly performed until connection with the host device 2 is broken (YES in step S16) or data transmission timing is reached (YES in step S10).
  • the random number generation circuit 34 may always generate a random number and generate the same only in a period while the MPU 27 gives an
  • scramble data SRDi is contained in a symbol set instead of setting the number of types of idle symbols to one type (LIDL: K28.3) .
  • Scramble data SRDi is generated by the random number generation circuit 34. More specifically, the scramble data is a byte string generated by an M sequence and is a random number formed by a generator polynomial
  • FIG. 14 is a graph of a frequency spectrum showing the result of simulation of the present embodiment. As shown in the drawing, the spectrum becomes more continuously and the peak
  • the peak intensity around 200 MHz is approximately 60 dB and is reduced by 5 dB in comparison with a case of FIG. 7. As a result, noise can be reduced.
  • FIG. 15 is a timing chart of signals transmitted from the memory card 1 to the host device 2, for illustrating a case wherein 2-byte scramble data items SRDi, SRD(i+l) are contained in one symbol set.
  • the first symbol set is COM+LIDL+SRD0+SRD1
  • a symbol set following this is COM+LIDL+SRD2+SRD3 and they are similarly determined.
  • the spectrum can be more widely spread and noise can be reduced by increasing the number of bytes of scramble data.
  • the present embodiment is attained by applying the first embodiment to symbol SYN (hereinafter referred to as a synchronization symbol) . That is, in the present embodiment, two types of SYN (SYNO, SYN1) are generated instead of generating two types of LIDL in the first embodiment. The other is the same as that of the first embodiment, and therefore, it is simply explained below .
  • FIG. 16 is a timing chart of signals transmitted from a memory card 1 to a host device 2. As shown in the drawing, as symbol set SYNC used to set up synchronization with the host device 2, COM+SYN0 or COM+SYN1 is selected. Whether SYN0 or SYN1 is selected.
  • symbol set SYNC is repeatedly transmitted. Therefore, also, in this period, there occurs a possibility that a signal in which "0"/"l” successively occurs in a certain pattern may be repeated. However, a signal in which "0"/"l” successively occurs in a certain pattern can be
  • the present embodiment is attained by applying the second embodiment to symbol SYN (hereinafter referred to as a synchronization symbol) . That is, in the present embodiment, scramble data SRDi is not instead in symbol set IDL as in the second embodiment but included in symbol set SYNC. The other is the same as that of the second embodiment and it is simply
  • FIG. 17 is a timing chart of signals transmitted from a memory card 1 to a host device 2. As shown in the drawing, symbol set SYNC used to set up
  • scramble data contained in one symbol set SYNC may be set to two bytes or more.
  • the semiconductor device 12 and memory system 1 can communicate with the host apparatus 2.
  • the device 12 and system 1 includes a symbol generation unit 24 which includes a random number generation circuit 32 and generates a symbol LIDL0, LIDLl (or SYN0, SYN1) according to a random number generated by the random number generation circuit 32; a coding unit
  • semiconductor device 12 and memory system 1 can communicate with the host apparatus 2.
  • the device can communicate with the host apparatus 2.
  • system 1 includes a symbol generation unit 24 capable of generating a symbol; a scramble data
  • generation unit 33 capable of generating scramble data SRD; a coding unit 25 which performs 8b/10b coding for the symbol and scramble data SRD; and a transmission unit 26 which transmits, to the host apparatus 2, the symbol and scramble data SRD coded by the 8b/10b coding unit 25 as one symbol set.
  • the symbol indicates an idle state which is non-communication period with the host device
  • the symbol generation unit 24 may be configured to generate three or more types of idle symbols and synchronization symbols. Even in the case of three or more types, one of the symbols to be generated is determined according to a random number. Further, the symbol generation unit 24 may generate a plurality of symbols, then select one of them according to a random number and output the selected symbol to the command/data control unit 23 without determining a to-be-generated symbol according to a random number.
  • symbol set IDL at an idle time may be configured by use of symbol COM+(LIDL0 or
  • synchronization time may be configured by use of symbol COM+(SYN0 or SYNl)+SRDi.
  • the first or second embodiment and the third or fourth embodiment can be simultaneously performed. That is, a plurality of symbols may be prepared for both of the idle symbol and synchronization symbol or scramble data may be added thereto.
  • the first to fourth embodiments can be applied to a symbol other than the idle symbol and synchronization symbol. That is, if another symbol in which it is assumed to cause occurrence of noise due to repetition of a signal in which "0"/"l" successively occurs in a certain pattern is used, the same effect can be attained by preparing plural types of symbols and randomly selecting one of them or adding random data thereto.
  • data may be transmitted to the host device 2 while it is kept set in the scrambled state.
  • the scramble data generation unit 33 may be provided between the buffer and the command/data control unit 23 and read data supplied from the buffer 22 may be scrambled by the scramble data generation unit 33.
  • the recent transmission speed of high-speed serial data transmission by use of a small amplitude differential signal is increased to 1 Gbps or more. Then, in the high-speed data transmission of 1 Gbps or more, a system for multiplexing a data signal and clock signal on the same signal line and
  • a clock multiplex system In the clock multiplex system, a clock is played back by detecting a signal toggle of a transmission signal on the data reception side and is used as a clock signal for reception. If the first to fourth embodiments are applied to the above extremely high-speed data transmission system, a more significant effect can be attained.
  • generation of the symbols and random data explained in the first to fourth embodiments may be performed by use of hardware or performed by use of software. However, from the viewpoint of operation speed, it is desirable to use exclusive hardware.
  • the operation shown in FIG. 6 is performed by storing a symbol generation program in a ROM 28 or the like and permitting an MPU 27 to execute the program. This also applies to generation of random data.
  • the host interface module 26 includes a serial input port and serial-to-parallel conversion unit. Then, the serial input port receives a signal from the host device 2 and the serial-to- parallel conversion unit converts the same to a
  • the 8b/10b coding unit 25 codes 10-bit parallel data to 8 bits and stores the same in the buffer 22. Then, the MPU 27 issues a data write command with respect to the NAND flash memory 11 and outputs data to the NAND flash memory 11 via the flash controller 21.
  • the memory card 1 also receives symbol set SYNC from the host device 2. Further, it receives symbol set IDL from the host device 2 at an idle time.
  • the symbols may be symbols selected from a plurality of symbols based on a random number or symbols to which scramble data is added. That is, not only the memory card 1 but also the host device 2 may have the configuration according to the first to fourth embodiments and the above embodiments are intended to contain the above
  • the SD memory card is used as the memory system as an example, but another device having an SD interface such as an SD 10 device or ultra-high ⁇ speed (UHS) II card may be used and the other device may be used.
  • SD 10 device or ultra-high ⁇ speed (UHS) II card
  • UHS ultra-high ⁇ speed
  • it is not limited to a memory card having the NAND flash memory 11, another storage medium may be used and an electronic device that performs high-speed data transfer can be widely applied without being limited to the storage medium.

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  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
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Abstract

Selon un mode de réalisation, un dispositif à semi-conducteur (1, 12) apte à communiquer avec un appareil hôte (2) comprend une unité de génération de symbole (24), une unité de codage (25), et une unité d'envoi (26). L'unité de génération de symbole (24) comprend un circuit de génération de nombre aléatoire (32) et génère un symbole en fonction d'un nombre aléatoire généré par le circuit de génération de nombre aléatoire (32). L'unité de codage (25) réalise un codage 8b/10b pour le symbole. L'unité d'envoi (26) envoie le symbole codé par l'unité de codage 8b/10b (25) à l'appareil hôte (2).
PCT/JP2010/066464 2009-12-09 2010-09-15 Dispositif à semi-conducteur et système de mémoire WO2011070837A1 (fr)

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US13/514,736 US8781024B2 (en) 2009-12-09 2010-09-15 Semiconductor device and memory system
CN201080056003.7A CN102652299B (zh) 2009-12-09 2010-09-15 半导体设备和存储器系统
KR1020127014714A KR101431930B1 (ko) 2009-12-09 2010-09-15 반도체 장치 및 메모리 시스템
EP10835759.1A EP2510419B1 (fr) 2009-12-09 2010-09-15 Dispositif à semi-conducteur et système de mémoire
US14/292,180 US9111048B2 (en) 2009-12-09 2014-05-30 Semiconductor device and memory system
US14/797,970 US9471527B2 (en) 2009-12-09 2015-07-13 Semiconductor device and memory system
US15/257,666 US9720870B2 (en) 2009-12-09 2016-09-06 Semiconductor device and memory system
US15/627,821 US9996493B2 (en) 2009-12-09 2017-06-20 Semiconductor device and memory system
US15/978,272 US10482052B2 (en) 2009-12-09 2018-05-14 Semiconductor device and memory system
US16/593,508 US10877917B2 (en) 2009-12-09 2019-10-04 Semiconductor device and memory system
US17/100,161 US11176079B2 (en) 2009-12-09 2020-11-20 Semiconductor device and memory system
US17/500,581 US11762800B2 (en) 2009-12-09 2021-10-13 Semiconductor device and memory system
US18/364,970 US20230376440A1 (en) 2009-12-09 2023-08-03 Semiconductor device and memory system

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US14/292,180 Continuation US9111048B2 (en) 2009-12-09 2014-05-30 Semiconductor device and memory system

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2630172C2 (ru) * 2012-05-11 2017-09-05 Морфо Способ и устройство для передачи сообщения

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5657242B2 (ja) * 2009-12-09 2015-01-21 株式会社東芝 半導体装置及びメモリシステム
JP2013140541A (ja) 2012-01-06 2013-07-18 Toshiba Corp 半導体記憶装置
US9270417B2 (en) * 2013-11-21 2016-02-23 Qualcomm Incorporated Devices and methods for facilitating data inversion to limit both instantaneous current and signal transitions
EP2892156A3 (fr) * 2013-12-27 2015-10-28 Altera Corporation Appareil de codage amélioré et procédés associés
FR3032576B1 (fr) 2015-02-05 2017-03-10 St Microelectronics Grenoble 2 Procede de codage en ligne a bit de polarite utilisant des trames aperiodiques
CN104579583A (zh) * 2015-02-09 2015-04-29 浪潮电子信息产业股份有限公司 一种对8b/10b编码方式的改进方法
JP6398801B2 (ja) * 2015-03-09 2018-10-03 沖電気工業株式会社 メモリ装置へのデータ書き込み／読み出し制御方法及びメモリ装置
US10013944B2 (en) 2015-11-27 2018-07-03 Panasonic Liquid Crystal Display Co., Ltd. Display device and source driver for bit conversion of image data
CN106791950A (zh) * 2016-12-27 2017-05-31 深圳Tcl数字技术有限公司 高速信号传输系统、高速信号传输方法及装置
US20180308214A1 (en) * 2017-04-21 2018-10-25 Intel Corporation Data scrambling mechanism
US11093811B2 (en) * 2017-06-05 2021-08-17 Kioxia Corporation Memory card with multiple modes, and host device corresponding to the memory card
JP7292864B2 (ja) * 2018-04-23 2023-06-19 キオクシア株式会社 半導体記憶装置
CN115421928B (zh) * 2022-11-04 2023-01-31 摩尔线程智能科技(北京)有限责任公司 减少芯片产生的电磁干扰的装置、方法和电子设备

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020018492A1 (en) 2000-06-19 2002-02-14 Koji Sakai Transmission method and transmission system as well as communications device
JP2003204363A (ja) * 2002-01-04 2003-07-18 Hitachi Ltd シリアル伝送方式
JP2004171561A (ja) * 2002-11-15 2004-06-17 Hewlett-Packard Development Co Lp メモリ構成要素内でデータを管理するメモリ・コントローラ

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5229769A (en) * 1992-02-21 1993-07-20 Advanced Micro Devices, Inc. Method and circuit for performing running disparity measurements
US5304996A (en) * 1992-02-21 1994-04-19 Advanced Micro Devices, Inc. 8B/10B encoder providing one of pair of noncomplementary, opposite disparity codes responsive to running disparity and selected commands
US6657949B1 (en) * 1999-07-06 2003-12-02 Cisco Technology, Inc. Efficient request access for OFDM systems
US6625716B2 (en) * 2001-06-28 2003-09-23 Intel Corporation Method apparatus, and system for efficient address and data protocol for a memory
US7092629B2 (en) * 2001-11-19 2006-08-15 Hewlett-Packard Development Company, L.P. Time-division and wave-division multiplexed link for use in a service area network
JP4081541B2 (ja) * 2002-03-11 2008-04-30 富士フイルム株式会社 撮像通信システム
US7917673B2 (en) * 2003-09-20 2011-03-29 Samsung Electronics Co., Ltd. Communication device and method having a shared local memory
US6876315B1 (en) * 2004-03-12 2005-04-05 International Business Machines Corporation DC-balanced 6B/8B transmission code with local parity
US7386027B2 (en) * 2004-03-31 2008-06-10 Matsushita Electric Industrial Co., Ltd. Methods and apparatus for generating and processing wideband signals having reduced discrete power spectral density components
US7081838B2 (en) * 2004-12-29 2006-07-25 Enigma Semiconductor, Inc. 16b/10s coding apparatus and method
US7782805B1 (en) * 2005-02-08 2010-08-24 Med Belhadj High speed packet interface and method
US7292161B2 (en) * 2005-05-31 2007-11-06 International Business Machines Corporation NB/MB coding apparatus and method using both disparity independent and disparity dependent encoded vectors
KR100707308B1 (ko) * 2005-06-13 2007-04-12 삼성전자주식회사 엠엠씨 인터페이스를 갖는 플래시 메모리 장치 및 그것을포함한 메모리 시스템
KR100799574B1 (ko) 2005-12-08 2008-01-31 한국전자통신연구원 서비스 품질 보장형 스위치드 라우터 시스템
US8988223B2 (en) * 2005-12-09 2015-03-24 Tego Inc. RFID drive management facility
KR100782327B1 (ko) * 2006-05-27 2007-12-06 삼성전자주식회사 반도체 장치 사이의 단일형 병렬데이터 인터페이스 방법,기록매체 및 반도체 장치
WO2007145316A1 (fr) * 2006-06-15 2007-12-21 Panasonic Corporation Contrôleur de mémoire, dispositif de stockage non volatil et système pour le dispositif de stockage non volatil
JP5002201B2 (ja) * 2006-06-30 2012-08-15 株式会社東芝 メモリシステム
JP4908083B2 (ja) * 2006-06-30 2012-04-04 株式会社東芝 メモリコントローラ
US7383992B2 (en) * 2006-10-10 2008-06-10 Imation Corp. Memory card with host interface and including internal interface for receiving micro-size memory cards
US7492291B2 (en) * 2006-10-20 2009-02-17 Agere Systems Inc. Methods and apparatus for interfacing a plurality of encoded serial data streams to a serializer/deserializer circuit
KR100849956B1 (ko) 2007-01-29 2008-08-01 삼성전자주식회사 반도체 장치 및 그것의 스크램블된 데이터 전송 방법
EP1973285A1 (fr) * 2007-03-23 2008-09-24 Nokia Siemens Networks Gmbh & Co. Kg Procédé et récepteur pour le décodage d'informations numériques
US8665735B2 (en) * 2007-07-20 2014-03-04 Broadcom Corporation Method and system for quality of service management in a multi-standard mesh of networks
US8233622B2 (en) * 2008-06-18 2012-07-31 International Business Machines Corporation Transmitting parallel data via high-speed serial interconnection
US7769048B2 (en) * 2008-06-25 2010-08-03 Intel Corporation Link and lane level packetization scheme of encoding in serial links
CN101677399B (zh) * 2008-09-18 2014-07-09 香港科技大学 基于流密码的安全编码方案的多媒体内容编码方法和系统
JP5375320B2 (ja) * 2009-05-08 2013-12-25 富士通株式会社 通信制御方法、通信システム及び通信装置
JP5657242B2 (ja) * 2009-12-09 2015-01-21 株式会社東芝 半導体装置及びメモリシステム

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020018492A1 (en) 2000-06-19 2002-02-14 Koji Sakai Transmission method and transmission system as well as communications device
JP2002084247A (ja) * 2000-06-19 2002-03-22 Sharp Corp 伝送方法および伝送システム並びに通信装置
JP2003204363A (ja) * 2002-01-04 2003-07-18 Hitachi Ltd シリアル伝送方式
JP2004171561A (ja) * 2002-11-15 2004-06-17 Hewlett-Packard Development Co Lp メモリ構成要素内でデータを管理するメモリ・コントローラ

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
DAVID ROBERT STAUFFER: "High-Speed Serdes Devices and Applications", 2008, PUBLISHED BY SPRINGER, pages: 140 - 143
See also references of EP2510419A4

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2630172C2 (ru) * 2012-05-11 2017-09-05 Морфо Способ и устройство для передачи сообщения

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US20180260355A1 (en) 2018-09-13
US20160371217A1 (en) 2016-12-22
US10877917B2 (en) 2020-12-29
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US11176079B2 (en) 2021-11-16
US9720870B2 (en) 2017-08-01
US20170300448A1 (en) 2017-10-19
US20150317270A1 (en) 2015-11-05
US20140281097A1 (en) 2014-09-18
TW201145038A (en) 2011-12-16
EP2510419B1 (fr) 2018-09-05
EP2510419A4 (fr) 2017-06-07
CN104965805B (zh) 2018-01-09
US20200034324A1 (en) 2020-01-30
CN102652299B (zh) 2015-07-08
US20220066973A1 (en) 2022-03-03
CN102652299A (zh) 2012-08-29
JP2011123609A (ja) 2011-06-23
US8781024B2 (en) 2014-07-15
US20210073164A1 (en) 2021-03-11
KR101431930B1 (ko) 2014-08-19
US20120243636A1 (en) 2012-09-27
CN104965805A (zh) 2015-10-07
US10482052B2 (en) 2019-11-19
US11762800B2 (en) 2023-09-19
EP2510419A1 (fr) 2012-10-17
US9471527B2 (en) 2016-10-18

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