WO2011069230A1 - Réseau d'impédances pour produire une somme pondérée d'entrées - Google Patents

Réseau d'impédances pour produire une somme pondérée d'entrées Download PDF

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Publication number
WO2011069230A1
WO2011069230A1 PCT/CA2009/001818 CA2009001818W WO2011069230A1 WO 2011069230 A1 WO2011069230 A1 WO 2011069230A1 CA 2009001818 W CA2009001818 W CA 2009001818W WO 2011069230 A1 WO2011069230 A1 WO 2011069230A1
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WO
WIPO (PCT)
Prior art keywords
sets
network
impedance
branches
branch
Prior art date
Application number
PCT/CA2009/001818
Other languages
English (en)
Inventor
Martin Mallinson
Original Assignee
Ess Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ess Technology, Inc. filed Critical Ess Technology, Inc.
Priority to US13/515,254 priority Critical patent/US8766841B2/en
Priority to PCT/CA2009/001818 priority patent/WO2011069230A1/fr
Publication of WO2011069230A1 publication Critical patent/WO2011069230A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/78—Simultaneous conversion using ladder network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/14—Arrangements for performing computing operations, e.g. operational amplifiers for addition or subtraction 
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H15/00—Transversal filters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/68—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/78—Simultaneous conversion using ladder network
    • H03M1/785—Simultaneous conversion using ladder network using resistors, i.e. R-2R ladders
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/80—Simultaneous conversion using weighted impedances
    • H03M1/808—Simultaneous conversion using weighted impedances using resistors

Definitions

  • This invention relates to the digital to analog conversions.
  • this invention relates to an impedance selection network for producing a weighted sum of input values useful in Digital to Analog Converter and signal processing applications.
  • Voltages or currents may be manipulated in resistor networks under digital control if switches are used to vary the connectivity of the resistors.
  • the network can be considered a DAC (Digital to Analog Converter) since it commonly results in an analog output parameter proportional to the digital number applied, or sometimes a Multiplying DAC (MDAC) in cases where a conversion scale factor is involved.
  • DAC Digital to Analog Converter
  • MDAC Multiplying DAC
  • R-2R networks There are two distinct ways that R-2R networks can be connected to make a DAC: the so called “voltage mode DAC” and "current mode DAC". Each has its advantages and disadvantages, discussed in the paper by Walt Kester, available online at http://www.analog.com/static/imported- files/tutorials/MT-015.pdf. Of interest in the present case is the ability of multiple MDAC's to form a sum- of-products as is often required in signal processing and other applications. Since a voltage mode MDAC has constant output impedance, multiples MDACs may be connected to a common output node and the sum-of-products will appear as the voltage on that output node. However such sum-of-products configurations have limitations.
  • N ' ' where X is the analog input voltage, D the digital number applied and ⁇ the total number of MDACs used.
  • the invention comprises a digitally controllable impedance network that produces a weighted sum of products.
  • the invention draws inspiration from a recognition that the voltage at the node of star-connected resistor networks is tolerant of near zero value inputs applied to one or more of the branches, and that the branch resistors provide a weighting factor of 1/R of the branch input to the node output. Resistor dynamic range is further controlled by a novel branch and summing configuration.
  • the invention comprises a dynamically controllable switched impedance network comprising a plurality of branches of impedance components, the branches being connected in a star configuration to a summing output node.
  • each of the branches comprises at least one set of impedance components selectable by at least one active device in permutated combinations to achieve one of several possible impedance values for the set.
  • the set of impedance components are selectable to result in a parallel arrangement of all of the impedance components in the set.
  • each of the branches comprises a plurality of sets of such selectable impedance components.
  • the dynamically controllable network is digitally controllable, and the number of impedance components in each branch corresponds to the number of elements in a digital control signal.
  • the invention comprises such a network in which specific sets from a given branch are used to code sets of control bits of a given significance.
  • the respective sets from each branch that are used to code control bits of a given significance provide their outputs to the summing output node independently of the outputs of the other sets in their branch.
  • each set comprises successive impedance values that are multiples of the preceding impedance value.
  • an impedance component is provided between the summing output node and the output of each sets other than the sets used to code the most significant bits in the control signal.
  • each of the foregoing networks is used in a rotating coefficient signal processor for summing weighted values of a signal across a set of coefficients.
  • the networks are used in a rotating coefficient FIR filter.
  • the invention comprises a method of producing a weighted sum of input values, comprising providing a network of resistors grouped in sets and in branches of sets, the branches being connected in a star configuration to a common summing output node, under digital control selecting combinations of resistors in each set to apply an effective weighting value to each set, providing inputs to each of the branches and providing a summed output of the branches at the summing output node.
  • the sets within a branch correspond to the significance of bits in control signals applied to respective sets.
  • the method further comprises attenuating the contribution of the sets representing all but the most significant bits by applying an impedance between the output of such sets and the summing output node.
  • Fig. 1 is a diagram of a prior art rotating coefficient FIR filter
  • Fig. 2 is a circuit schematic of a prototype resistor selection network used in the development of the eventual preferred embodiment.
  • Fig. 3 is a circuit schematic showing the preferred embodiment of the invention.
  • the voltage present at the node in the center of a "star-connected" network is:
  • a resistor R would be connected between two nodes via an active device such as a switch such that when the switch is On', R appears between the nodes.
  • a resistor of value 2R is similarly connected (typically in parallel), as well as resistors of values 4R, 8R and so forth. Since they are connected in parallel, the conductances add, providing control of the total conductance (1/R) as required using permutated combinations of the various resistors.
  • a rotating coefficient FIR filter is represented in Fig. 1 , drawn from Figure 7 of a thesis by Cameron Lacy 1 .
  • the coefficients rotate in order to be applied to the samples that are taken in a "round-robin" fashion.
  • the star-connected network of the present invention may be used to provide the rotating coefficients in each branch of the filter, and the summing junction of the filter, provided an appropriate means of changing the coefficients in a relatively simple resistor network can be achieved.
  • Fig. 2 represents a form of segmented processor.
  • each branch comprises a plurality of sets of resistors selectable by an active device such as a switch.
  • the preferred embodiment avoids linking the sets through RL1 and RL2 on a branch by branch (that is tap by tap) basis. That is done by postponing the use of the link resistors to the top level.
  • the respective sets from each branch that are used to code control bits of a given significance provide their outputs to the summing output node "OUT" independently of the outputs from the other sets in their branch.
  • the sets of three most significant bits in each of the three branches of Fig. 3 sum their outputs at the summing output node without contribution from the other sets of those branches, save for the effect of the overall star-connected topology.
  • Fig. 3 shows three taps of the rotating coefficient FIR filter, with the MSB being at the top of each column and the LSB at the bottom.
  • Each branch is segmented into three three-bit sections and the maximum dynamic range of resistor values is 4:1.
  • the sets are arranged in groups to code control bits of a given significance. For example, the sets of three uppermost bits in each branch of Fig. 3 code for the 3 most significant control bits.
  • the link resistors RL1 and RL2 are not repeated in each individual branch - they are used only one time to merge each of the segments after they are summed - into the final output.
  • RL1 and RL2 are provided between the summing output node "OUT" and the output of each set other than the set of three most significant bits in the control signal.
  • each individual branch has varying output impedance, but the collection of branches has constant output impedance, hence one fixed value of RL1 (and RL2) works.
  • the impedance must be constant, because the same coefficients are rotating around and the branches are indistinguishable.
  • the "star connected" adjustable resistor network as disclosed has the advantage that when multiple branches are wired together at the output forming a sum-of-products network, there is no attenuation in the output even if many "near zero" coefficients are present in the control code.
  • the invention segments the branches, in a viable implementation of a rotating coefficient FIR filter. In general, a sufficient requirement for segmentation is that the total output impedance of each segment be constant.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Biomedical Technology (AREA)
  • Health & Medical Sciences (AREA)
  • Software Systems (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biophysics (AREA)
  • Data Mining & Analysis (AREA)
  • General Health & Medical Sciences (AREA)
  • Molecular Biology (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Computational Linguistics (AREA)
  • Artificial Intelligence (AREA)
  • Neurology (AREA)
  • Computer Hardware Design (AREA)
  • Networks Using Active Elements (AREA)
  • Filters That Use Time-Delay Elements (AREA)

Abstract

L'invention concerne un réseau de résistances sélectionnables de manière dynamique utilisé dans une configuration en étoile afin de produire une somme pondérée de valeurs d'entrée sans atténuation des contributions proches de zéro. Chaque branche du réseau connecté en étoile comprend des ensembles de composants d'impédance, de préférence des résistances, qui sont sélectionnables activement de manière à produire des combinaisons permutées de valeurs de pondération efficaces. Les bits de commande numérique des codes de résistances et les sorties des ensembles de résistances dans les branches respectives qui correspondent aux bits de commande les moins importants envoient leurs sorties vers le noeud de sortie d'addition indépendamment des ensembles de résistances correspondant aux bits de commande ayant une autre importance.
PCT/CA2009/001818 2009-12-11 2009-12-11 Réseau d'impédances pour produire une somme pondérée d'entrées WO2011069230A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US13/515,254 US8766841B2 (en) 2009-12-11 2009-12-11 Impedance network for producing a weighted sum of inputs
PCT/CA2009/001818 WO2011069230A1 (fr) 2009-12-11 2009-12-11 Réseau d'impédances pour produire une somme pondérée d'entrées

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CA2009/001818 WO2011069230A1 (fr) 2009-12-11 2009-12-11 Réseau d'impédances pour produire une somme pondérée d'entrées

Publications (1)

Publication Number Publication Date
WO2011069230A1 true WO2011069230A1 (fr) 2011-06-16

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Family Applications (1)

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PCT/CA2009/001818 WO2011069230A1 (fr) 2009-12-11 2009-12-11 Réseau d'impédances pour produire une somme pondérée d'entrées

Country Status (2)

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US (1) US8766841B2 (fr)
WO (1) WO2011069230A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9323959B2 (en) * 2012-03-21 2016-04-26 Ess Technology, Inc. Buffer-less rotating coefficient filter
US8937506B2 (en) * 2012-03-21 2015-01-20 Ess Technology, Inc. Rotating coefficient filter
US9124296B2 (en) * 2012-06-27 2015-09-01 Analog Devices Global Multi-stage string DAC
CN111801894A (zh) * 2018-01-05 2020-10-20 德克萨斯仪器股份有限公司 数模转换器系统

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4636772A (en) * 1985-01-17 1987-01-13 Riken Denshi Co. Ltd. Multiple function type D/A converter
US20090160690A1 (en) * 2007-12-25 2009-06-25 Seiko Epson Corporation D/a converter circuit, integrated circuit device, and electronic apparatus

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5059978A (en) * 1990-12-20 1991-10-22 Vlsi Technology, Inc. Resistor-string digital to analog converters with auxiliary coarse ladders
US6567026B1 (en) * 2000-06-22 2003-05-20 Analog Devices, Inc. Voltage scaling digital-to- analog converter with impedance strings
US6414616B1 (en) * 2000-06-22 2002-07-02 Analog Devices, Inc. Architecture for voltage scaling DAC
US6937178B1 (en) * 2003-05-15 2005-08-30 Linear Technology Corporation Gradient insensitive split-core digital to analog converter
KR100714612B1 (ko) * 2006-02-22 2007-05-07 삼성전기주식회사 고분해능을 갖는 디지털/아날로그 컨버팅 장치

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4636772A (en) * 1985-01-17 1987-01-13 Riken Denshi Co. Ltd. Multiple function type D/A converter
US20090160690A1 (en) * 2007-12-25 2009-06-25 Seiko Epson Corporation D/a converter circuit, integrated circuit device, and electronic apparatus

Also Published As

Publication number Publication date
US8766841B2 (en) 2014-07-01
US20130015995A1 (en) 2013-01-17

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