WO2011028004A3 - 미세회로 형성을 위한 임베디드용 동박 - Google Patents

미세회로 형성을 위한 임베디드용 동박 Download PDF

Info

Publication number
WO2011028004A3
WO2011028004A3 PCT/KR2010/005860 KR2010005860W WO2011028004A3 WO 2011028004 A3 WO2011028004 A3 WO 2011028004A3 KR 2010005860 W KR2010005860 W KR 2010005860W WO 2011028004 A3 WO2011028004 A3 WO 2011028004A3
Authority
WO
WIPO (PCT)
Prior art keywords
layer
copper foil
microcircuit
forming
embedded pattern
Prior art date
Application number
PCT/KR2010/005860
Other languages
English (en)
French (fr)
Other versions
WO2011028004A2 (ko
Inventor
류종호
양창열
Original Assignee
일진소재산업(주)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 일진소재산업(주) filed Critical 일진소재산업(주)
Priority to CN2010800387300A priority Critical patent/CN102577645A/zh
Priority to JP2012526669A priority patent/JP5464722B2/ja
Publication of WO2011028004A2 publication Critical patent/WO2011028004A2/ko
Publication of WO2011028004A3 publication Critical patent/WO2011028004A3/ko

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/205Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09009Substrate related
    • H05K2201/09036Recesses or grooves in insulating substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03Metal processing
    • H05K2203/0369Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03Metal processing
    • H05K2203/0376Etching temporary metallic carrier substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03Metal processing
    • H05K2203/0384Etch stop layer, i.e. a buried barrier layer for preventing etching of layers under the etch stop layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Electroplating And Plating Baths Therefor (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Abstract

캐리어동박층; 상기 캐리어동박층의 일표면에 형성된 배리어층; 및 상기 배리어층의 표면에 형성된 회로형성을 위한 씨드층; 으로 이루어지며, 상기 배리어층이 니켈 또는 니켈 합금층이며, 상기 씨드층이 구리층이며, 상기 씨드층 표면의 평균조도가 Rz: 1.5㎛ 미만, 및 Rmax: 2.5㎛ 미만인 노듈이 없는 임베디드패턴용 동박이 제시된다.
PCT/KR2010/005860 2009-09-01 2010-08-31 미세회로 형성을 위한 임베디드용 동박 WO2011028004A2 (ko)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN2010800387300A CN102577645A (zh) 2009-09-01 2010-08-31 用于形成微电路的用于嵌入图案的铜箔
JP2012526669A JP5464722B2 (ja) 2009-09-01 2010-08-31 微細回路の形成のためのエンベデッド用銅箔

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020090081909A KR101298999B1 (ko) 2009-09-01 2009-09-01 미세회로 형성을 위한 임베디드용 동박
KR10-2009-0081909 2009-09-01

Publications (2)

Publication Number Publication Date
WO2011028004A2 WO2011028004A2 (ko) 2011-03-10
WO2011028004A3 true WO2011028004A3 (ko) 2011-07-14

Family

ID=43649764

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2010/005860 WO2011028004A2 (ko) 2009-09-01 2010-08-31 미세회로 형성을 위한 임베디드용 동박

Country Status (4)

Country Link
JP (1) JP5464722B2 (ko)
KR (1) KR101298999B1 (ko)
CN (1) CN102577645A (ko)
WO (1) WO2011028004A2 (ko)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012132573A1 (ja) * 2011-03-25 2012-10-04 Jx日鉱日石金属株式会社 複合銅箔及びその製造方法
WO2012132574A1 (ja) * 2011-03-25 2012-10-04 Jx日鉱日石金属株式会社 複合銅箔及びその製造方法
JP6403969B2 (ja) * 2013-03-29 2018-10-10 Jx金属株式会社 キャリア付銅箔、プリント配線板、銅張積層板、電子機器及びプリント配線板の製造方法
JP6425401B2 (ja) * 2013-04-26 2018-11-21 Jx金属株式会社 高周波回路用銅箔、高周波回路用銅張積層板、高周波回路用プリント配線板、高周波回路用キャリア付銅箔、電子機器、及びプリント配線板の製造方法
TWI589201B (zh) * 2013-11-22 2017-06-21 Mitsui Mining & Smelting Co Manufacturing method of a printed circuit board having a buried circuit and a printed circuit board obtained by the manufacturing method
JP5870148B2 (ja) * 2013-11-27 2016-02-24 Jx金属株式会社 キャリア付銅箔、プリント回路板の製造方法、銅張積層板、銅張積層板の製造方法、及び、プリント配線板の製造方法
KR101682555B1 (ko) * 2015-08-07 2016-12-07 대덕전자 주식회사 미세 패턴 제조방법
CN112055759B (zh) 2018-04-24 2021-11-23 三菱瓦斯化学株式会社 铜箔用蚀刻液和使用其的印刷电路板的制造方法以及电解铜层用蚀刻液和使用其的铜柱的制造方法
CN111491456A (zh) * 2019-01-29 2020-08-04 上海美维科技有限公司 一种含有隐埋线路的印制电路板的制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2927968B2 (ja) * 1995-02-16 1999-07-28 三井金属鉱業株式会社 高密度多層プリント回路内層用銅箔および該銅箔を内層回路用に用いた高密度多層プリント回路基板
JP3081026B2 (ja) * 1991-07-18 2000-08-28 古河サーキットフォイル株式会社 プリント配線板用電解銅箔
JP2000269637A (ja) * 1999-03-18 2000-09-29 Furukawa Circuit Foil Kk 高密度超微細配線板用銅箔
KR20050045903A (ko) * 2003-11-11 2005-05-17 후루카와서키트호일가부시끼가이샤 캐리어 부착 극박 동박, 및 캐리어 부착 극박 동박을이용한 배선판

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100389061B1 (ko) * 2002-11-14 2003-06-25 일진소재산업주식회사 전해 동박 제조용 전해액 및 이를 이용한 전해 동박 제조방법
JP3977790B2 (ja) * 2003-09-01 2007-09-19 古河サーキットフォイル株式会社 キャリア付き極薄銅箔の製造方法、及び該製造方法で製造された極薄銅箔、該極薄銅箔を使用したプリント配線板、多層プリント配線板、チップオンフィルム用配線基板
JP4570070B2 (ja) * 2004-03-16 2010-10-27 三井金属鉱業株式会社 絶縁層形成用の樹脂層を備えたキャリア箔付電解銅箔、銅張積層板、プリント配線板、多層銅張積層板の製造方法及びプリント配線板の製造方法
JP2007186797A (ja) * 2007-02-15 2007-07-26 Furukawa Circuit Foil Kk キャリア付き極薄銅箔の製造方法、及び該製造方法で製造された極薄銅箔、該極薄銅箔を使用したプリント配線板、多層プリント配線板、チップオンフィルム用配線基板
JPWO2008126522A1 (ja) * 2007-03-15 2010-07-22 日鉱金属株式会社 銅電解液及びそれを用いて得られた2層フレキシブル基板

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3081026B2 (ja) * 1991-07-18 2000-08-28 古河サーキットフォイル株式会社 プリント配線板用電解銅箔
JP2927968B2 (ja) * 1995-02-16 1999-07-28 三井金属鉱業株式会社 高密度多層プリント回路内層用銅箔および該銅箔を内層回路用に用いた高密度多層プリント回路基板
JP2000269637A (ja) * 1999-03-18 2000-09-29 Furukawa Circuit Foil Kk 高密度超微細配線板用銅箔
KR20050045903A (ko) * 2003-11-11 2005-05-17 후루카와서키트호일가부시끼가이샤 캐리어 부착 극박 동박, 및 캐리어 부착 극박 동박을이용한 배선판

Also Published As

Publication number Publication date
CN102577645A (zh) 2012-07-11
WO2011028004A2 (ko) 2011-03-10
KR101298999B1 (ko) 2013-08-23
JP2013503965A (ja) 2013-02-04
JP5464722B2 (ja) 2014-04-09
KR20110024055A (ko) 2011-03-09

Similar Documents

Publication Publication Date Title
WO2011028004A3 (ko) 미세회로 형성을 위한 임베디드용 동박
WO2008149969A1 (ja) 印刷物及びその製造方法並びに電磁波シールド材及びその製造方法
EP2458620A3 (en) Fabrication of graphene electronic devices using step surface contour
MY161680A (en) Copper foil for printed wiring board, method for producing said copper foil, resin substrate for printed wiring board and printed wiring board
WO2013019541A3 (en) Low-stress vias
PH12014502150A1 (en) Copper foil with carrier, method for manufacturing copper foil with carrier, copper foil with carrier for printed circuit board, and printed circuit board
WO2012140050A3 (de) Verfahren zur herstellung eines licht emittierenden halbleiterbauelements und licht emittierendes halbleiterbauelement
WO2010027231A3 (ko) 리드 프레임 및 그 제조방법
WO2010104274A3 (en) Lead frame and method for manufacturing the same
TW201130063A (en) Integrated circuit package system with through semiconductor vias and method of manufacture thereof
MX2011013713A (es) Cuerpo de multiples capas.
EP2423951A3 (en) Antiphase domain boundary-free III-V compound semiconductor material on semiconductor substrate and method for manufacturing thereof
TW200746276A (en) Method for bonding a semiconductor substrate to a metal substrate
WO2009057419A1 (ja) 回路形成方法
WO2009005042A1 (ja) 金属材料、その製造方法、及びそれを用いた電気電子部品
TW200833503A (en) Adhesive layer for resin and a method of producing a laminate including the adhesive layer
WO2009056235A3 (de) Mehrschichtsystem mit kontaktelementen und verfahren zum erstellen eines kontaktelements für ein mehrschichtsystem
MX2012010887A (es) Aleacion de cobre para material electronico y metodo de manufactura del mismo.
WO2010011009A9 (ko) 전자부품 모듈용 금속 기판과 이를 포함하는 전자부품 모듈 및 전자부품 모듈용 금속 기판 제조방법
MY159991A (en) Manufacturing method of printed wiring board and printed wiring board
WO2011070316A3 (en) Electronic device
WO2012087942A3 (en) Method of fabrication and resultant encapsulated electromechanical device
MY180430A (en) Copper foil with carrier, laminate, printed wiring board, and method of producing electronic devices
WO2011012893A3 (en) Security document
MY154122A (en) Electronic circuit, method for forming same, and copper clad laminate for forming electronic circuit

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 201080038730.0

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10813913

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2012526669

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 10813913

Country of ref document: EP

Kind code of ref document: A2