WO2011007389A1 - 移動体受信装置 - Google Patents
移動体受信装置 Download PDFInfo
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- WO2011007389A1 WO2011007389A1 PCT/JP2009/003333 JP2009003333W WO2011007389A1 WO 2011007389 A1 WO2011007389 A1 WO 2011007389A1 JP 2009003333 W JP2009003333 W JP 2009003333W WO 2011007389 A1 WO2011007389 A1 WO 2011007389A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/08—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
- H04B7/0837—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station using pre-detection combining
- H04B7/084—Equal gain combining, only phase adjustments
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- the present invention relates to a mobile reception device particularly suitable for use in a vehicle, in which a broadcast wave received via an antenna changes every moment due to the influence of multipath or the like.
- a radio intermediate frequency circuit is provided with a delay circuit that has a negligible delay for a desired signal but cannot be ignored for a noise component.
- a technique for improving the SN ratio and improving the sensitivity has been proposed.
- the present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a mobile receiver that realizes dynamic reception performance improvement at low cost.
- a mobile receiver includes a first tuner that converts a reception frequency signal received by an antenna into an intermediate frequency signal, and a delay circuit that uses a time required for movement of the reception frequency signal for a specific wavelength as a delay time. And a second tuner for converting the output of the delay circuit into a second intermediate frequency signal, and the delay time is moved to the delay circuit according to the moving speed of the moving body to be measured and the received electric field strength at that time. And a controller for synthesizing and outputting the intermediate frequency signals respectively generated by the first tuner and the second tuner by equal phase synthesis.
- the reception frequency signal that has passed through the delay circuit and the reception frequency signal that is not delayed are individually input to the first tuner and the second tuner, respectively, and the control unit converts the intermediate frequency signal that is converted by each of the first and second tuners.
- FIG. 1 is a block diagram showing an internal configuration of a mobile receiver 100A according to Embodiment 1 of the present invention.
- a radio receiver mounted on a vehicle is illustrated as a mobile.
- a mobile receiver 100A according to Embodiment 1 of the present invention includes a single antenna 1, two tuners A (2) and B (3), a delay circuit 4, It comprises a DSP (digital signal processing device 5A), an audio output unit 6, a CPU (central processing unit 7A), an operation unit 8, a display unit 9, and a speed detector 10.
- a thick solid arrow indicates a received signal
- a thin solid arrow indicates a control signal from the DSP 5A or the CPU 7A.
- the antenna 1 receives the broadcast reception wave and inputs the RF signal to the tuner A (2) and the delay circuit 4.
- the tuner A (2) converts the input RF signal into an IF signal and outputs it to the DSP 5A.
- the delay circuit 4 converts the RF signal delayed by a delay time set by a CPU 7A described later into an IF signal. To the DSP 5A.
- the DSP 5A includes two analog digital converters (hereinafter referred to as ADC-A (51) and ADC-B (52)), an equiphase synthesizer 53, and the like, as shown in FIG. , A detector 54, a signal strength detector 55, an audio processing unit 56, and a digital-analog converter (hereinafter referred to as DAC 57).
- ADC-A analog digital converter
- ADC-B ADC-B
- DAC 57 digital-analog converter
- the ADC-A (51) receives the IF signal input from the tuner A (2), converts it into a digital signal according to the sampling period under the control of the CPU 7A, and outputs it to the equal phase synthesizer 53.
- the ADC-B (52) obtains the IF signal input from the tuner B (3), converts it into a digital signal under the control of the CPU 7A, and outputs it to the equal phase synthesizer 53.
- the equal phase synthesizer 53 synthesizes the digital IF signals, which are the ADC-A (51) output and the ADC-B (52) output, in phase with each other under the control of the CPU 7A, and outputs the resultant signal to the detector 54.
- the effect as a diversity antenna becomes remarkable.
- the detector 54 detects the output of the equiphase synthesizer 53 and outputs the detected signal to the signal intensity detector 55 and the audio processing unit 56.
- the signal strength detector 55 detects a received signal strength indicator (RSSI) from the output of the detector 54 and outputs it to the CPU 7A.
- the audio processing unit 56 extracts an audio signal component from the IF signal and supplies the audio signal component to the audio output unit 6 configured by a speaker or the like via the DAC 57.
- the audio processing unit 56 also adjusts the volume, tone control, and the like in accordance with a user operation by the operation unit 8.
- the CPU 7A operates in cooperation with the DSP 5A to dynamically set the delay time in the delay circuit 4 according to the moving speed of the moving body measured by the speed detector 10 and the RSSI at that time. , And functions as a control unit for synthesizing and outputting IF signals respectively generated by the tuner A (2) and the tuner B (3). Details will be described later with reference to FIGS.
- the operation unit 8 is an input device that activates the CPU 7A and transmits user instructions such as channel selection to the CPU 7A by operation input
- the display unit 9 is a console that displays other information about the receiving station if it is a radio. If it is TV, it is comprised with the LCD (Liquid Crystal Display Device) display device which displays an image
- the speed detector 10 is composed of a vehicle speed sensor or the like connected externally, and the vehicle speed signal detected here is supplied to the CPU 7A.
- FIG. 2 is a block diagram showing functional expansion of the internal configuration of the control unit of mobile receiving apparatus 100A according to Embodiment 1 of the present invention.
- the CPU 7A includes a Doppler shift amount calculation unit 7A1, a delay time calculation unit 7A2, a tuner / audio processing control unit 7A3, an ADC input filter setting control unit 7A4, and a delay circuit control unit 7A5. And a phase synthesizer time constant controller 7A6.
- the Doppler shift amount calculation unit 7A1 acquires the RSSI from the signal strength detector 55 built in the DSP 5A, further acquires the inter-vehicle movement speed from the speed detector 10 connected externally, and the Doppler whose frequency changes with movement.
- the shift frequency, its sign, and the cycle are calculated by executing an arithmetic expression that will be described later, and the delay time calculation unit 7A2 and the ADC input filter setting control unit 7A4 are controlled.
- the delay time calculation unit 7A2 has a function of activating the delay circuit control unit 7A5 and the phase synthesis time constant control unit 7A6 by calculating the time required to move a quarter wavelength of the reception frequency.
- the delay circuit control unit 7A5 has a function of setting the time required for moving the 1 ⁇ 4 wavelength of the reception frequency calculated by the delay time calculation unit 7A2 in the delay circuit 4, and also has a phase synthesizer time constant.
- the controller 7A6 has a function of setting the delay time calculated by the delay time calculator 7A2 to the response time constant of the equal phase synthesizer 53 of the DSP 5A.
- the tuner / audio processing control unit 7A3 is activated by a user's operation input such as channel selection by the operation unit 8, and has a function of controlling the tuner A (2), tuner B (3), and the audio processing unit 56 in the DSP 5A. Have.
- the ADC input filter setting control unit 7A4 has a function of shifting the center frequency of the input filter according to the code by the Doppler shift frequency calculated by the Doppler shift amount calculation unit 7A1.
- FIG. 3 is a flowchart showing the operation of the mobile receiver according to Embodiment 1 of the present invention.
- the operation of mobile receiving apparatus 100A according to Embodiment 1 of the present invention shown in FIGS. 1 and 2 will be described in detail below with reference to the flowchart of FIG.
- the CPU 7A follows the control cycle (step ST301 “YES”) to detect the speed.
- the moving speed is read from the device 10 and the RSSI is read from the signal strength detector 55 built in the DSP 5A (step ST302).
- the CPU 7A Doppler shift amount calculation unit 7A1 determines these time changes, and the transmission antenna of the base station including a broadcast station (not shown) depending on whether the RSSI increases or decreases with time. Whether the vehicle is approaching or moving away from the vehicle is determined.
- the following equation (1) is executed to calculate the Doppler shift amount ⁇ f1 of the reception frequency fo and its period T1 (step ST303).
- the angle ⁇ 180 ° (step 302).
- the CPU 7A (ADC input filter setting control unit 7A4) corrects the Doppler shift shift, and the center frequency of the input filter of each of the ADC-A (51) and ADC-B (52) built in the DSP 5A. Are shifted by the Doppler shift amount ⁇ f1 in consideration of the ⁇ sign (step ST304).
- the CPU 7A (delay time calculation unit 7A2) requires a time required to move from the 1/8 wavelength of the reception frequency to the 1/4 wavelength in consideration of the Doppler shift amount ⁇ f1 output by the Doppler shift amount calculation unit 7A1. T2 is calculated (step ST305).
- the delay circuit controller 7A5 sets the delay time T2 output from the delay time calculator 7A2 in the delay circuit 4 (step ST306). Further, the phase synthesizer time constant control unit 7A6 performs control for setting the time constant indicating the response characteristic of the phase synthesis of the equal phase synthesizer 53 built in the DSP 5A in accordance with the delay time T2 (step ST307). After the delay time and time constant are set, the process returns to step ST301, and the series of operations described above is repeatedly executed by the CPU 7A for each control cycle. This control cycle may be matched with the sampling cycle of ADC-A (51) and ADC-B (52).
- the control unit (CPU 7A) sets the delay time corresponding to the reception frequency and the Doppler shift frequency in the delay circuit 4, and the control unit (DSP 5A)
- the control unit (CPU 7A) calculates the Doppler shift cycle and adapts it to the response speed of the equal phase synthesis, so that it is possible to extract a sound that does not feel uncomfortable in terms of audibility after detection.
- FIG. FIG. 4 is a block diagram showing an internal configuration of mobile receiving apparatus 100B according to Embodiment 2 of the present invention.
- the difference in configuration from the first embodiment shown in FIG. 1 is that the delay circuit 40 is built in the DSP 5B (the delay circuit 4 is out in the first embodiment), and the ADC-A (51) A multiplier 41 that multiplies the IF signal output between the equal phase synthesizer 53, a multiplier 42 that multiplies the IF signal output between the ADC-B (52) and the delay circuit 40, an equal phase synthesizer 53, This is because frequency dividers 43 are inserted between the detectors 35.
- the DSP 5B operates in cooperation with the CPU 7B to multiply the IF signal of the tuner A (2) by the multiplier 41 and the IF signal of the tuner B (3) by the multiplier 42.
- the equal phase synthesizer 53 uses the equal phase synthesizer 53 to synthesize the signal delayed by the delay circuit 40 having a delay time obtained by dividing the time taken to move the reception frequency by a specific wavelength by the multiplication ratio that can secure the modulation band. Control to output.
- the CPU 7B has a frequency divider / multiplier control unit 7B7 added to the configuration of the first embodiment shown in FIG. 2, as shown in FIG. It has been configured. Details of the frequency divider / multiplier control unit 7B7 will be described later.
- FIG. 6 is a flowchart showing the operation of the mobile receiver 100B according to Embodiment 2 of the present invention.
- the operation of mobile receiving apparatus 100B according to the second embodiment of the present invention shown in FIGS. 4 and 5 will be described in detail with reference to the flowchart of FIG.
- the CPU 7B follows the control cycle (step ST601 “YES”) and detects the speed.
- the moving speed is read from the device 10 and the RSSI is read from the signal strength detector 55 built in the DSP 5B (step ST602).
- the CPU 7B Doppler shift amount calculation unit 7B1 determines these time changes, and the RSSI increases or decreases with the passage of time, so that the transmission antenna of the base station including the broadcast station (not shown). Whether the vehicle is approaching or moving away is determined.
- the Doppler shift amount ⁇ f1 of the reception frequency fo and its period T1 are calculated by the above-described arithmetic expression (1) (step ST603).
- the CPU 7B (ADC input filter setting control unit 7B4) corrects the Doppler shift shift, and the center frequency of the input filter of each of the ADC-A (51) and ADC-B (52) built in the DSP 5 is corrected. Are shifted by ⁇ f1 in consideration of the ⁇ sign (step ST604).
- the CPU 7B (frequency divider / multiplier control unit 7B7) sets the optimum multiplication ratio n1 that can ensure a sufficient modulation band in the multiplier 41, the multiplier 42, and the frequency divider 43 incorporated in the DSP 5B, respectively (step). ST605).
- the delay time calculation unit 7B2 calculates a time T3 required to move the 1 / (4n1) wavelength from the 1 / (8n1) wavelength of the reception frequency in consideration of the Doppler shift amount ⁇ f1 (step ST606).
- the time T3 is set in the delay circuit 40 by the delay circuit control unit 7B5 (step ST607).
- the phase synthesizer time constant control unit 7B6 performs control to set the time constant indicating the response characteristic of the phase synthesis of the equal phase synthesizer 53 built in the DSP 5 in accordance with the delay time T3 (step ST608).
- the output of the equal phase synthesizer 53 is frequency-divided by the frequency divider 43 to the original IF frequency of 1 / (n1) and detected.
- step ST601 After the delay time and time constant are set, the process returns to step ST601, and the series of operations described above is repeatedly executed by the CPU 7B for each control cycle.
- the control unit (CPU 7B) sets the delay time corresponding to the reception frequency and the Doppler shift frequency to the delay circuit incorporated in the DSP 5B.
- Set to 40 and the control unit (DSP 5B) performs equal phase synthesis of signals having a phase difference of about 1 ⁇ 4 wavelength (90 °), so that reception under a multipath is possible for moving radio or television broadcast reception. Performance can be improved. Further, by calculating the period of Doppler shift and adapting it to the response speed of equal phase synthesis, it is possible to extract a sound that does not feel uncomfortable in terms of audibility after detection.
- the delay circuit 40 when the delay circuit 40 is incorporated in the DSP 5B and the multiplier 41 and the multiplier 42 are multiplied by n1, the phase rotation of the IF signal output for the same delay time becomes n1 times.
- the delay corresponds to a delay time of T3 ⁇ n1 in the antenna stage.
- T2 n1 ⁇ T3 in the second embodiment. Therefore, the delay time T3 is 1 / n1 times the delay time T2, and the burden on the delay device is reduced.
- the phase difference of the RF stage is the same as the phase difference of the IF stage, and the phase difference is multiplied by n1.
- n1 is set large, no matter how low the speed of the moving body is theoretically, it is multiplied by n1 and Two IF signals having a phase difference of 90 ° can be input to the equal phase synthesizer 53 to provide a diversity effect.
- the DSP 5A (5B) and the CPU 7A (7B) operate in cooperation, so that “the moving speed of the moving body to be measured and the received electric field strength at that time”
- this function may be determined separately, for example, by the DSP 5A (5B) sharing the load including the Doppler shift amount calculation and the delay time calculation, or all functions. Can be realized by the DSP 5A (5B) alone or the CPU 7A (7B) alone.
- the delay time is dynamically set in the delay circuit in accordance with the moving speed of the moving body to be measured and the received electric field strength at that time, and the intermediate time generated by the first tuner and the second tuner, respectively.
- Data processing for synthesizing and outputting frequency signals with equal phase may be realized on a computer by one or a plurality of programs, or at least a part thereof may be realized by hardware.
- the mobile reception device 100A (100B) according to the present invention is not delayed with the reception frequency signal via the delay circuit 4 (40) in order to realize dynamic reception performance improvement at low cost.
- the reception frequency signal is individually input to the first tuner 2 and the second tuner 3 respectively, and the control units (DSP 5A (5B) and CPU 7A (7B)) synthesize the intermediate frequency signals converted respectively by equal phase. Because of this configuration, it is possible to optimize the output of the intermediate frequency signal synthesized when the broadcast wave input to the antenna 1 changes from moment to moment, and of course not only radio and television mounted in the vehicle, but also at high speed.
- the present invention can also be applied to a mobile communication device mounted on a moving airplane or the like.
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Abstract
Description
また、アンテナを一定距離だけ離してレイアウトし、その出力で等位相合成を図る、所謂、ダイバーシティー技術も存在するが、アンテナシステムが2組必要になり、このため高いコストを要する。
実施の形態1.
図1は、この発明の実施の形態1による移動体受信装置100Aの内部構成を示すブロック図であり、ここでは、移動体として車両に搭載されたラジオ受信機が例示されている。
図1に示されるように、この発明の実施の形態1に係る移動体受信装置100Aは、唯一のアンテナ1と、2系統のチューナA(2)、B(3)と、遅延回路4と、DSP(デジタル信号処理装置5A)と、オーディオ出力部6と、CPU(中央処理装置7A)と、操作部8と、表示部9と、速度検出器10と、により構成される。
なお、図1において、太実線矢印は受信信号を、細実線矢印は、DSP5AまたはCPU7Aによる制御信号を示す。
信号強度検出器55は、検波器54出力から受信電界強度(RSSI:Received Signal Strength Indicator)を検出してCPU7Aへ出力する。オーディオ処理部56は、IF信号からオーディオ信号成分を抽出してDAC57経由で、スピーカ等により構成されたオーディオ出力部6へ供給する。オーディオ処理部56は、操作部8によるユーザ操作にしたがい、音量、トーンコントロール等の調整も行う。
なお、速度検出器10は、外部接続される車速センサ等で構成され、ここで検出された車速信号はCPU7Aに供給される。
図2に示されるように、CPU7Aは、ドップラーシフト量演算部7A1と、遅延時間演算部7A2と、チューナ・オーディオ処理制御部7A3と、ADC入力フィルタ設定制御部7A4と、遅延回路制御部7A5と、位相合成器時定数制御部7A6と、を含む。
遅延時間演算部7A2は、受信周波数の1/4波長を移動するのに必要な時間を計算して遅延回路制御部7A5、および位相合成時定数制御部7A6を起動する機能を有する。遅延回路制御部7A5は、遅延時間演算部7A2で計算された受信周波数の1/4波長を移動するのに必要な時間を遅延回路4に設定する機能を有し、また、位相合成器時定数制御部7A6は、遅延時間演算部7A2で計算された遅延時間をDSP5Aの等位相合成器53の応答時定数に設定する機能を有する。
ADC入力フィルタ設定制御部7A4は、入力フィルタの中心周波数を、ドップラーシフト量演算部7A1で計算されたドップラーシフト周波数分だけ前記符号にしたがいシフトする機能を有する。
以下、図3のフローチャートを参照しながら、図1、図2に示すこの発明の実施の形態1による移動体受信装置100Aの動作を詳細に説明する。
続いてCPU7A(ドップラーシフト量演算部7A1)は、これらの時間変化を判定し、RSSIが時間経過とともに増加しているか、または減少しているかにより、不図示の放送局を含む基地局の送信アンテナに対し車両が接近しているか遠ざかっているか、その進行方向を判定する。同時に、以下に示す演算式(1)を実行することにより、受信周波数foのドップラーシフト量Δf1と、その周期T1とを算出する(ステップST303)。
このとき、CPU7A(遅延時間演算部7A2)は、ドップラーシフト量演算部7A1により出力されるドップラーシフト量Δf1を加味した受信周波数の1/8波長から1/4波長を移動するのに必要な時間T2を計算する(ステップST305)。
上記した遅延時間および時定数設定後、ステップST301の処理に戻り、上記した一連の動作はCPU7Aにより制御周期毎に繰り返し実行される。なお、この制御周期は、ADC-A(51)、ADC-B(52)のサンプリング周期に合わせてもよい。
また、制御部(CPU7A)が、ドップラーシフトの周期を算出し、等位相合成の応答速度に適応させることにより、検波後の聴感上、違和感のない音声を抽出することができる。
図4は、この発明の実施の形態2に係る移動体受信装置100Bの内部構成を示すブロック図である。
図1に示す実施の形態1との構成上の差異は、遅延回路40をDSP5Bが内蔵し(実施の形態1では遅延回路4を外出ししてある)、かつ、ADC-A(51)と等位相合成器53の間にIF信号出力を逓倍する逓倍器41と、ADC-B(52)と遅延回路40との間にIF信号出力を逓倍する逓倍器42と、等位相合成器53と検波器35との間に分周器43を、それぞれ挿入したことにある。
以下、図6のフローチャートを参照しながら、図4、図5に示すこの発明の実施の形態2による移動体受信装置100Bの動作を詳細に説明する。
続いてCPU7B(ドップラーシフト量演算部7B1)は、これらの時間変化を判定し、RSSIが時間経過とともに増加しているか、または減少しているにより、不図示の放送局を含む基地局の送信アンテナに対して接近しているか遠ざかっているか、進行方向を判定する。同時に、上記した演算式(1)により受信周波数foのドップラーシフト量Δf1、ならびにその周期T1を算出する(ステップST603)。
このとき、CPU7B(分周器・逓倍器制御部7B7)は、変調帯域が充分確保できる最適逓倍比n1をDSP5Bが内蔵する逓倍器41、逓倍器42、分周器43にそれぞれ設定する(ステップST605)。ここで、遅延時間演算部7B2は、ドップラーシフト量Δf1を加味した受信周波数の1/(8n1)波長から1/(4n1)波長を移動するのに必要な時間T3を計算し、(ステップST606)、この時間T3を、遅延回路制御部7B5により遅延回路40に設定する(ステップST607)。また、位相合成器時定数制御部7B6は、DSP5が内蔵する等位相合成器53の、位相合成の応答特性を示す時定数も遅延時間T3に合わせて設定する制御を行う(ステップST608)。等位相合成器53の出力は、分周器43にて1/(n1)の元のIF周波数に分周され、検波される。
また、DSP5Bに遅延回路40を内蔵し、かつ、逓倍器41、逓倍器42をn1逓倍した場合、同一遅延時間に対するIF信号出力の位相回転がn1倍になるため、遅延回路40でT3時間の遅延を行うと、その遅延はアンテナ段でのT3×n1の遅延時間に相当する。ここで、受信周波数の1/8~1/4波長の距離を移動するのに必要な時間を実施の形態1のT2とすれば、本実施の形態2では、T2=n1・T3で示されるため、遅延時間T3は、遅延時間T2の1/n1倍になり、遅延器の負担が少なくなる。RF段の位相差はIF段での位相差と同じであり、その位相差がn1倍されるため、n1を大きく取れば理論上はどんなに移動体の速度が遅くても、n1倍されてかつ位相差が90°の2つのIF信号を等位相合成器53に入力し、ダイバーシティー効果を持たせることができる。
また、上記した実施の形態1、実施の形態2では、DSP5A(5B)とCPU7A(7B)が協働して動作することにより、「測定される移動体の移動速度とそのときの受信電界強度とに応じて遅延回路に前記遅延時間を動的に設定すると共に、第1のチューナと第2のチューナによりそれぞれ生成される中間周波数信号を等位相合成して出力する制御部」、としての機能を実現するものとして説明したが、この機能は、例えば、ドップラーシフト量演算、遅延時間演算も含めてDSP5A(5B)が負荷を分担する等、機能分担を別に定めても、あるいは、全ての機能をDSP5A(5B)単体で、あるいはCPU7A(7B)単体で実現することも可能である。
例えば、測定される移動体の移動速度とそのときの受信電界強度とに応じて遅延回路に前記遅延時間を動的に設定すると共に、第1のチューナと第2のチューナによりそれぞれ生成される中間周波数信号を等位相合成して出力するデータ処理は、1または複数のプログラムによりコンピュータ上で実現してもよく、また、その少なくとも一部をハードウェアで実現してもよい。
Claims (4)
- 移動体に搭載される移動体受信装置において、
アンテナで受信した受信周波数信号を中間周波数信号に変換する第1のチューナと、
前記移動体が前記受信周波数信号の特定波長分の移動にかかる時間分だけ前記受信周波数信号を遅延させる遅延回路と、
前記遅延回路出力を第2の中間周波数信号に変換する第2のチューナと、
測定される前記移動体の移動速度とそのときの受信電界強度とに応じて前記遅延回路に前記遅延時間を動的に設定すると共に、前記第1のチューナと前記第2のチューナによりそれぞれ生成される中間周波数信号を等位相合成して出力する制御部と、
を備えたことを特徴とする移動体受信装置。 - 前記制御部は、
前記移動速度を読み出してそのときの受信電界強度から移動体の進行方向を決定し、
前記移動体の移動に伴い周波数が変化するドップラーシフト周波数、その符号、および周期を計算し、
前記第1のチューナ出力と前記第2のチューナ出力をデジタル信号に変換するそれぞれのアナログデシタルコンバータを構成する入力フィルタの中心周波数を、前記計算されたドップラーシフト周波数分だけ前記符号にしたがいシフトし、
前記移動体が前記受信周波数の1/4波長を移動するのに必要な時間を計算して前記遅延回路に設定し、かつ、等位相合成の際の時定数も同値に設定すること、
を特徴とする請求項1記載の移動体受信装置。 - 前記制御部は、
前記第1のチューナの中間周波数信号を逓倍した出力と、前記第2のチューナの中間周波数信号を逓倍した出力を、前記移動体が前記受信周波数の特定波長分の移動にかかる時間を変調帯域が確保可能な逓倍比で割った時間を遅延時間とする前記遅延回路で遅延した信号と等位相合成して出力することを特徴とする請求項1記載の移動体受信装置。 - 前記制御部は、
前記移動速度を読み出してそのときの受信電界強度から移動体の進行方向を決定し、
前記移動体の移動に伴い周波数が変化するドップラーシフト周波数、その符号、および周期を計算し、
前記第1のチューナ出力と前記第2のチューナ出力をデジタル信号に変換するそれぞれのアナログデシタルコンバータを構成する入力フィルタの中心周波数を、前記計算されたドップラーシフト周波数分だけ前記符号にしたがいシフトし、
前記逓倍比を設定して前記移動体が前記受信周波数の1/4波長を移動するのに必要な時間を計算して前記遅延回路に設定し、かつ、等位相合成の際の時定数も同値に設定すること、
を特徴とする請求項3記載の移動体受信装置。
Priority Applications (5)
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JP2011522625A JP5143284B2 (ja) | 2009-07-15 | 2009-07-15 | 移動体受信装置 |
PCT/JP2009/003333 WO2011007389A1 (ja) | 2009-07-15 | 2009-07-15 | 移動体受信装置 |
US13/264,071 US8385837B2 (en) | 2009-07-15 | 2009-07-15 | Mobile receiver apparatus |
DE112009005070.0T DE112009005070B4 (de) | 2009-07-15 | 2009-07-15 | Mobil -Empfänger-Gerät |
CN200980160538.6A CN102474309B (zh) | 2009-07-15 | 2009-07-15 | 移动体接收装置 |
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JP (1) | JP5143284B2 (ja) |
CN (1) | CN102474309B (ja) |
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TWI730667B (zh) * | 2020-03-12 | 2021-06-11 | 瑞昱半導體股份有限公司 | 具有抗射頻干擾機制的訊號接收裝置及方法 |
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JP2001028561A (ja) * | 1998-09-17 | 2001-01-30 | Matsushita Electric Ind Co Ltd | デジタルテレビジョン放送受信装置および送受信システム |
JP2002530005A (ja) * | 1998-11-09 | 2002-09-10 | クゥアルコム・インコーポレイテッド | 通信システムにおける交差偏波分離方法及び装置 |
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JPH07336628A (ja) | 1994-06-09 | 1995-12-22 | Casio Comput Co Ltd | テレビ受信装置 |
EP1804494A3 (en) * | 1998-09-17 | 2008-04-30 | Matsushita Electric Industrial Co., Ltd. | Digital TV broadcast receiving apparatus, and transmitting and receiving system |
JP2002299960A (ja) | 2001-04-02 | 2002-10-11 | Nippon Telegr & Teleph Corp <Ntt> | Fm検波器およびfm受信機 |
US7426450B2 (en) * | 2003-01-10 | 2008-09-16 | Wavetronix, Llc | Systems and methods for monitoring speed |
JP4546177B2 (ja) * | 2003-07-28 | 2010-09-15 | パナソニック株式会社 | 無線通信装置および無線通信方法 |
JP4405375B2 (ja) * | 2004-12-07 | 2010-01-27 | 三菱電機株式会社 | ディジタル放送受信装置 |
US7697913B2 (en) * | 2005-12-19 | 2010-04-13 | Delphi Technologies, Inc. | Dual tuner diversity for background processing and to reduce multipath distortion |
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- 2009-07-15 WO PCT/JP2009/003333 patent/WO2011007389A1/ja active Application Filing
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JP2001028561A (ja) * | 1998-09-17 | 2001-01-30 | Matsushita Electric Ind Co Ltd | デジタルテレビジョン放送受信装置および送受信システム |
JP2002530005A (ja) * | 1998-11-09 | 2002-09-10 | クゥアルコム・インコーポレイテッド | 通信システムにおける交差偏波分離方法及び装置 |
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JP5143284B2 (ja) | 2013-02-13 |
JPWO2011007389A1 (ja) | 2012-12-20 |
DE112009005070T5 (de) | 2012-07-05 |
CN102474309A (zh) | 2012-05-23 |
DE112009005070B4 (de) | 2014-05-28 |
US20120028593A1 (en) | 2012-02-02 |
US8385837B2 (en) | 2013-02-26 |
CN102474309B (zh) | 2014-07-30 |
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