WO2011003366A1 - 一种形成带有绝缘埋层的衬底的方法 - Google Patents

一种形成带有绝缘埋层的衬底的方法 Download PDF

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Publication number
WO2011003366A1
WO2011003366A1 PCT/CN2010/075098 CN2010075098W WO2011003366A1 WO 2011003366 A1 WO2011003366 A1 WO 2011003366A1 CN 2010075098 W CN2010075098 W CN 2010075098W WO 2011003366 A1 WO2011003366 A1 WO 2011003366A1
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WIPO (PCT)
Prior art keywords
substrate
layer
etching
edge
insulating buried
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PCT/CN2010/075098
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English (en)
French (fr)
Inventor
王湘
魏星
张苗
林成鲁
王曦
Original Assignee
上海新傲科技股份有限公司
中国科学院上海微系统与信息技术研究所
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Priority claimed from CN 200910054626 external-priority patent/CN101599451B/zh
Priority claimed from CN2009100546274A external-priority patent/CN101599452B/zh
Priority claimed from CN 200910199624 external-priority patent/CN101707188B/zh
Application filed by 上海新傲科技股份有限公司, 中国科学院上海微系统与信息技术研究所 filed Critical 上海新傲科技股份有限公司
Priority to EP10796743.2A priority Critical patent/EP2461359B1/en
Priority to US13/383,416 priority patent/US8633090B2/en
Publication of WO2011003366A1 publication Critical patent/WO2011003366A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN

Definitions

  • This invention relates to the field of semiconductor materials, and more particularly to a method of forming a substrate with an insulating buried layer having edge chamfers.
  • the basic structure of a silicon-on-insulator includes an upper layer of top silicon, an intermediate buried layer of silicon dioxide, and a bottom supporting substrate.
  • the bonding SOI is produced by forming two layers of the above-mentioned three-layer structure by high-temperature reinforcement by direct bonding.
  • the top layer of silicon (or device layer) is thinned to a certain thickness by a series of methods, but after thinning, due to the change of the edge shape of the original silicon wafer, certain edge treatment must be performed, and the top layer is polished by edge grinding or polishing. The edge of the silicon is removed, otherwise defects such as chipping may occur in the subsequent process.
  • the first is to chamfer the SOI substrate, immerse the SOI wafer in tetramethylammonium hydroxide (TMAH) to etch away excess silicon at the edges, and then immerse the SOI wafer in hydrofluoric acid, due to hydrofluoric acid.
  • TMAH tetramethylammonium hydroxide
  • the silicon is not corroded, so the HF solution erodes the residual silicon dioxide at the edges.
  • the above process In order to eliminate the silicon dioxide residue at the edge of the silicon wafer, the above process must be immersed in hydrofluoric acid, but this will destroy the thermally oxidized silicon dioxide coating on the surface of the supporting substrate of the SOI substrate, thereby destroying the equilibrium warpage of the silicon wafer. degree. In addition, many undesirable defects are introduced on the silicon surface after immersion in TMAH.
  • the other is to remove the edge residual silica directly from the SOI substrate with thin top silicon after grinding the top layer silicon without using chamfer grinding, but directly using a chemical mechanical polishing oxide polishing solution.
  • the technical problem to be solved by the present invention is to provide a method for forming a substrate with an insulating buried layer having edge chamfering, which can complete the processing of the edge of the substrate without etching the original covering layer on the back side. And it is possible to avoid excess buried buried layer on the edge, thereby ensuring that the warpage of the substrate is not affected.
  • the present invention provides a method of forming a substrate with an insulating buried layer having edge chamfering, comprising the steps of: providing a first substrate for forming an insulating layer a top layer semiconductor layer of the buried substrate; forming a corrosion barrier layer on the surface of the first substrate; chamfering the first substrate and the corrosion barrier layer on the surface thereof by edge grinding; etching by edge etching by edge etching a first substrate exposed by etching the barrier layer; a second substrate for forming a support layer with an insulating buried substrate; bonding the first substrate through an insulating buried layer To the second substrate, wherein the edge-polished surface of the first substrate faces the second substrate.
  • the present invention also provides a method of forming a substrate with an insulating buried layer having edge chamfering, comprising the steps of: providing a first substrate; sequentially forming an etching barrier layer and a top semiconductor layer on the surface of the first substrate; Laminating the top semiconductor layer of the first substrate on the rotating etching carrier platform, passing the etching solution for etching the top semiconductor layer to the back surface of the first substrate and simultaneously rotating the substrate to pass the etching liquid through the first substrate
  • the edge flows to the edge of the top semiconductor layer to etch the edge portion of the top semiconductor layer; a second substrate is provided, the second substrate is used to form a support layer with an insulating buried substrate; Bonding to the second substrate through an insulating buried layer, wherein the edge-etched top semiconductor layer of the first substrate faces the second substrate; the first substrate and the etch stop layer are removed.
  • the present invention also provides a method of forming a substrate with an insulating buried layer having edge chamfering, comprising the steps of: providing a semiconductor substrate with an insulating buried layer, the semiconductor substrate comprising a support layer, an insulating buried a layer and a top semiconductor layer; a cover layer is formed on both the upper surface and the lower surface of the semiconductor substrate, the upper surface is a surface of the top semiconductor layer, and the lower surface is the other surface opposite to the upper surface; The edges of the insulating buried layer and the top semiconductor layer are chamfered; the upper surface of the substrate is placed on the rotating corrosion carrier platform upward, and the etching solution of the covering layer and the etching solution of the insulating buried layer are sequentially connected to the upper surface of the substrate.
  • the cover layer is simultaneously rotated to remove the cover layer of the surface and the insulating buried layer which is exposed by the cover layer being removed by grinding, while leaving the cover layer on the back side.
  • the present invention also provides a method of forming a substrate with an insulating buried layer having edge chamfering, comprising the steps of: providing a substrate with an insulating buried layer, the substrate with an insulating buried layer comprising a support a layer, an insulating buried layer and a top semiconductor layer; a cover layer is formed on both the front side and the back side of the substrate, the front side is a surface of the top semiconductor layer, and the back side is the other side opposite to the front side; Grinding and removing; placing the front side of the substrate down on the rotating etching slide platform, passing the etching liquid of the top semiconductor layer to the covering layer on the back surface of the substrate and rotating the substrate at the same time, so that the etching liquid flows through the edge of the substrate To the front side, etch the edge portion of the front top semiconductor layer; place the front side of the substrate on the rotating corrosion carrier platform, pass the insulating buried etching solution to the front side of the substrate and simultaneously rotate the substrate, and etch away the
  • the invention has the advantages that the edge etching of the top semiconductor layer is removed by performing a spin etching process before or after bonding, thereby avoiding the phenomenon of chipping in the subsequent device process; and flexibly selecting the rotation according to the surface condition of the substrate
  • the way of the etching process is to effectively perform edge corrosion on the target layer without excessively damaging the parts that need to be retained.
  • FIG. 1 is a schematic view showing the steps of the first embodiment of the present invention
  • FIGS. 2 to 8 are schematic views showing the process of the first embodiment of the present invention.
  • Figure 9 is a schematic view showing the steps of the second embodiment of the present invention.
  • FIG. 10 to FIG. 14 are schematic views showing the process of the second embodiment of the present invention.
  • FIG. 15 is a schematic view showing the steps of the third embodiment of the present invention.
  • FIG. 16 is a schematic view showing the process of the third embodiment of the present invention.
  • FIG. 22 is a schematic view showing the steps of the fourth embodiment of the present invention.
  • 23 to 28 are schematic views showing the process of the fourth embodiment of the present invention.
  • Step S10 providing a first substrate
  • Step S11 forming a corrosion barrier layer on the surface of the first substrate, wherein the corrosion barrier layer is formed on the first Step S12, using a edge grinding method to chamfer a smooth surface of the first substrate and a corrosion barrier layer on the surface thereof
  • Step S13 using a method of rotational corrosion to block the corrosion due to edge grinding And exposing the first substrate
  • step S14 providing a second substrate
  • step S15 bonding the first substrate to the second substrate through an insulating buried layer.
  • a first substrate 110 is provided.
  • the first substrate 110 in the present embodiment is a single crystal silicon substrate.
  • the first substrate 110 is used to form a top semiconductor layer with an insulating buried substrate. Therefore, in other embodiments, the material of the first substrate 110 needs to be selected according to the requirements of the target product, and may be, for example, any one of silicon carbide, germanium silicon, strained silicon, and various compound semiconductors.
  • an etching stopper layer 111 is formed on the surface of the first substrate 110, and the etching stopper layer 111 is formed on all surfaces of the first substrate 110.
  • the material of the etching stopper layer 111 is silicon oxide, and it can be formed by thermal oxidation.
  • etching stopper layer 111 on both the front and back surfaces of the first substrate 110 in that the back surface of the first substrate 110 can be protected from corrosion by the etching liquid in the subsequent step. Corrosion of the back side of the first substrate 110 affects the overall warpage characteristics of the substrate, causing uncertainty in the bonding process.
  • the material of the suitable corrosion barrier layer 111 should be selected based on the material of the first substrate 110 and the nature of the etching solution employed in the subsequent selective etching process. How to select the material of the corrosion barrier in the selective etching process is a common knowledge in the art, and will not be enumerated here.
  • a smooth surface of the first substrate 110 and a corrosion blocking layer 111 on the surface thereof are chamfered by edge grinding.
  • edge chamfer grinding of a wafer is a common process and will not be described here.
  • the chamfering process of this step enables the etching barrier layer 111 and the edge of the first substrate 110 to be ground into a bevel by calculating the angle and speed of the polishing, thereby exposing the edge portion of the first substrate 110 to ensure the subsequent etching process.
  • the first substrate 110 exposed by the edge-grinding etching barrier layer is etched by a method of spin etching.
  • the chamfered surface of the first substrate 110 is placed up on the rotating corrosion carrier platform 190 to pass the etching solution to the upward surface while rotating the first substrate 110.
  • the etching liquid can withstand corrosion for a long time, so that the chamfered surface of the first substrate 110 can be placed on the rotating corrosion carrier platform upward.
  • the etching solution is directly passed to the upward surface, that is, the surface of the etching stopper 111, and the substrate is rotated at the same time.
  • the rotation rate of the slide stage 190 In order to ensure the quality of the selective corrosion, it is necessary to optimize the rotation rate of the rotary corrosion. If the edge of the first semiconductor layer 110 is to be etched more efficiently in this step, it is necessary to control the etching liquid not to flow to the other side of the first substrate 110 as much as possible. Therefore, it is preferable to control the rotation rate of the slide stage 190 within a large range in the case of spin corrosion. Experiments have shown that the preferred rate of rotation in this step is greater than 500 cycles per minute, especially at greater than 1500 cycles per minute.
  • the first substrate 110 in this embodiment is a single crystal silicon substrate, which is corroded.
  • the material of the barrier layer 111 is silicon oxide, so tetramethylammonium hydroxide can be used as the etching solution for the spin corrosion in this step.
  • corrosive solutions such as potassium hydroxide or catechol-ethylenediamine-water, which are common in the art, can also be used in this step.
  • the concentration of the etching solution and the etching time are also process parameters that need to be optimized so that the corrosion rate is controllable and the corrosion time is controlled within a reasonable range. If the flow rate of the corrosive liquid is too large or the concentration of the corrosive liquid is too high, the corrosion rate becomes fast and difficult to control; on the contrary, if the flow rate is too small or the concentration of the corrosive liquid is too low, the corrosion time becomes long, which is not conducive to improving the process efficiency. . Therefore, it is necessary to control the concentration and flow rate of the corrosive liquid within a suitable range to obtain a balance of corrosion controllability and speed. Experiments have shown that the mass concentration of the corrosive solution ranges from 5% to 49%, and the flow rate of the corrosive solution is from 500 to 2500 ml per minute is a preferred process parameter.
  • a second substrate 120 is provided.
  • the second substrate 120 is used to form a support layer with an insulating buried substrate.
  • the material selection of the second substrate 120 is relatively broad. Since the second substrate 120 is used as a supporting layer, in addition to a common substrate such as a single crystal silicon substrate and a sapphire substrate, silicon carbide, diamond, glass, or even a metal substrate are available.
  • the first substrate 110 is bonded to the second substrate 120 through an insulating buried layer.
  • the edge-polished surface of the first substrate 110 faces the second substrate 120.
  • the insulating buried layer is the etching stopper 111 serving as a corrosion barrier in the foregoing step.
  • the corrosion barrier layer 111 is uninsulated, or the corrosion barrier layer is damaged during the etching process, or is otherwise unsuitable for use as an insulating buried layer of the final product due to various other reasons, It is also possible to remove the etching barrier layer 111 and separately grow a new insulating buried layer.
  • the new insulating buried layer may be grown on the surface of the first substrate 110 or on the surface of the second substrate 120, and of course may be simultaneously grown on the surfaces of the two substrates.
  • the bonding process is a common process in the art, and the specific implementation process will not be described in detail.
  • the first substrate 110 may be further thinned to a target thickness as needed.
  • the thinning may be performed by various common processes including etching, grinding, and peeling, and will not be described herein.
  • Figure 8 shows a thinned substrate having an insulating buried layer 111 including a second substrate 120 serving as a supporting substrate and a first substrate 110 serving as a top semiconductor layer after thinning. Due to the first substrate 110 The surface for bonding is subjected to a chamfering process, so that the edge of the top semiconductor layer of the substrate after bonding thinning has been removed before bonding, and no further processing is required.
  • the embodiment first performs edge etching treatment on the top semiconductor layer, and then performs bonding, thereby avoiding damage to the substrate during the process of processing the edge of the bonded substrate;
  • the spin etching process etches the first substrate on which the top semiconductor layer is to be formed, the etching rate is easy to control, and the uniformity and concentricity are superior to the conventional etching process, and is particularly suitable for etching the edge of the wafer.
  • Step S20 providing a first substrate
  • Step S21 sequentially forming an etching barrier layer and a top semiconductor layer on the surface of the first substrate
  • Step S22 Laying the top semiconductor layer of the first substrate down on the rotating etching slide platform, passing the etching liquid etching the top semiconductor layer to the back surface of the first substrate and rotating the substrate simultaneously, so that the etching liquid flows through the first substrate
  • the edge flows to the edge of the top semiconductor layer to etch the edge portion of the top semiconductor layer
  • step S23 providing a second substrate for forming a support layer with an insulating buried substrate
  • step S24 And bonding the first substrate to the second substrate through an insulating buried layer, wherein the edge-etched top semiconductor layer of the first substrate faces the second substrate
  • Step S25 removing the first substrate and the etching barrier layer .
  • the material of the top semiconductor layer is silicon, and the etching liquid for the top semiconductor layer used is tetramethylammonium hydroxide; the material of the insulating buried layer is silicon oxide.
  • the top semiconductor layer may also be germanium, germanium silicon, and any other common semiconductor material; the insulating buried layer may be other insulating materials such as silicon nitride.
  • a suitable solution is selected as the etching solution for etching the top semiconductor layer depending on the materials used.
  • a first substrate 210 is provided.
  • the first substrate 210 in the present embodiment is a single crystal silicon substrate.
  • the first substrate 210 is used for the supporting substrate of the top layer semiconductor layer, so the selection range is very wide.
  • the material of the first substrate 210 may be, for example, any one of silicon carbide, germanium silicon, strained silicon, and various compound semiconductors.
  • the material of the first substrate 210 may be a metal material such as aluminum or copper, in addition to a common substrate material such as single crystal silicon or sapphire.
  • a corrosion barrier layer is sequentially formed on the surface of the first substrate 210. 239 and top semiconductor layer 230.
  • the material of the top semiconductor layer 230 is single crystal silicon, and the material of the etching stopper layer 239 is silicon oxide.
  • the top semiconductor layer 230 may also be germanium, germanium silicon, and any other common semiconductor material, and the growth method thereof may be, but not limited to, a method using chemical vapor deposition; the etching barrier layer 239 may also be used in any one of the methods.
  • the top semiconductor layer 230 of the first substrate 210 is placed down on the spin-etching slide stage 290, and the etching solution for etching the top semiconductor layer 230 is passed to the back of the first substrate 210.
  • the substrate is rotated, and the etching liquid flows through the edge of the first substrate 210 to the edge of the top semiconductor layer 230 to etch the edge portion of the top semiconductor layer 230.
  • TMAH tetramethylammonium hydroxide
  • This step requires optimization of the process parameters of the concentration of the etching solution and the etching time, which enables the corrosion rate to be controlled and the corrosion time to be controlled within a reasonable range. If the flow rate of the corrosive liquid is too large or the concentration of the corrosive liquid is too high, the corrosion rate becomes fast and difficult to control; on the contrary, if the flow rate is too small or the concentration of the corrosive liquid is too low, the corrosion time becomes long, which is not conducive to improving the process efficiency. .
  • concentration range of corrosive liquid is controlled between 5% and 50%, and the flow range of the control is controlled between 0.5 and 2.0 liters per minute. It can simultaneously consider the corrosion rate and corrosion time. It is a suitable process parameter. .
  • a further preferred range for the flow of the etching solution is 1.0 to 1.5 liters per minute.
  • Another key parameter in this step is the rate of rotation of the rotating corrosion. Selecting a suitable rotational speed is advantageous for controlling the width of the edge portion which erodes the back of the top semiconductor layer 230. Excessively rotating speed causes most of the solution to be directly pulled out of the substrate without flowing through the edge to the front side of the substrate first substrate 210, and the etching liquid flowing to the front side can only be affected by the centrifugal force. Immerse into the narrow part of the edge; on the other hand, if the speed is too slow, the opposite effect is easy to obtain. Experiments have shown that the rotational rate of spin corrosion ranges from 50 to 1000 revolutions per minute, which is the preferred range of speed, especially 100 to 500 revolutions per minute.
  • the etching solution is directly introduced into the exposed top semiconductor layer 230 on the front surface of the first substrate 210, the top semiconductor layer 230 is completely removed, and edge etching cannot be performed.
  • the back surface of the first substrate 210 preferably grows a layer different from that of the first substrate 210 and the top semiconductor layer 230. Layer (not shown). Because if there is no cover layer, the etching solution is consumed by the first substrate 210 and the front semiconductor layer 230 cannot be etched. Therefore, the presence of the cover layer is particularly important in the case where the top semiconductor layer 230 and the first substrate 210 are the same material.
  • a second substrate 220 is provided for forming a support layer with an insulating buried substrate.
  • the material of the second substrate 220 is single crystal silicon.
  • the material selection of the second substrate 220 is relatively broad. Since the second substrate 220 is used as a supporting layer, in addition to a common substrate such as a single crystal silicon substrate and a sapphire substrate, silicon carbide, diamond, glass, or even a metal substrate can be selected.
  • the first substrate 210 is bonded to the second substrate 220 through an insulating buried layer 240, wherein the edge-etched top semiconductor layer 230 of the first substrate 210 faces the second liner. Bottom 220.
  • the insulating layer 240 may be formed on the surface of the first substrate 210 or the top semiconductor layer 230 in advance, or an insulating layer may be formed on the surfaces of the above two layers.
  • bonding is performed to obtain the structure shown in Fig. 14.
  • the bonding process is a common process in the art, and the specific implementation process will not be described in detail.
  • step S25 the first substrate 210 and the etch stop layer 239 are removed.
  • the present embodiment removes the first substrate 210 and the etch stop layer 239 using a spin etch process.
  • the first substrate 210 may be first thinned by a grinding process before etching.
  • the grinding process can be any abrasive thinning process that is common in the art, including chemical mechanical polishing processes.
  • the etching solution for etching the first substrate 210 is selected from tetramethylammonium hydroxide (TMAH), and the solution has good corrosion selectivity to single crystal silicon and silicon oxide. Since this step will stop on the surface of the corrosion barrier layer 239, the structure of the corrosion barrier layer 239 may not be absolutely dense, and there must be a certain density of pinholes and penetrating defects, and the etching solution easily passes through the pinholes and The penetrating defects penetrate into the top semiconductor layer 230 under the etch stop layer 239. Since the top semiconductor layer 230 is the same material as the first substrate 210 and is also single crystal silicon, the top semiconductor layer 230 is also at risk of being corroded.
  • TMAH tetramethylammonium hydroxide
  • the rotating corrosion process is used in place of the conventional embodiment.
  • Immersion etching process The spin etching process in this step is to place the first substrate 210 on the rotating platform 290 upward, and spray the etching solution onto the surface of the center of the first substrate 210 by spraying, and simultaneously rotate the first substrate 210, The corrosive liquid is caused to flow from the center to the periphery on the surface of the first substrate 210 by the centrifugal force of the rotation. Since the etching liquid and the substrate have a relative movement in the direction of the surface of the first substrate 210 during the spin etching, the immersion phenomenon of the etching liquid in the direction perpendicular to the surface of the first substrate 210 is avoided. Refer to Figure 15 for the placement and rotation of the substrate and the flow of the etching solution.
  • the rotational speed of the rotary corrosion and the temperature of the etching solution are processes that are particularly optimized in this step. Too slow rotation speed and excessive temperature are not conducive to inhibiting the immersion of corrosive liquid, and too fast rotation speed and too low temperature will cause the corrosive liquid to flow rapidly through the surface of the substrate and it is too late to cause chemical reaction, resulting in corrosion. The speed is slower, so you need to optimize the rotation speed for best results.
  • the rotation speed of the substrate is 3000 to 10000 cycles per minute, and preferably 4000 weeks; the temperature of the etching solution is 80 ° C to 100 ° C, and preferably 90 ° C At the above temperature, it is most beneficial to exert the activity of the corrosive liquid.
  • the etching solution that continues to remove the etching barrier layer 239 is hydrofluoric acid.
  • the spin etching process can be used to prevent the etching solution from being immersed in the top semiconductor layer 230 and etched into the insulating buried layer 240 at a rotational speed of 3,000 to 10,000 cycles per minute, and preferably 4000 weeks.
  • the step of using the spin etching process in this step is also advantageous in that the flatness of the surface of the top semiconductor layer 230 can be improved.
  • the placement and rotation of the substrate while continuing to remove the corrosion barrier layer 239 and the flow of the etching solution are the same as in Fig. 15.
  • a substrate with an insulating buried layer can be obtained, the structure of which is similar to that of Fig. 8 of the previous embodiment, and will not be repeatedly shown here.
  • the embodiment first performs edge etching treatment on the top semiconductor layer 230, and then performs bonding, thereby avoiding damage to the substrate during the process of performing processing on the edge of the bonded substrate;
  • the semiconductor layer 230 is etched by a spin etching process, the etching rate is easy to control, and the uniformity and concentricity are superior to the conventional etching process, and is particularly suitable for etching the edge of the wafer.
  • FIG 16 is a schematic diagram showing the implementation steps of the specific embodiment, including: Step S30, a semiconductor substrate with an insulating buried layer, the semiconductor substrate comprising a support layer, an insulating buried layer and a top semiconductor layer; Step S31, forming a capping layer on both the upper surface and the lower surface of the semiconductor substrate, The upper surface is a surface of the top semiconductor layer, and the lower surface is the other surface opposite to the upper surface; in step S32, the edge of the insulating buried layer and the top semiconductor layer are chamfered by edge grinding; step S33, the substrate is The upper surface is placed upward on the rotating corrosion carrier platform, and the etching solution of the coating layer and the etching solution of the insulating layer are sequentially passed to the silicon oxide layer on the upper surface of the substrate and the substrate is rotated simultaneously, thereby removing the surface covering layer and the lining.
  • the bottom edge is an insulating buried layer exposed by the top oxide layer being removed by polishing, while leaving the back cover layer.
  • the material of the top semiconductor layer is silicon
  • the material of the insulating buried layer and the cover layer is silicon oxide
  • the etching liquid corresponding to the insulating buried layer and the cover layer is hydrofluoric acid.
  • the top semiconductor layer may also be germanium, germanium silicon, and any other common semiconductor material; the insulating buried layer and the cap layer may be other insulating materials such as silicon nitride.
  • a suitable solution is further selected as the etching solution for etching the buried insulating layer and the covering layer depending on the materials used.
  • a semiconductor substrate 30 with an insulating buried layer is provided.
  • the semiconductor substrate 30 with an insulating buried layer includes a support layer 310, an insulating buried layer 320, and a top semiconductor layer 330.
  • the thickness of the support layer 310 is usually several hundred micrometers for supporting the insulating buried layer 320 and the top semiconductor layer 330.
  • the thickness of the above supporting insulating buried layer 320 and the top semiconductor layer 330 is usually only in the range of several micrometers to several tens of nanometers. Therefore, it needs to be disposed on the thicker supporting substrate 310 to be further used in the subsequent process.
  • the material of the support substrate 310 may be a common substrate material such as single crystal silicon or sapphire, and may even be a metal such as aluminum or copper.
  • a cover layer 340 is formed on both the front and back surfaces of the semiconductor substrate 30, including a front cover layer 341 and a back cover layer 342, the front surface being a top surface of the top semiconductor layer 330, the back surface It is the other side opposite to the front.
  • Forming the cover layer may employ a common process such as chemical deposition. If the materials of the support layer 310 and the top semiconductor layer 330 are both single crystal silicon, the thermal oxidation method can be used to form silicon dioxide as the cover layer 340. The advantage of using the thermal oxidation method is that the texture is denser than the cover layer 340 formed by other processes. , And the thickness of the front and back sides is uniform.
  • the edges of the insulating buried layer 320 and the top semiconductor layer 330 are chamfered by edge grinding.
  • edge chamfer grinding of a wafer is a common process and will not be described here.
  • the chamfering process of this step can calculate the angle and speed of the grinding, so that the edges of the insulating buried layer 320 and the top semiconductor layer 330 can be ground into a bevel, thereby exposing the edge portion of the insulating buried layer 320, thereby ensuring the subsequent etching process.
  • step S33 the upper surface of the substrate 30 is placed up on the rotating etching slide platform 390, and the etching solution of the cover layer 341 and the etching solution of the insulating buried layer 320 are sequentially passed to the substrate 30.
  • the substrate is rotated while the surface is simultaneously removed, thereby removing the front cover layer 341 and the insulating buried layer exposed at the edge of the substrate 30 due to the removal of the front cover layer 341, while retaining the back cover layer 342.
  • the insulating buried layer 320 and the cover layer 340 are made of silicon oxide. Therefore, it is possible to use hydrofluoric acid as both the etching liquid of the covering layer 340 and the etching liquid of the insulating layer 320.
  • the insulating buried layer is different from the material of the covering layer and a material that can simultaneously erode both materials cannot be found, two different etching solutions should be selected separately. And in this step, it is permissible to first apply which solution to perform the rotary corrosion.
  • the insulating buried etching solution used in this step only erodes the exposed insulating buried layer 320.
  • This step requires optimization of the process parameters of the concentration of the etching solution and the etching time, which enables the corrosion rate to be controlled and the corrosion time to be controlled within a reasonable range. If the flow rate of the corrosive liquid is too large or the concentration of the corrosive liquid is too high, the corrosion rate becomes fast and difficult to control; on the contrary, if the flow rate is too small or the concentration of the corrosive liquid is too low, the corrosion time becomes long, which is not conducive to improving the process efficiency. . Therefore, it is necessary to control the concentration and flow rate of the corrosive liquid within a suitable range to obtain a balance of corrosion controllability and speed.
  • the preferred concentration of hydrofluoric acid is from 5% to 49%, and the flow rate is from 0.5 to 2.5 liters per minute, especially from 1.5 to 2.5 liters per minute.
  • Another key parameter in this step is the rate of rotation of the rotating corrosion. If the back cover layer 342 is to be completely retained in this step, it is necessary to control the etching liquid of the cover layer not to flow to the other side of the substrate 30. Therefore, when etching is performed using a solution capable of etching the cover layer 340, it is preferable to control the rotation rate of the slide stage 390 within a large range. Experiments show that this step A preferred rate of rotation is greater than 500 cycles per minute, especially greater than 1500 cycles per minute.
  • Figure 21 is a schematic view of the substrate obtained after the above steps are carried out.
  • edges of the top semiconductor layer 330 and the insulating buried layer 320 have been removed by edge grinding chamfering, thereby avoiding occurrence of chipping or the like in a subsequent process. Moreover, by using the centrifugal action of the etching solution in the spin etching process, the cover layer 342 on the back surface of the substrate 30 is kept intact during the etching of the front cover layer 341, thereby avoiding damage to the original structure on the back surface of the substrate 30 and affecting the final product. Balanced warpage.
  • Figure 22 is a schematic view showing the implementation steps of the present embodiment, including: Step S40, providing a substrate with an insulating buried layer, the substrate with an insulating buried layer comprising a supporting layer, an insulating buried layer and a top semiconductor a layer; a step S41, forming a cover layer on the front side and the back side of the substrate, the front side is a surface of the top semiconductor layer, and the back side is the other side opposite to the front surface; Step S42, removing the cover layer on the front side of the substrate Step S43, placing the front side of the substrate down on the rotating corrosion carrier platform, passing the etching liquid of the top semiconductor layer to the cover layer on the back surface of the substrate and rotating the substrate at the same time, so that the etching liquid flows through the edge of the substrate Flowing to the front side, etching the edge portion of the front top semiconductor layer; step S44, placing the front side of the substrate on the rotating corrosion carrier platform, passing the insulating buried etching solution to the front side of
  • the material of the top semiconductor layer is silicon, and the etching liquid corresponding to the top semiconductor layer is tetramethylammonium hydroxide; the material of the insulating buried layer is silicon oxide, corresponding to the etching solution of the insulating buried layer used. It is hydrofluoric acid.
  • the top semiconductor layer may also be germanium, germanium, silicon, and any other common semiconductor material; the insulating buried layer may be other insulating materials such as silicon nitride.
  • a suitable solution is selected as the etching solution for etching the top semiconductor layer and the insulating buried layer according to the materials used.
  • a substrate 40 having an insulating buried layer is provided, and the substrate 40 having an insulating buried layer includes a supporting layer 410, an insulating buried layer 420, and a top semiconductor layer 430.
  • the thickness of the support layer 410 is usually several hundred micrometers for supporting the insulating buried layer 420 and the top semiconductor layer 430.
  • the thickness of the above supporting insulating buried layer 420 and the top semiconductor layer 430 is usually only in the range of several micrometers to several tens of nanometers. Therefore, it needs to be disposed on the thick support substrate 410 to be able to further Used in subsequent processes.
  • the material of the support substrate 410 may be a common substrate material such as single crystal silicon, sapphire or the like, and may even be a metal such as aluminum or copper.
  • a cover layer 440 is formed on both the front and back sides of the substrate 40, and includes a front cover layer 441 and a back cover layer 442, the front surface being the surface of the top semiconductor layer 430- ⁇ , and the back surface is The other side opposite the front.
  • Forming the cover layer may employ a common process such as chemical deposition. If the materials of the support layer 410 and the top semiconductor layer 430 are both single crystal silicon, silicon dioxide can be formed as the overcoat layer 440 by thermal oxidation. The advantage of using the thermal oxidation method is that the cover layer 440 formed by the other processes is denser than the other processes, and the thicknesses of the front and back sides are uniform.
  • step S42 the cover layer 441 on the front side of the substrate 410 is removed by grinding.
  • the purpose of this step is to use grinding instead of the etching layer.
  • the purpose of the grinding is to ensure that only the front cover layer 441 is removed without affecting the back cover layer 442, thereby ensuring that the back cover layer 442 remains intact after this step is completed.
  • step S43 the front side of the substrate 40 is placed on the rotating etching slide stage 490, and the etching liquid of the top semiconductor layer 430 is passed to the surface of the cover layer 442 on the back surface of the substrate 40 while rotating.
  • the substrate 40 is caused to flow through the edge of the substrate 40 to the front side to etch the edge portion of the front side semiconductor layer 430.
  • TMAH tetramethylammonium hydroxide
  • concentration range of corrosive liquid is controlled between 5% and 50%, and the flow range of the control is controlled between 0.5 and 2.0 liters per minute. It can simultaneously consider the corrosion rate and corrosion time. It is a suitable process parameter. .
  • a further preferred range for the flow of the etching solution is 1.0 to 1.5 liters per minute.
  • Another key parameter in this step is the rate of rotation of the rotating corrosion. Selecting a suitable rotational speed facilitates controlling the width of the edge portion where the top semiconductor layer 430 is etched away. Excessively rotating speed will cause most of the solution to be directly pulled out of the substrate without flowing through the edge to the front side of the substrate 40, and the corrosive liquid flowing to the front side can only be immersed to the edge due to the centrifugal force. Narrow part If the rotation speed is too slow, it is easy to obtain the opposite effect.
  • the rotational rate of rotational corrosion ranges from 50 to 1000 revolutions per minute, which is a preferred range of speeds, especially from 100 to 500 revolutions per minute.
  • this step may also be performed before step S41.
  • this step must be carried out after the implementation of the step S42. And this step cleverly utilizes the back cover layer 442 as a corrosion barrier. If there is no back cover layer 442, the etching solution will directly pass to the surface of the support layer 410.
  • the material of the top semiconductor layer 430 and the support layer 410 is a single crystal silicon material because the single crystal silicon material is the most common material in the semiconductor field.
  • the etching solution is consumed by the support layer 410 and the front semiconductor layer 430 of the front side cannot be etched. Therefore, the presence of the back cover layer 442 is particularly important for the case where the top semiconductor layer 430 and the support layer 410 are the same material.
  • step S44 the front side of the substrate 40 is placed on the rotating etching slide stage 490, and the insulating buried etching liquid is passed to the front surface of the substrate 40 while rotating the substrate 40 to remove the substrate by etching.
  • the insulating buried layer 420 is exposed at 40 edges due to the removal of the top semiconductor layer 430.
  • hydrofluoric acid can be used as the etching liquid.
  • the etching solution used in this step etches only the exposed insulating buried layer 420.
  • the concentration of the corrosive solution, the flow rate, and the rotational speed of the slide platform 490 all affect the implementation of the corrosion process. Therefore, it is necessary to control the concentration and flow rate of the corrosive liquid within a suitable range to obtain a balance of corrosion controllability and speed.
  • the preferred concentration of hydrofluoric acid is from 5% to 49%, and the flow rate is from 0.5 to 2.5 liters per minute, especially from 1.5 to 2.5 liters per minute.
  • this step preferably controls the rotation rate of the carrier platform 490 to a relatively large range.
  • the preferred rate of rotation in this step is greater than 500 cycles per minute, especially at greater than 1500 cycles per minute.
  • Figure 28 is a schematic view showing the substrate obtained after the above steps are carried out.
  • the edges of the top semiconductor layer 430 and the insulating buried layer 420 have been removed by spin etching, thereby avoiding subsequent work.
  • the occurrence of a chipping or the like occurs in the art, and the cover layer 442 on the back surface of the substrate 40 is kept intact, thereby avoiding variations in the stress state on both sides of the substrate 40 and causing a change in warpage.
  • a further advantage of the above method is that the method of removing the edge of the top semiconductor layer 420 utilizes the centrifugal force of the corrosive liquid by the spin corrosion, and thus has a better concentricity than the conventional grinding process.

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Description

一种形成带有绝缘埋层的衬底的方法
【技术领域】
本发明涉及半导体材料领域，尤其涉及一种形成具有边缘倒角的带有绝缘 埋层的衬底的方法。
【背景技术】
绝缘体上硅（SOI: Silicon On Insulator)的基本结构包括：上层的顶层硅， 中间的隐埋层二氧化硅以及底部的支撑衬底。键合 SOI的制作方法是两片硅片 用直接键合方法经高温加固后形成上述的三层结构。顶层硅（或称之为器件层) 经过一系列方法减薄到一定厚度， 但在减薄后又由于原硅片的边缘形状变化， 必须要进行一定的边缘处理， 通过边缘研磨或抛光将顶层硅的边缘去除， 否则 在后序工艺中会产生崩边等缺陷。
现有技术中， 对 SOI衬底进行边缘倒角有两种方法。
第一种是将 SOI 衬底倒角研磨后， 将 SOI 硅片浸入四甲基氢氧化铵 (TMAH) 中腐蚀掉边缘的多余的硅， 再将 SOI硅片浸入氢氟酸， 由于氢氟酸 不腐蚀硅， 因此 HF溶液将边缘残余的二氧化硅腐蚀掉。
上述工艺要消除硅片边缘的二氧化硅残留， 必须要浸入氢氟酸， 但是这样 会破坏 SOI衬底的支撑衬底表面的热氧化的二氧化硅覆盖层，从而破坏硅片的 平衡翘曲度。 另外， 浸入 TMAH后在硅表面也会引入许多不必要的缺陷。
另一种是对具有薄顶层硅的 SOI衬底在顶层硅研磨后， 不进行倒角研磨， 而是直接利用化学机械抛光的氧化物抛光液进行边缘残余二氧化硅的去除。
上述两种工艺处理方法的工艺步骤复杂， 边缘倒角后的形状不容易控制， 控制边缘的去除量以保证衬底同心度的难度很大。该方法容易产生边缘的二氧 化硅的残留， 以至于无法进行硅片单面处理， 破坏衬底的整体翘曲度， 而影响 后续工艺的应用。
【发明内容】
本发明所要解决的技术问题是，提供一种形成具有边缘倒角的带有绝缘埋 层的衬底的方法， 能够在不腐蚀背面原有的覆盖层的情况下， 完成衬底边缘的 处理工艺， 并且能够避免边缘残留多余的绝缘埋层， 从而保证衬底的翘曲度不 受影响。 为了解决上述问题，本发明提供了一种形成具有边缘倒角的带有绝缘埋层 的衬底的方法， 包括如下步骤： 提供第一衬底， 所述第一衬底用于形成带有绝 缘埋层衬底的顶层半导体层； 在第一衬底表面形成腐蚀阻挡层； 采用边缘研磨 的方法对第一衬底和其表面的腐蚀阻挡层实施倒角；采用旋转腐蚀的方法腐蚀 由于边缘研磨腐蚀阻挡层而露出来的第一衬底； 提供第二衬底， 所述第二衬底 用于形成带有绝缘埋层衬底的支撑层；将第一衬底通过一绝缘埋层键合至第二 衬底， 其中第一衬底的被边缘研磨的表面朝向第二衬底。
本发明还提供了一种形成具有边缘倒角的带有绝缘埋层的衬底的方法，包 括如下步骤： 提供第一衬底； 在第一衬底表面依次形成腐蚀阻挡层和顶层半导 体层； 将第一衬底的顶层半导体层向下放置于旋转腐蚀载片平台上， 将腐蚀顶 层半导体层的腐蚀液通至第一衬底背面并同时旋转衬底，使腐蚀液流通过第一 衬底的边沿流淌到顶层半导体层的边缘， 以腐蚀顶层半导体层的边缘部分； 提 供第二衬底， 所述第二衬底用于形成带有绝缘埋层衬底的支撑层； 将第一衬底 通过一绝缘埋层键合至第二衬底，其中第一衬底的被边缘腐蚀的顶层半导体层 朝向第二衬底； 除去第一衬底和腐蚀阻挡层。
本发明还提供了一种形成具有边缘倒角的带有绝缘埋层的衬底的方法，包 括如下步骤： 提供带有绝缘埋层的半导体衬底， 所述半导体衬底包括支撑层、 绝缘埋层和顶层半导体层； 在半导体衬底的上表面和下表面均形成覆盖层， 所 述上表面是顶层半导体层一恻的表面， 下表面是与上表面相对的另一面； 采用 边缘研磨的方法将绝缘埋层和顶层半导体层的边缘倒角；将衬底的上表面向上 放置于旋转腐蚀载片平台上，依次将覆盖层的腐蚀液和绝缘埋层的腐蚀溶液通 至衬底上表面的覆盖层并同时旋转衬底，从而除去表面的覆盖层以及衬底边缘 由于覆盖层被研磨除去而露出的绝缘埋层， 而保留背面的覆盖层。
本发明还提供了一种形成具有边缘倒角的带有绝缘埋层的衬底的方法，包 括如下步骤：提供带有绝缘埋层的衬底，所述带有绝缘埋层的衬底包括支撑层、 绝缘埋层和顶层半导体层； 在衬底的正面和背面均形成覆盖层， 所述正面是顶 层半导体层一恻的表面， 背面是与正面相对的另一面； 将衬底正面的覆盖层研 磨除去； 将衬底的正面向下放置于旋转腐蚀载片平台上， 将顶层半导体层的腐 蚀液通至衬底背面的覆盖层并同时旋转衬底，使腐蚀液流通过衬底的边沿流淌 到正面， 腐蚀正面顶层半导体层的边缘部分； 将衬底的正面向上放置于旋转腐 蚀载片平台上，将绝缘埋层腐蚀液通至衬底正面并同时旋转衬底， 腐蚀除去衬 底边缘由于顶层半导体层被腐蚀除去而露出的绝缘埋层。
本发明的优点在于， 通过在键合之前或者之后择机实施旋转腐蚀工艺， 将 顶层半导体层的边缘腐蚀除去， 从而避免后续器件工艺中发生崩边的现象； 并 根据衬底表面的情况灵活选择旋转腐蚀工艺的方式，做到即能够有效地对目标 层实施边缘腐蚀， 又不会过分伤及需要保留的部分。
【附图说明】
附图 1所示是本发明第一具体实施方式的实施步骤示意图；
附图 2至附图 8所示是本发明第一具体实施方式的工艺示意图；
附图 9所示是本发明第二具体实施方式的实施步骤示意图；
附图 10至附图 14所示是本发明第二具体实施方式的工艺示意图； 附图 15所示是本发明第三具体实施方式的实施步骤示意图；
附图 16至附图 21所示是本发明第三具体实施方式的工艺示意图； 附图 22所示是本发明第四具体实施方式的实施步骤示意图；
附图 23至附图 28所示是本发明第四具体实施方式的工艺示意图。
【具体实施方式】
下面结合附图对本发明提供的一种形成具有边缘倒角的带有绝缘埋层的 衬底的方法的具体实施方式做详细说明。
首先结合附图给出本发明的第一具体实施方式。
附图 1 所示是本具体实施方式的实施步骤示意图， 包括如下步骤： 步骤 S10, 提供第一衬底； 步骤 Sll， 在第一衬底表面形成腐蚀阻挡层， 所述腐蚀 阻挡层形成于第一衬底的所有表面； 步骤 S12， 采用边缘研磨的方法对第一衬 底的一光滑的表面和其表面的腐蚀阻挡层实施倒角； 步骤 S13， 采用旋转腐蚀 的方法腐蚀由于边缘研磨腐蚀阻挡层而露出来的第一衬底； 步骤 S14， 提供第 二衬底； 步骤 S15 , 将第一衬底通过一绝缘埋层键合至第二衬底。
附图 2至附图 8所示是本具体实施方式的工艺示意图。
附图 2所示， 参考步骤 S10， 提供第一衬底 110。 本实施方式中的第一衬 底 110为单晶硅衬底。第一衬底 110用于形成带有绝缘埋层衬底的顶层半导体 层。 因此在其他的实施方式中， 需要根据目标产品的需求选择第一衬底 110的 材料，例如可以是碳化硅、锗硅、应变硅和各种化合物半导体等中的任意一种。
更正页 (细则第 91条） 附图 3所示， 参考步骤 Sll， 在第一衬底 110表面形成腐蚀阻挡层 111， 所述腐蚀阻挡层 111形成于第一衬底 110的所有表面。 本实施方式中， 腐蚀阻 挡层 111的材料为氧化硅， 可以采用热氧化的方法形成。
在第一衬底 110的正面和背面都形成腐蚀阻挡层 111的优点还在于能够保 护第一衬底 110的背面， 防止其在后续的步骤中受到腐蚀液的腐蚀。 第一衬底 110背面被腐蚀会影响到衬底的整体翘曲特性， 为键合工艺带来不确定性。
在其他的实施方式中，应当根据第一衬底 110的材料和后续选择性腐蚀工 艺所采用的腐蚀液的性质选择合适的腐蚀阻挡层 111的材料。在选择性腐蚀工 艺中如何选择腐蚀阻挡层的材料是本领域内的公知常识， 此处不再一一列举。
附图 4所示， 参考步骤 S12, 采用边缘研磨的方法对第一衬底 110的一光 滑的表面和其表面的腐蚀阻挡层 111实施倒角。
对晶圆进行边缘倒角研磨的工艺是一种常见工艺， 此处不再赘述。本步骤 的倒角工艺通过计算研磨的角度和速度， 使腐蚀阻挡层 111和第一衬底 110的 边缘都能够被研磨成斜面， 从而露出第一衬底 110的边缘部分， 保证后续腐蚀 工艺的顺利实施。
附图 5所示， 参考步骤 S13, 采用旋转腐蚀的方法腐蚀由于边缘研磨腐蚀 阻挡层而露出来的第一衬底 110。 本具体实施方式中是将第一衬底 110被倒角 的表面向上放置于旋转腐蚀载片平台 190上，将腐蚀液通至向上的表面并同时 旋转第一衬底 110。
本具体实施方式由于采用的是氧化硅作为腐蚀阻挡层 111， 能够耐受腐蚀 液较长时间的腐蚀， 因此可以将第一衬底 110被倒角的表面向上放置于旋转腐 蚀载片平台上， 将腐蚀液直接通至向上的表面， 即腐蚀阻挡层 111的表面， 并 同时旋转衬底。
为了保证选转腐蚀的质量， 需要对旋转腐蚀的旋转速率作出优化。本步骤 中如果要更高效的腐蚀第一半导体层 110的边缘，就要尽量控制腐蚀液不要流 淌到第一衬底 110的另一面。 因此， 在旋转腐蚀时最好能够控制载片平台 190 的旋转速率在一个较大的范围内。 实验表明， 本步骤中较佳的旋转速率是大于 每分钟 500圈， 尤其以大于每分钟 1500圈为最佳。
如前述步骤所述， 本具体实施方式中的第一衬底 110为单晶硅衬底， 腐蚀 阻挡层 111的材料为氧化硅， 故本步骤中可以采用四甲基氢氧化铵作为旋转腐 蚀所采用的腐蚀液。 当然， 本领域内常见的氢氧化钾或邻苯二酚-乙二胺 -水等 腐蚀液也可以用于此步骤之中。
腐蚀液的浓度和腐蚀时间也是需要优化的工艺参数，从而做到腐蚀速率可 控， 并且将腐蚀时间控制在合理的范围内。如果腐蚀液的通入流量过大或者腐 蚀液的浓度过高， 腐蚀速率变快而难以控制； 反之通入流量过小或者腐蚀液的 浓度过低， 则腐蚀时间变长， 不利于提高工艺效率。 因此， 需要控制腐蚀液的 浓度和流量在合适的范围内， 以获得腐蚀可控性和速度的平衡。 实验表明， 所 述腐蚀溶液的质量浓度范围是 5%至 49%， 所通入腐蚀液的流量范围为每分钟 500至 2500毫升是优选的工艺参数。
附图 6所示， 参考步骤 S14, 提供第二衬底 120。 所述第二衬底 120用于 形成带有绝缘埋层衬底的支撑层。
第二衬底 120的材料选择较为宽泛。 由于第二衬底 120是用作支撑层， 因 此除常见的单晶硅衬底和蓝宝石衬底等常见衬底之外， 碳化硅、 金刚石、 玻璃 甚至于金属衬底等都是可用的选择。
附图 7所示， 参考步骤 S15, 将第一衬底 110通过一绝缘埋层键合至第二 衬底 120。 其中第一衬底 110的被边缘研磨的表面朝向第二衬底 120。 本实施 方式中， 绝缘埋层就是前述步骤中用作腐蚀阻挡的腐蚀阻挡层 111。
在其他的实施方式中， 如果腐蚀阻挡层 111是不绝缘的， 或者腐蚀阻挡层 在腐蚀的过程中表面受到损伤，或者由于其他各种原因导致其不适合用做最终 产品的绝缘埋层， 则也可以将腐蚀阻挡层 111除去， 另行生长一层新的绝缘埋 层。新的绝缘埋层可以生长在第一衬底 110的表面，也可以生长在第二衬底 120 的表面， 当然也可以同时生长在两个衬底的表面。
键合工艺是本领域的常见工艺， 具体实施过程不再详述。
在步骤 S15实施完毕之后，还可以进一步根据需要对第一衬底 110实施减 薄至目标厚度， 减薄可以采用包括腐蚀、 研磨和剥离等多种常见的工艺方法， 此处不再赘述。
附图 8所示是经过减薄后的具有绝缘埋层 111的衬底， 包括用作支撑衬底 的第二衬底 120和减薄后用作顶层半导体层的第一衬底 110。由于第一衬底 110 用于键合的表面之前进行过倒角处理， 因此键合减薄后衬底的顶层半导体层的 边缘已经在键合之前先行被去除， 不需要再次处理。 相比于现有技术而言， 本 具体实施方式先对顶层半导体层进行边缘腐蚀处理， 再实施键合， 从而避免了 对键合后的衬底的边缘实施处理的过程中损伤衬底；采用旋转腐蚀工艺对欲形 成顶层半导体层的第一衬底实施腐蚀， 腐蚀速率易于控制， 且均匀度和同心度 优于普通的腐蚀工艺， 尤其适合对晶圆的边缘进行腐蚀。
接下来结合附图说明本发明的第二具体实施方式。
附图 9 所示是本具体实施方式的实施步骤示意图， 包括如下步骤： 步骤 S20, 提供第一衬底； 步骤 S21 , 在第一衬底表面依次形成腐蚀阻挡层和顶层 半导体层； 步骤 S22， 将第一衬底的顶层半导体层向下放置于旋转腐蚀载片平 台上， 将腐蚀顶层半导体层的腐蚀液通至第一衬底背面并同时旋转衬底， 使腐 蚀液流通过第一衬底的边沿流淌到顶层半导体层的边缘， 以腐蚀顶层半导体层 的边缘部分； 步骤 S23, 提供第二衬底， 所述第二衬底用于形成带有绝缘埋层 衬底的支撑层； 步骤 S24, 将第一衬底通过一绝缘埋层键合至第二衬底， 其中 第一衬底的被边缘腐蚀的顶层半导体层朝向第二衬底； 步骤 S25, 除去第一衬 底和腐蚀阻挡层。
本具体实施方式中， 顶层半导体层的材料为硅， 对应所采用的顶层半导体 层腐蚀液为四甲基氢氧化铵； 绝缘埋层的材料为氧化硅。在其他的具体实施方 式中， 顶层半导体层也可是锗、 锗硅以及其他任何常见的半导体材料； 绝缘埋 层可以是氮化硅等其他绝缘材料。并根据所采用的材料选择合适的溶液作为腐 蚀顶层半导体层的腐蚀溶液。
附图 10至附图 15为本具体实施方式的工艺流程图。
附图 10所示， 参考步骤 S20, 提供第一衬底 210。
本实施方式中的第一衬底 210为单晶硅衬底。第一衬底 210用于顶层半导 体层的支撑衬底，因此选材范围非常宽泛。在其他的实施方式中，第一衬底 210 的材料例如可以是碳化硅、锗硅、应变硅和各种化合物半导体等中的任意一种。 所述第一衬底 210的材料除了可以是单晶硅、 蓝宝石等常见的衬底材料之外， 甚至也可以是铝或者铜等金属材料。
附图 11所示， 参考步骤 S21， 在第一衬底 210表面依次形成腐蚀阻挡层 239和顶层半导体层 230。
本实施方式中， 所述顶层半导体层 230的材料为单晶硅， 腐蚀阻挡层 239 的材料是氧化硅。 在其他的实施方式中， 顶层半导体层 230也可以是锗、 锗硅 以及其他任何常见的半导体材料，其生长方法可以但不限于采用化学气相沉积 的方法； 腐蚀阻挡层 239也可以采用任何一种能够起到腐蚀阻挡作用的材料， 例如氮化硅、 或者具有不同掺杂浓度的单晶硅等。
附图 12所示， 参考步骤 S22, 将第一衬底 210的顶层半导体层 230向下 放置于旋转腐蚀载片平台 290上，将腐蚀顶层半导体层 230的腐蚀液通至第一 衬底 210背面并同时旋转衬底，使腐蚀液流通过第一衬底 210的边沿流淌到顶 层半导体层 230的边缘， 以腐蚀顶层半导体层 230的边缘部分。
在顶层半导体层 230 的材料为硅的情况下， 可以采用四甲基氢氧化铵 (TMAH)作为腐蚀液。此步骤需要优化腐蚀液的浓度和腐蚀时间的工艺参数， 能够做到腐蚀速率可控， 并且将腐蚀时间控制在合理的范围内。如果腐蚀液的 通入流量过大或者腐蚀液的浓度过高， 腐蚀速率变快而难以控制； 反之通入流 量过小或者腐蚀液的浓度过低， 则腐蚀时间变长， 不利于提高工艺效率。 实践 表明， 腐蚀液的质量浓度范围控制在 5%至 50%之间， 通入的流量范围控制在 每分钟 0.5至 2.0升之间， 能够同时兼顾腐蚀速度和腐蚀时间， 是较为合适的 工艺参数。 通入腐蚀液流量的进一步优选范围是每分钟 1.0至 1.5升。
此步骤中， 另一个关键的参数是旋转腐蚀的旋转速率。选择合适的转速有 利于控制将顶层半导体层 230的背腐蚀掉的边缘部分的宽度。旋转速度过快会 导致大部分的溶液都被直接甩到衬底之外而不会通过边缘流到衬底第一衬底 210的正面， 并且流淌到正面的腐蚀液由于离心力的作用而只能浸入到边缘很 窄的部分； 反之如果转速过慢， 则容易获得相反的效果。 实验表明， 旋转腐蚀 的旋转速率范围是每分钟 50至 1000圈是优选的转速范围，尤其每分钟 100至 500圈为更佳。
本步骤中，如果直接将腐蚀液通入第一衬底 210正面裸露的顶层半导体层 230， 会将顶层半导体层 230全部除去， 无法做到边缘腐蚀。
在顶层半导体层 230与第一衬底 210的材料相同的情况下， 第一衬底 210 的背面最好生长一层与第一衬底 210和顶层半导体层 230的材料不相同的覆盖 层 （图中未示出）。 因为如果没有覆盖层， 腐蚀液会被第一衬底 210消耗而无 法腐蚀正面的顶层半导体层 230。 因此对于顶层半导体层 230和第一衬底 210 材料相同的情况下， 覆盖层的存在显得尤其重要。
附图 13所示， 参考步骤 S23 , 提供第二衬底 220， 所述第二衬底 220用于 形成带有绝缘埋层衬底的支撑层。
本实施方式中第二衬底 220的材料为单晶硅。第二衬底 220的材料选择较 为宽泛。 由于第二衬底 220是用作支撑层， 因此除常见的单晶硅衬底和蓝宝石 衬底等常见衬底之外， 碳化硅、 金刚石、 玻璃甚至于金属衬底等都是可用的选 择。
附图 14所示， 参考步骤 S24, 将第一衬底 210通过一绝缘埋层 240键合 至第二衬底 220， 其中第一衬底 210的被边缘腐蚀的顶层半导体层 230朝向第 二衬底 220。
绝缘层 240可以预先形成在第一衬底 210或者顶层半导体层 230的表面， 也可以在上述两层的表面都形成绝缘层。
形成绝缘层 230之后， 再实施键合以获得附图 14所示的结构。 键合工艺 是本领域的常见工艺， 具体实施过程不再详述。
附图 15所示， 参考步骤 S25 , 除去第一衬底 210和腐蚀阻挡层 239。 本具 体实施方式采用旋转腐蚀工艺除去第一衬底 210和腐蚀阻挡层 239。
由于第一衬底 210的厚度通常是数百微米以上， 为了提高工艺效率， 可以 在腐蚀之前首先采用研磨工艺减薄第一衬底 210。 所述研磨工艺可以是包括化 学机械抛光工艺在内的任何本领域内常见的研磨减薄工艺。
本具体实施方式中，所述腐蚀第一衬底 210的腐蚀液选用四甲基氢氧化铵 (TMAH) , 该溶液对单晶硅与氧化硅的腐蚀选择性较好。 由于该步骤将停止 在腐蚀阻挡层 239的表面， 而腐蚀阻挡层 239的结构不可能是绝对致密的， 必 然存在一定密度的针孔和穿透性的缺陷，而腐蚀液很容易通过针孔和穿透性缺 陷渗透到腐蚀阻挡层 239下面的顶层半导体层 230。 由于顶层半导体层 230与 第一衬底 210的材料相同， 同为单晶硅， 因此顶层半导体层 230也有被腐蚀的 危险。
为了避免上述现象的发生，本具体实施方式中采用旋转腐蚀工艺替代传统 的浸入式腐蚀工艺。本步骤中的旋转腐蚀工艺是将第一衬底 210向上放置在旋 转平台 290上， 并将腐蚀液采用喷射的方式喷射到第一衬底 210中心的表面， 并同时旋转第一衬底 210， 使腐蚀液在旋转离心力的作用下在第一衬底 210表 面由中央向四周流动。 由于旋转腐蚀过程中腐蚀液与衬底具有沿第一衬底 210 表面方向的相对运动， 因此避免了腐蚀液沿垂直第一衬底 210表面方向产生的 浸入现象。 衬底的放置和旋转以及腐蚀液的流动方式请参考附图 15。
旋转腐蚀的旋转速度和腐蚀液温度对是本步骤中尤其需要优化的工艺。过 慢的旋转速度和过高的温度不利于抑制腐蚀液的浸入现象，而过快的旋转速度 和过低的温度会导致腐蚀液迅速的流过衬底的表面而来不及发生化学反应，导 致腐蚀速度变慢， 因此需要优化旋转速度以获得最佳效果。 本步骤中， 所述旋 转腐蚀工艺中，衬底的旋转速度为每分钟 3000至 10000周，并优选为 4000周； 腐蚀液的温度范围是 80°C至 100°C，并优选为 90°C， 以上温度下最有利于发挥 腐蚀液的活性。
本具体实施方式中， 在第一衬底 210除去之后， 继续除去腐蚀阻挡层 239 的腐蚀液为氢氟酸。 同上面的叙述类似， 采用旋转腐蚀工艺可以避免腐蚀液浸 入顶层半导体层 230而腐蚀到绝缘埋层 240，旋转速度为每分钟 3000至 10000 周， 并优选为 4000周。 并且， 本步骤采用旋转腐蚀工艺的优点还在于能够提 高顶层半导体层 230表面的平整度。继续除去腐蚀阻挡层 239时的衬底的放置 和旋转以及腐蚀液的流动方式与附图 15相同。
在实施了包括上述步骤的工艺之后， 能够获得带有绝缘埋层的衬底， 其结 构与前一个具体实施方式的附图 8类似， 此处不再重复展示。
由于顶层半导体层 230用于键合之前进行过边缘腐蚀处理， 因此键合减薄 后衬底的顶层半导体层 230的边缘已经在键合之前先行被去除，不需要再次处 理。 相比于现有技术而言， 本具体实施方式先对顶层半导体层 230进行边缘腐 蚀处理， 再实施键合， 从而避免了对键合后的衬底的边缘实施处理的过程中损 伤衬底； 采用旋转腐蚀工艺对半导体层 230实施腐蚀， 腐蚀速率易于控制， 且 均匀度和同心度优于普通的腐蚀工艺， 尤其适合对晶圆的边缘进行腐蚀。
接下来结合附图给出本发明的第三具体实施方式。
附图 16所示是本具体实施方式的实施步骤示意图， 包括： 步骤 S30， 提 供带有绝缘埋层的半导体衬底， 所述半导体衬底包括支撑层、 绝缘埋层和顶层 半导体层； 步骤 S31 , 在所述半导体衬底的上表面和下表面均形成覆盖层， 所 述上表面是顶层半导体层一恻的表面， 下表面是与上表面相对的另一面； 步骤 S32, 采用边缘研磨的方法将绝缘埋层和顶层半导体层的边缘倒角； 步骤 S33, 将衬底的上表面向上放置于旋转腐蚀载片平台上，依次将覆盖层的腐蚀液和绝 缘埋层的腐蚀溶液通至衬底上表面的氧化硅层并同时旋转衬底，从而除去表面 的覆盖层以及衬底边缘由于顶层氧化层被研磨除去而露出的绝缘埋层，而保留 背面的覆盖层。
本具体实施方式中， 顶层半导体层的材料为硅， 绝缘埋层与覆盖层的材料 为氧化硅， 对应所采用的绝缘埋层与覆盖层的腐蚀液均为氢氟酸。在其他的具 体实施方式中，顶层半导体层也可是锗、锗硅以及其他任何常见的半导体材料; 绝缘埋层与覆盖层可以是氮化硅等其他绝缘材料。 在采用其他材料的情况下， 进一步根据所采用的材料选择合适的溶液作为腐蚀绝缘埋层和覆盖层的腐蚀 溶液。
附图 17至附图 21为本具体实施方式的工艺流程图。
附图 17所示， 参考步骤 S30, 提供带有绝缘埋层的半导体衬底 30， 所述 带有绝缘埋层的半导体衬底 30包括支撑层 310、绝缘埋层 320和顶层半导体层 330。
所述支撑层 310的厚度通常为数百微米，用于支撑绝缘埋层 320和顶层半 导体层 330， 以上支撑绝缘埋层 320和顶层半导体层 330的厚度通常只有数微 米至数十纳米的范围内， 因此需要设置在较厚的支撑衬底 310上才能够进一步 用于后续工艺。所述支撑衬底 310的材料可以是单晶硅、 蓝宝石等常见的衬底 材料， 甚至也可以是铝或者铜等金属。
附图 18所示， 参考步骤 S31 , 在半导体衬底 30的正面和背面均形成覆盖 层 340，包括正面覆盖层 341和背面覆盖层 342，所述正面是顶层半导体层 330 一恻的表面， 背面是与正面相对的另一面。
形成覆盖层可以采用化学沉积等常见工艺。如果支撑层 310和顶层半导体 层 330的材料均为单晶硅，则可以采用热氧化的方法形成二氧化硅作为覆盖层 340ο 采用热氧化方法的优点在于质地较其他的工艺形成的覆盖层 340致密， 并且正面和背面的厚度均匀一致。
附图 19所示， 参考步骤 S32, 采用边缘研磨的方法将绝缘埋层 320和顶 层半导体层 330的边缘倒角。
对晶圆进行边缘倒角研磨的工艺是一种常见工艺， 此处不再赘述。本步骤 的倒角工艺通过计算研磨的角度和速度，能够做到绝缘埋层 320和顶层半导体 层 330的边缘都能够被研磨成斜面， 从而露出绝缘埋层 320的边缘部分， 保证 后续腐蚀工艺的顺利实施。
附图 20所示， 参考步骤 S33, 将衬底 30的上表面向上放置于旋转腐蚀载 片平台 390上，依次将覆盖层 341的腐蚀液和绝缘埋层 320的腐蚀溶液通至衬 底 30上表面并同时旋转衬底，从而除去正面的覆盖层 341以及衬底 30边缘由 于正面的覆盖层 341被研磨除去而露出的绝缘埋层，而保留背面的覆盖层 342。
本具体实施方式中， 绝缘埋层 320与覆盖层 340的材料均为氧化硅。 因此 可以采用氢氟酸既作为覆盖层 340腐蚀液， 也作为绝缘埋层 320腐蚀液。
在其他的实施方式中，如果绝缘埋层与覆盖层的材料不同并且无法找到一 种同时可以腐蚀两种材料的情况下， 应当分别选择两种不同的腐蚀液。 并且此 步骤中， 先通入何种溶液进行旋转腐蚀都是允许的。
由于顶层半导体层 330的阻挡作用，本步骤所采用的绝缘埋层腐蚀液只腐 蚀露出的绝缘埋层 320。
此步骤需要优化腐蚀液的浓度和腐蚀时间的工艺参数，能够做到腐蚀速率 可控， 并且将腐蚀时间控制在合理的范围内。 如果腐蚀液的通入流量过大或者 腐蚀液的浓度过高， 腐蚀速率变快而难以控制； 反之通入流量过小或者腐蚀液 的浓度过低， 则腐蚀时间变长， 不利于提高工艺效率。 因此， 需要控制腐蚀液 的浓度和流量在合适的范围内， 以获得腐蚀可控性和速度的平衡。 较佳的氢氟 酸质量浓度是 5%至 49%, 流量范围是每分钟 0.5至 2.5升， 尤其以每分钟 1.5 至 2.5升为最佳。
此步骤中， 另一个关键的参数是旋转腐蚀的旋转速率。本步骤中如果要将 背面覆盖层 342完整保留下来，就要尽量控制覆盖层的腐蚀液不要流淌到衬底 30的另一面。 因此， 在采用能够腐蚀覆盖层 340的溶液进行腐蚀的时候， 最好 能够控制载片平台 390的旋转速率在一个较大的范围内。 实验表明， 本步骤中 较佳的旋转速率是大于每分钟 500圈， 尤其以大于每分钟 1500圈为最佳。 附图 21所示是上述步骤实施完毕后获得的衬底示意图。顶层半导体层 330 和绝缘埋层 320的边缘已经通过边缘研磨倒角的方法被除去，从而避免了在后 续工艺中产生崩边等情况的发生。并且利用旋转腐蚀工艺中对腐蚀液的离心作 用， 在腐蚀正面覆盖层 341的过程中保持衬底 30背面的覆盖层 342完整， 避 免了对衬底 30背面原有结构的损伤而影响到最终产品的平衡翘曲度。
接下来结合附图给出本发明的第四具体实施方式。
附图 22所示是本具体实施方式的实施步骤示意图， 包括： 步骤 S40, 提 供带有绝缘埋层的衬底， 所述带有绝缘埋层的衬底包括支撑层、 绝缘埋层和顶 层半导体层； 步骤 S41 , 在衬底的正面和背面均形成覆盖层， 所述正面是顶层 半导体层一恻的表面， 背面是与正面相对的另一面； 步骤 S42， 将衬底正面的 覆盖层研磨除去； 步骤 S43 , 将衬底的正面向下放置于旋转腐蚀载片平台上， 将顶层半导体层的腐蚀液通至衬底背面的覆盖层并同时旋转衬底，使腐蚀液流 通过衬底的边沿流淌到正面， 腐蚀正面顶层半导体层的边缘部分； 步骤 S44, 将衬底的正面向上放置于旋转腐蚀载片平台上，将绝缘埋层腐蚀液通至衬底正 面并同时旋转衬底，腐蚀除去衬底边缘由于顶层半导体层被腐蚀除去而露出的 绝缘埋层。
本具体实施方式中， 顶层半导体层的材料为硅， 对应所采用的顶层半导体 层腐蚀液为四甲基氢氧化铵； 绝缘埋层的材料为氧化硅， 对应所采用的绝缘埋 层的腐蚀液为氢氟酸。 在其他的具体实施方式中， 顶层半导体层也可是锗、 锗 硅以及其他任何常见的半导体材料； 绝缘埋层可以是氮化硅等其他绝缘材料。 并根据所采用的材料选择合适的溶液作为腐蚀顶层半导体层和绝缘埋层的腐 蚀溶液。
附图 23至附图 28为本具体实施方式的工艺流程图。
附图 23所示， 参考步骤 S40, 提供带有绝缘埋层的衬底 40， 所述带有绝 缘埋层的衬底 40包括支撑层 410、 绝缘埋层 420和顶层半导体层 430。
所述支撑层 410的厚度通常为数百微米，用于支撑绝缘埋层 420和顶层半 导体层 430， 以上支撑绝缘埋层 420和顶层半导体层 430的厚度通常只有数微 米至数十纳米的范围内， 因此需要设置在较厚的支撑衬底 410上才能够进一步 用于后续工艺。所述支撑衬底 410的材料可以是单晶硅、 蓝宝石等常见的衬底 材料， 甚至也可以是铝或者铜等金属。
附图 24所示， 参考步骤 S41 , 在衬底 40的正面和背面均形成覆盖层 440， 包括正面覆盖层 441和背面覆盖层 442， 所述正面是顶层半导体层 430—恻的 表面， 背面是与正面相对的另一面。
形成覆盖层可以采用化学沉积等常见工艺。如果支撑层 410和顶层半导体 层 430的材料均为单晶硅，则可以采用热氧化的方法形成二氧化硅作为覆盖层 440。 采用热氧化方法的优点在于质地较其他的工艺形成的覆盖层 440致密， 并且正面和背面的厚度均匀一致。
附图 25所示， 参考步骤 S42, 将衬底 410正面的覆盖层 441研磨除去。 此步骤采用研磨而不采用腐蚀层其他方法的目的在于，研磨可以保证只将 正面覆盖层 441除去而不影响背面覆盖层 442， 从而保证背面覆盖层 442在此 步骤实施完毕之后仍然保持完整。
附图 26所示， 参考步骤 S43， 将衬底 40的正面向下放置于旋转腐蚀载片 平台 490上， 将顶层半导体层 430的腐蚀液通至衬底 40背面的覆盖层 442表 面并同时旋转衬底 40， 使腐蚀液流通过衬底 40的边沿流淌到正面， 腐蚀正面 顶层半导体层 430的边缘部分。
在顶层半导体层 430 的材料为硅的情况下， 可以采用四甲基氢氧化铵 (TMAH)作为腐蚀液。此步骤需要优化腐蚀液的浓度和腐蚀时间的工艺参数， 能够做到腐蚀速率可控， 并且将腐蚀时间控制在合理的范围内。如果腐蚀液的 通入流量过大或者腐蚀液的浓度过高， 腐蚀速率变快而难以控制； 反之通入流 量过小或者腐蚀液的浓度过低， 则腐蚀时间变长， 不利于提高工艺效率。 实践 表明， 腐蚀液的质量浓度范围控制在 5%至 50%之间， 通入的流量范围控制在 每分钟 0.5至 2.0升之间， 能够同时兼顾腐蚀速度和腐蚀时间， 是较为合适的 工艺参数。 通入腐蚀液流量的进一步优选范围是每分钟 1.0至 1.5升。
此步骤中， 另一个关键的参数是旋转腐蚀的旋转速率。选择合适的转速有 利于控制将顶层半导体层 430被腐蚀掉的边缘部分的宽度。旋转速度过快会导 致大部分的溶液都被直接甩到衬底之外而不会通过边缘流到衬底 40的正面， 并且流淌到正面的腐蚀液由于离心力的作用而只能浸入到边缘很窄的部分；反 之如果转速过慢， 则容易获得相反的效果。 实验表明， 旋转腐蚀的旋转速率范 围是每分钟 50至 1000圈是优选的转速范围，尤其每分钟 100至 500圈为更佳。
本步骤中， 如果直接将腐蚀液通入衬底 40正面裸露的顶层半导体层 430， 会将顶层半导体层 430全部除去， 无法做到边缘腐蚀。
在顶层半导体层 430与支撑层 410的材料不同，并且腐蚀液并不腐蚀支撑 层 410的情况下， 本步骤也可以在步骤 S41之前实施。
在顶层半导体层 430与支撑层 410的材料相同的情况下，此步骤必须在步 骤 S42实施完毕后实施。并且此步骤巧妙的利用了背面的覆盖层 442作为腐蚀 阻挡层，如果没有背面的覆盖层 442，则腐蚀液会直接通到支撑层 410的表面。
在大多数情况下，顶层半导体层 430与支撑层 410的材料都是单晶硅材料， 因为单晶硅材料是半导体领域最为常见的材料。而在此情况下， 腐蚀液会被支 撑层 410消耗而无法腐蚀正面的顶层半导体层 430。因此对于顶层半导体层 430 和支撑层 410材料相同的情况下， 背面覆盖层 442的存在显得尤其重要。
附图 27所示， 参考步骤 S44, 将衬底 40的正面向上放置于旋转腐蚀载片 平台 490上， 将绝缘埋层腐蚀液通至衬底 40正面并同时旋转衬底 40， 腐蚀除 去衬底 40边缘由于顶层半导体层 430被腐蚀除去而露出的绝缘埋层 420。
在绝缘埋层 420的材料为硅的情况下， 可以采用氢氟酸作为腐蚀液。
由于顶层半导体层 430的阻挡作用，本步骤所采用的腐蚀液只腐蚀露出的 绝缘埋层 420。
同上面步骤类似的， 腐蚀液的浓度、 流量以及载片平台 490的旋转速度都 会影响到腐蚀工艺的实施效果。 因此， 需要控制腐蚀液的浓度和流量在合适的 范围内， 以获得腐蚀可控性和速度的平衡。 较佳的氢氟酸质量浓度是 5%至 49%， 流量范围是每分钟 0.5至 2.5升， 尤其以每分钟 1.5至 2.5升为最佳。
但是，同步骤 S43相反的是，本步骤中要将背面覆盖层 442完整保留下来， 因此并不希望腐蚀液留到衬底 40的另一面。 所以本步骤最好能够控制载片平 台 490的旋转速率在一个较大的范围内。 实验表明， 本步骤中较佳的旋转速率 是大于每分钟 500圈， 尤其以大于每分钟 1500圈为最佳。
附图 28示是上述步骤实施完毕后获得的衬底示意图。 顶层半导体层 430 和绝缘埋层 420的边缘已经通过旋转腐蚀的方法被除去，从而避免了在后续工 艺中产生崩边等情况的发生， 并且将衬底 40背面的覆盖层 442保持完整， 避 免了衬底 40两面的应力状态不均衡而引起翘曲度的变化。 上述方法进一步的 优点还在于除去顶层半导体层 420边缘的方法利用的是旋转腐蚀对腐蚀液的离 心力作用， 因此同普通的研磨工艺相比具有更好的同心度。
以上所述仅是本发明的优选实施方式， 应当指出， 对于本技术领域的普通 技术人员， 在不脱离本发明原理的前提下， 还可以做出若干改进和润饰， 这些 改进和润饰也应视为本发明的保护范围。

Claims

权 利 要 求 书
1. 一种形成具有边缘倒角的带有绝缘埋层的衬底的方法， 其特征在于， 包括 如下步骤：
提供第一衬底，所述第一衬底用于形成带有绝缘埋层衬底的顶层半导体层； 在第一衬底表面形成腐蚀阻挡层；
采用边缘研磨的方法对第一衬底和其表面的腐蚀阻挡层实施倒角； 采用旋转腐蚀的方法腐蚀由于边缘研磨腐蚀阻挡层而露出来的第一衬底； 提供第二衬底， 所述第二衬底用于形成带有绝缘埋层衬底的支撑层； 将第一衬底通过一绝缘埋层键合至第二衬底， 其中第一衬底的被边缘研磨 的表面朝向第二衬底。
2. 根据权利要求 1所述的形成具有边缘倒角的带有绝缘埋层的衬底的方法， 其特征在于， 所述腐蚀阻挡层形成于第一衬底的所有表面， 边缘研磨的步 骤中选择一光滑的表面实施。
3. 根据权利要求 2所述的形成具有边缘倒角的带有绝缘埋层的衬底的方法， 其特征在于， 所述旋转腐蚀的步骤中， 将第一衬底被倒角的表面向上放置 于旋转腐蚀载片平台上， 将腐蚀液通至向上的表面并同时旋转衬底， 旋转 腐蚀的旋转速率大于每分钟 500圈。
4. 根据权利要求 3所述的形成具有边缘倒角的带有绝缘埋层的衬底的方法， 其特征在于， 所述第一衬底为单晶硅衬底， 所述腐蚀阻挡层为氧化硅， 所 述旋转腐蚀所采用的腐蚀液是四甲基氢氧化铵。
5. 根据权利要求 4所述的形成具有边缘倒角的带有绝缘埋层的衬底的方法， 其特征在于， 所述氢氟酸腐蚀溶液的质量浓度范围是 5%至 49%。
6. 根据权利要求 4所述的形成具有边缘倒角的带有绝缘埋层的衬底的方法， 其特征在于， 所通入氢氟酸的流量范围为每分钟 500至 2500毫升。
7. 一种形成具有边缘倒角的带有绝缘埋层的衬底的方法， 其特征在于， 包括 如下步骤：
提供第一衬底；
在第一衬底表面依次形成腐蚀阻挡层和顶层半导体层；
将第一衬底的顶层半导体层向下放置于旋转腐蚀载片平台上， 将腐蚀顶层 半导体层的腐蚀液通至第一衬底背面并同时旋转衬底， 使腐蚀液流通过第 一衬底的边沿流淌到顶层半导体层的边缘， 以腐蚀顶层半导体层的边缘部 分；
提供第二衬底， 所述第二衬底用于形成带有绝缘埋层衬底的支撑层； 将第一衬底通过一绝缘埋层键合至第二衬底， 其中第一衬底的被边缘腐蚀 的顶层半导体层朝向第二衬底；
除去第一衬底和腐蚀阻挡层。
8. 根据权利要求 7所述的形成具有边缘倒角的带有绝缘埋层的衬底的方法， 其特征在于， 腐蚀顶层半导体层的步骤中， 旋转腐蚀的旋转速率范围是每 分钟 50至 1000圈。
9. 根据权利要求 7或 8所述的形成具有边缘倒角的带有绝缘埋层的衬底的方 法， 其特征在于， 所述顶层半导体层的材料为硅， 腐蚀顶层半导体层的腐 蚀液为四甲基氢氧化铵。
10.根据权利要求 9所述的形成具有边缘倒角的带有绝缘埋层的衬底的方法， 其特征在于， 腐蚀顶层半导体层的步骤中， 四甲基氢氧化铵的质量浓度范 围是 5%至 50%， 流量范围是每分钟 0.5至 2.0升。
11.一种形成具有边缘倒角的带有绝缘埋层的衬底的方法， 其特征在于， 包括 如下步骤：
提供带有绝缘埋层的半导体衬底， 所述绝缘体上硅衬底包括支撑层、 绝缘 埋层和顶层半导体层；
在衬底的上表面和下表面均形成覆盖层， 所述上表面是顶层半导体层一恻 的表面， 下表面是与上表面相对的另一面；
采用边缘研磨的方法将绝缘埋层和顶层半导体层的边缘倒角；
将衬底的上表面向上放置于旋转腐蚀载片平台上， 依次将覆盖层的腐蚀液 和绝缘埋层的腐蚀溶液通至衬底上表面的覆盖层并同时旋转衬底， 从而除 去表面的覆盖层以及衬底边缘由于覆盖层被研磨除去而露出的绝缘埋层， 而保留背面的覆盖层。
12.根据权利要求 11所述的形成具有边缘倒角的带有绝缘埋层的衬底的方法， 其特征在于， 所述绝缘埋层与覆盖层由相同的材料构成， 所述绝缘埋层的 腐蚀液和绝缘埋层的腐蚀溶液为同一种溶液。
13.根据权利要求 11或 12所述的形成具有边缘倒角的带有绝缘埋层的衬底的 方法， 其特征在于， 所述腐蚀覆盖层以及绝缘埋层的步骤中， 旋转腐蚀的 旋转速率大于每分钟 500圈。
14.根据权利要求 12所述的形成具有边缘倒角的带有绝缘埋层的衬底的方法， 其特征在于， 所述绝缘埋层与覆盖层的材料为氧化硅， 所述腐蚀液为氢氟 酸。
15.根据权利要求 14所述的形成具有边缘倒角的带有绝缘埋层的衬底的方法， 其特征在于， 所述氢氟酸腐蚀溶液的质量浓度范围是 5%至 49%。
16.根据权利要求 14所述的形成具有边缘倒角的带有绝缘埋层的衬底的方法， 其特征在于， 所通入氢氟酸的流量范围为每分钟 500至 2500毫升。
17.—种形成具有边缘倒角的带有绝缘埋层的衬底的方法， 其特征在于， 包括 如下步骤：
提供带有绝缘埋层的衬底， 所述带半导体衬底包括支撑层、 绝缘埋层和顶 层半导体层；
在半导体衬底的正面和背面均形成覆盖层， 所述正面是顶层半导体层一恻 的表面， 背面是与正面相对的另一面；
将衬底正面的覆盖层研磨除去；
将衬底的正面向下放置于旋转腐蚀载片平台上， 将顶层半导体层的腐蚀液 通至衬底背面的覆盖层并同时旋转衬底， 使腐蚀液流通过衬底的边沿流淌 到正面， 腐蚀正面顶层半导体层的边缘部分；
将衬底的正面向上放置于旋转腐蚀载片平台上， 将绝缘埋层腐蚀液通至衬 底正面并同时旋转衬底， 腐蚀除去衬底边缘由于顶层半导体层被腐蚀除去 而露出的绝缘埋层。
18.根据权利要求 17所述的形成具有边缘倒角的带有绝缘埋层的衬底的方法， 其特征在于， 腐蚀顶层半导体层的步骤中， 旋转腐蚀的旋转速率范围是每 分钟 50至 1000圈。
19.根据权利要求 17或 18所述的形成具有边缘倒角的带有绝缘埋层的衬底的 方法， 其特征在于， 所述顶层半导体层的材料为硅， 腐蚀顶层半导体层的 腐蚀液为四甲基氢氧化铵。
20.根据权利要求 19所述的形成具有边缘倒角的带有绝缘埋层的衬底的方法， 其特征在于， 腐蚀顶层半导体层的步骤中， 四甲基氢氧化铵的质量浓度范 围是 5%至 50%， 流量范围是每分钟 0.5至 2.0升。
21.根据权利要求 17所述的形成具有边缘倒角的带有绝缘埋层的衬底的方法， 其特征在于，腐蚀绝缘埋层的步骤中，旋转腐蚀的旋转速率大于每分钟 500 圈。
22.根据权利要求 17或 21所述的腐蚀带有绝缘埋层的衬底边缘的方法， 其特 征在于， 所述绝缘埋层的材料为氧化硅， 腐蚀液绝缘埋层的腐蚀液为氢氟 酸。
23.根据权利要求 22所述的腐蚀带有绝缘埋层的衬底边缘的方法，其特征在于， 腐蚀绝缘埋层的步骤中， 氢氟酸的质量浓度范围是 5%至 49%,流量范围是 每分钟 0.5至 2.5升。
PCT/CN2010/075098 2009-07-10 2010-07-10 一种形成带有绝缘埋层的衬底的方法 WO2011003366A1 (zh)

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