WO2010141791A2 - Iterative interference cancellation receiver - Google Patents

Iterative interference cancellation receiver Download PDF

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Publication number
WO2010141791A2
WO2010141791A2 PCT/US2010/037343 US2010037343W WO2010141791A2 WO 2010141791 A2 WO2010141791 A2 WO 2010141791A2 US 2010037343 W US2010037343 W US 2010037343W WO 2010141791 A2 WO2010141791 A2 WO 2010141791A2
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WO
WIPO (PCT)
Prior art keywords
symbols
burst
weights
filter
interference suppression
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2010/037343
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English (en)
French (fr)
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WO2010141791A3 (en
Inventor
Divaydeep Sikri
Farrokh Abrishamkar
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Qualcomm Inc
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Qualcomm Inc
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Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Priority to CN201080030057.6A priority Critical patent/CN102461103B/zh
Priority to JP2012514164A priority patent/JP5512805B2/ja
Priority to EP10723892.5A priority patent/EP2438725B1/en
Priority to KR1020127000284A priority patent/KR101366009B1/ko
Publication of WO2010141791A2 publication Critical patent/WO2010141791A2/en
Publication of WO2010141791A3 publication Critical patent/WO2010141791A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0202—Channel estimation
    • H04L25/0224—Channel estimation using sounding signals
    • H04L25/0228—Channel estimation using sounding signals with direct estimation from sounding signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks

Definitions

  • the present invention relates to wireless communication and, in particular, relates to coherent single antenna interference cancellation.
  • a receiver's ability to properly decode a received signal depends upon the receiver's ability to maintain carrier synchronization. As wireless communications become ever more prevalent, however, increasing amounts of interference can negatively impact a receiver's ability to maintain this timing.
  • a method for suppressing interference in a wireless communication comprises the steps of receiving a burst of symbols, filtering the burst of symbols using an interference suppression filter with a first plurality of weights, decoding the filtered burst of symbols to generate data corresponding to the burst of symbols, encoding the data to generate a re-encoded burst of symbols, calculating a second plurality of weights for the interference suppression filter based upon the re-encoded burst of symbols, filtering the re-encoded burst of symbols using the interference suppression filter with the second plurality of weights, and decoding the filtered re-encoded burst of symbols.
  • a receiver comprises an antenna configured to receive a burst of symbols, an interference suppression filter configured to filter the burst of symbols with a first plurality of weights, a decoder configured to decode the filtered burst of symbols to generate data corresponding to the burst of symbols, an encoder configured to encode the data to generate a re-encoded burst of symbols, a processor configured to calculate a second plurality of weights for the interference suppression filter based upon the re-encoded burst of symbols, the interference suppression filter configured to filter the re-encoded burst of symbols with the second plurality of weights, and the decoder configured to decode the filtered re- encoded burst of symbols.
  • a receiver comprises means for receiving a burst of symbols, interference suppression means for filtering the burst of symbols with a first plurality of weights, decoding means for decoding the filtered burst of symbols to generate data corresponding to the burst of symbols, means for encoding the data to generate a re-encoded burst of symbols, means for calculating a second plurality of weights for the interference suppression means based upon the re- encoded burst of symbols, the interference suppression means for filtering the re- encoded burst of symbols with the second plurality of weights, and the decoding means for decoding the filtered re-encoded burst of symbols.
  • a machine-readable medium comprises instructions for suppressing interference in a wireless communication.
  • the instructions comprising code for receiving a burst of symbols, filtering the burst of symbols using an interference suppression filter with a first plurality of weights, decoding the filtered burst of symbols to generate data corresponding to the burst of symbols, encoding the data to generate a re-encoded burst of symbols, calculating a second plurality of weights for the interference suppression filter based upon the re-encoded burst of symbols, filtering the re-encoded burst of symbols using the interference suppression filter with the second plurality of weights, and decoding the filtered re-encoded burst of symbols.
  • FIG. 1 illustrates exemplary frame and burst formats in GSM in accordance with one aspect of the subject technology
  • FIG. 2 illustrates a receiver for use in a wireless communication system in accordance with one aspect of the subject technology
  • FIG. 3 illustrates a subset of symbols, including the first midamble symbol, that a receiver selects in accordance with one aspect of the subject technology
  • FIG. 4 illustrates a method for suppressing interference in accordance with one aspect of the subject technology
  • FIG. 5 illustrates a receiver for use in a wireless communication system in accordance with one aspect of the subject technology
  • FIG. 6 is a block diagram illustrating a computer system with which certain aspects of the subject technology may be implemented.
  • FIG. 1 shows exemplary frame and burst formats in GSM.
  • the timeline for downlink transmission is divided into multiframes.
  • each multiframe such as exemplary multiframe 101, includes 26 TDMA frames, which are labeled as TDMA frames 0 through 25.
  • the traffic channels are sent in TDMA frames 0 through 11 and TDMA frames 13 through 24 of each multiframe, as identified by the letter "T” in FIG. 1.
  • a control channel, identified by the letter "C,” is sent in TDMA frame 12.
  • No data is sent in the idle TDMA frame 25 (identified by the letter "I”), which is used by the wireless devices to make measurements for neighbor base stations.
  • Each TDMA frame such as exemplary TDMA frame 102, is further partitioned into eight time slots, which are labeled as time slots 0 through 7.
  • Each active wireless device/user is assigned one time slot index for the duration of a call.
  • User-specific data for each wireless device is sent in the time slot assigned to that wireless device and in TDMA frames used for the traffic channels.
  • Each burst such as exemplary burst 103, includes two tail fields, two data fields, a training sequence (or midamble) field, and a guard period (GP).
  • the number of bits in each field is shown inside the parentheses.
  • GSM defines eight different training sequences that may be sent in the training sequence field.
  • Each training sequence, such as midamble 104, contains 26 bits and is defined such that the first five bits are repeated and the second five bits are also repeated.
  • Each training sequence is also defined such that the correlation of that sequence with a 16-bit truncated version of that sequence is equal to (a) sixteen for a time shift of zero, (b) zero for time shifts of ⁇ 1, ⁇ 2, ⁇ 3, ⁇ 4, and ⁇ 5, and (3) a zero or non-zero value for all other time shifts.
  • FIG. 2 illustrates a receiver for use in a wireless communication system in accordance with one aspect of the subject technology.
  • Receiver 200 includes an antenna 210 configured to receive a wireless signal. While receiver 200 may be used in various communication systems, for clarity, receiver 200 is specifically described herein with respect to a GSM system.
  • the received signal is provided to a pre-processor 220 which demodulates the signal to generate received samples.
  • Pre-processor 220 may include a GMSK-to-BPSK rotator that performs phase rotation on the received samples.
  • Timing estimator 230 receives the samples from pre-processor 220 and makes several hypotheses regarding where a training sequence of symbols (i.e., midamble) begins in the burst of data, to provide several hypothetical channel estimates.
  • Interference suppressor 240 performs single antenna interference cancellation on each of the hypothesized channels, and midamble estimator 250 generates a midamble estimation error for each hypothesis.
  • Timing decision circuit 260 compares the midamble estimation errors for each hypothesis and selects the hypothesis with the lowest midamble estimation error.
  • timing decision circuit 260 represents the position in the burst of symbols where the midamble is estimated to begin.
  • the received samples are provided to interference suppressor 240, which re-calculates training weights based upon the entire burst of received samples and filters the entire burst.
  • the filtered signal is then provided to data processor 270, which decodes the received symbols based upon the selected timing hypothesis, and outputs the data corresponding to the received symbols.
  • the decoding process may employ any one of a number of error correction schemes known to those of skill in the art to reduce decoding errors and to provide accurate decoded data.
  • the decoded data is provided to an encoder 280, which re-encodes the data to provide a re-encoded burst of symbols, which are used by interference suppressor 240 to re-calculate training weights based upon the re-encoded burst of symbols and then filters the re-encoded burst of symbols using the re-calculated weights.
  • the filtered signal is then provided to data processor 270, which decodes the received symbols based upon the selected timing hypothesis, and outputs the data corresponding to the received symbols.
  • Accurate time synchronization may be achieved either non-coherently (e.g., through selection of the maximum correlation energy sum) or coherently, by performing interference suppression to provide an estimate of the symbols making up the training sequence, which can be compared against the previously-known symbols of that training sequence to determine an estimation error therefor.
  • window 105 has been illustrated as consisting of exactly 11 symbols, the scope of the present invention is not limited to such an arrangement. Rather, as will be readily apparent to one of skill in the art, any window size (up to the size of the entire data burst) may be selected.
  • the size of the search window may be chosen to be twice the size of the expected minimum propagation delay.
  • the search window size may be parameterized based on any other metric known to those of skill in the art.
  • interference suppressor 240 performs single antenna interference cancellation ("SAIC") on each estimated channel.
  • SAIC is a method by which oversampled and/or real/imaginary decomposition of a signal is used to provide virtual antennas with separate sample sequences, such that weights may be applied to the virtual antennas to form a beam in the direction of a desired transmitter and a beam null in the direction of an undesired interference source.
  • SAIC may be achieved with one or multiple actual antennas at the receiver by using space-time processing, where "space” may be virtually achieved with inphase and quadrature components, and "time” may be achieved using late and early samples.
  • s k is the midamble / quasi-midamble signal at time k
  • s_ k is a (t> + l)x l midamble / quasi-midamble vector
  • x k is a M x I received midamble / quasi- midamble vector
  • X k is a M x(l + l)xl vector of spatial temporal samples with a spatial length of
  • a spatial/temporal structured matrix can be constructed, such that
  • W SAlc -Z (4)
  • JF (L> + 1) X M (L + 1) and Z is equal to either s_ k ,( ⁇ + l)x (p - ⁇ ) or
  • the output of interference suppressor 240 is in the form S , where S represents an estimate of the midamble sequence.
  • S represents an estimate of the midamble sequence.
  • Equation 6 The difference between the estimated and known midamble sequences is determined according to Equation 6, below:
  • timing decision block 260 determines which hypothesis corresponds to the lowest estimation error e m , and the other hypothesized timing values are discarded.
  • the received samples are provided to interference suppressor 240, which re-calculates training weights based upon the entire burst of received samples and filters the entire burst.
  • the filtered signal is then provided to data processor 270, which decodes the received symbols based upon the selected timing hypothesis, and outputs the data corresponding to the received symbols.
  • the decoding process may employ any one of a number of error correction schemes known to those of skill in the art to reduce decoding errors and to provide accurate decoded data.
  • the decoded data is provided to an encoder 280, which re-encodes the data to provide a re-encoded burst of symbols, which are used by interference suppressor 240 to re-calculate training weights based upon the re-encoded burst of symbols and then filters the re-encoded burst of symbols using the re-calculated weights.
  • the filtered signal is then provided to data processor 270, which decodes the received symbols based upon the selected timing hypothesis, and outputs the data corresponding to the received symbols.
  • a Full Rate channel (e.g., TCH/FS, as defined in 3GPP standards), may have a packet size of 260 bits (e.g., 182 class 1 bits and 78 class 2 bits).
  • a message block of 456 bits is interleaved over 8 successive frames and then modulated, and transmitted.
  • the interference suppression filter used to filter the re-encoded burst of symbols may utilize a higher-order model than is used to filter the burst of symbols in the first iteration, as the reduction of signal noise accomplished by decoding (with error correction) the previously-filtered signal allows for a higher-order model (e.g., a model with increased temporal order L) with better curve fitting to be utilized.
  • a higher-order model e.g., a model with increased temporal order L
  • data processor 270 comprises a soft output generator that receives the signal from timing decision block 260 and generates soft decisions that indicate the confidence in the detected bits.
  • a soft output generator may implement an Ono algorithm, as is well known to those of skill in the art.
  • Data processor 270 may further comprise a de-interleaver that de-interleaves the soft decisions, and passes the soft decisions to a Viterbi decoder that decodes the deinterleaved soft decisions and outputs decoded data.
  • FIG. 4 is a flow chart illustrating a method for interference suppression in accordance with one aspect of the subject technology.
  • the method begins with step 401, in which a burst of symbols are received.
  • step 402 a plurality of timing hypotheses are generated for the burst of symbols.
  • step 403 the receiver calculates, for each timing hypothesis, a plurality of weights for an interference suppression filter based upon a subset of the burst of symbols.
  • the subset of the burst of symbols is filtered by the interference suppression filter with the corresponding first plurality of weights in step 404.
  • one of the plurality of timing hypotheses corresponding to a selection criteria is selected.
  • the selection criteria may be, for example, a midamble estimation error.
  • the burst of symbols are filtered using the interference suppression filter with the first plurality of weights.
  • the filtered burst of symbols are decoded to generate data corresponding to the burst of symbols.
  • the decoder may implement any one of a number of error correction procedures known to those of skill in the art.
  • the decoded data is re-encoded to generate a re-encoded burst of symbols, which are then iteratively processed in steps 409 to 411.
  • a second plurality of weights are calculated for the interference suppression filter in step 409, based upon the re-encoded burst of symbols.
  • the re-encoded burst of symbols are filtered using the interference suppression filter with the second plurality of weights.
  • the filtered re-encoded burst of symbols are decoded again.
  • FIG. 5 illustrates a receiver for use in a wireless communication system in accordance with one aspect of the subject technology.
  • Receiver 500 includes an antenna module 510 configured to receive a wireless signal such as, for example, an RF modulated GSM signal.
  • the received signal is provided to a pre -processor module 520 which demodulates the signal to generate received samples.
  • Pre-processor module 520 may also include a GMSK-to-BPSK rotator that performs phase rotation on the received samples.
  • Timing estimation module 530 receives the samples from pre-processing module 520 and makes several hypotheses regarding where a training sequence of symbols (midamble) begins in the burst of data, to provide several hypothetical channel estimates.
  • Interference suppression module 540 performs single antenna interference cancellation by calculating a plurality of filter weights for each hypothesis and then applying the filter, with the calculated weights, to each channel estimate hypothesis.
  • Midamble estimation module 550 generates a midamble estimation error for each hypothesis, and timing decision module 560 compares the midamble estimation errors for each hypothesis and selects the hypothesis with the lowest midamble estimation error. The selection of a hypothesis by timing decision module 560 represents the position in the burst of symbols where the midamble is estimated to begin.
  • the received samples are provided to interference suppressor module 540, which re-calculates training weights based upon the entire burst of received samples and filters the entire burst.
  • the interference suppression filter has been described as a single antenna interference cancellation filter, the scope of the present invention is not limited to such an embodiment. Rather, as will be apparent to those of skill in the art, the subject technology has application to systems with more than one antenna, which may perform, for example, dual antenna interference cancellation ("DAIC"), or any other multiple-antenna interference cancellation method, well known to those in the art.
  • DAIC dual antenna interference cancellation
  • FIG. 6 is a block diagram that illustrates a computer system 600 upon which an aspect may be implemented.
  • Computer system 600 includes a bus 602 or other communication mechanism for communicating information, and a processor 604 coupled with bus 602 for processing information.
  • Computer system 600 also includes a memory 606, such as a random access memory (“RAM”) or other dynamic storage device, coupled to bus 602 for storing information and instructions to be executed by processor 604.
  • Memory 606 may also be used for storing temporary variable or other intermediate information during execution of instructions to be executed by processor 604.
  • Computer system 600 further includes a data storage device 610, such as a magnetic disk or optical disk, coupled to bus 602 for storing information and instructions.
  • Computer system 600 may be coupled via I/O module 608 to a display device (not illustrated), such as a cathode ray tube ("CRT") or liquid crystal display (“LCD”) for displaying information to a computer user.
  • a display device such as a cathode ray tube ("CRT") or liquid crystal display (“LCD”)
  • An input device such as, for example, a keyboard or a mouse may also be coupled to computer system 600 via I/O module 608 for communicating information and command selections to processor 604.
  • I/O module 608 for communicating information and command selections to processor 604.
  • interference suppression is performed by a computer system 600 in response to processor 604 executing one or more sequences of one or more instructions contained in memory 606. Such instructions may be read into memory 606 from another machine-readable medium, such as data storage device 610.
  • main memory 606 causes processor 604 to perform the process steps described herein.
  • processors in a multi-processing arrangement may also be employed to execute the sequences of instructions contained in memory 606.
  • hard-wired circuitry may be used in place of or in combination with software instructions to implement various aspects. Thus, aspects are not limited to any specific combination of hardware circuitry and software.
  • machine-readable medium refers to any medium that participates in providing instructions to processor 604 for execution. Such a medium may take many forms, including, but not limited to, non-volatile media, volatile media, and transmission media.
  • Non-volatile media include, for example, optical or magnetic disks, such as data storage device 610.
  • Volatile media include dynamic memory, such as memory 606.
  • Transmission media include coaxial cables, copper wire, and fiber optics, including the wires that comprise bus 602. Transmission media can also take the form of acoustic or light waves, such as those generated during radio frequency and infrared data communications.
  • Machine -readable media include, for example, floppy disk, a flexible disk, hard disk, magnetic tape, any other magnetic medium, a CD-ROM, DVD, any other optical medium, punch cards, paper tape, any other physical medium with patterns of holes, a RAM, a PROM, an EPROM, a FLASH EPROM, any other memory chip or cartridge, a carrier wave, or any other medium from which a computer can read.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Noise Elimination (AREA)
  • Dc Digital Transmission (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
PCT/US2010/037343 2009-06-04 2010-06-04 Iterative interference cancellation receiver Ceased WO2010141791A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN201080030057.6A CN102461103B (zh) 2009-06-04 2010-06-04 迭代干扰消去接收机
JP2012514164A JP5512805B2 (ja) 2009-06-04 2010-06-04 繰り返し干渉キャンセル受信機
EP10723892.5A EP2438725B1 (en) 2009-06-04 2010-06-04 Iterative interference cancellation receiver
KR1020127000284A KR101366009B1 (ko) 2009-06-04 2010-06-04 수신기에 대한 반복적 간섭 제거

Applications Claiming Priority (2)

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US12/478,195 2009-06-04
US12/478,195 US8787509B2 (en) 2009-06-04 2009-06-04 Iterative interference cancellation receiver

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EP (1) EP2438725B1 (enExample)
JP (1) JP5512805B2 (enExample)
KR (1) KR101366009B1 (enExample)
CN (1) CN102461103B (enExample)
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