WO2010076956A2 - Procédé de compensation d'horloge de communication et données de communication - Google Patents

Procédé de compensation d'horloge de communication et données de communication Download PDF

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Publication number
WO2010076956A2
WO2010076956A2 PCT/KR2009/006017 KR2009006017W WO2010076956A2 WO 2010076956 A2 WO2010076956 A2 WO 2010076956A2 KR 2009006017 W KR2009006017 W KR 2009006017W WO 2010076956 A2 WO2010076956 A2 WO 2010076956A2
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WO
WIPO (PCT)
Prior art keywords
clock
data
communication
compensation method
falling edge
Prior art date
Application number
PCT/KR2009/006017
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English (en)
Korean (ko)
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WO2010076956A3 (fr
Inventor
공경식
Original Assignee
주식회사 테라칩스
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 주식회사 테라칩스 filed Critical 주식회사 테라칩스
Publication of WO2010076956A2 publication Critical patent/WO2010076956A2/fr
Publication of WO2010076956A3 publication Critical patent/WO2010076956A3/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

Definitions

  • the present invention relates to a method of compensating a communication clock or communication data, and more particularly, to a method of compensating a communication clock or communication data in a system that cannot synchronize data with a communication clock by a system clock.
  • FIG. 1 is a conceptual diagram illustrating a structure in which a plurality of systems are connected side by side to sequentially transmit a communication clock and data
  • FIG. 2 is a timing diagram illustrating a waveform relationship between a clock and data in FIG. 1.
  • each system receives the clock and data from the previous system through the clock input port (sclki) and data input port (sdati), respectively, respectively, the clock output port (sclko) and The clock and data are output to the next system through the data output port (sdato).
  • the delay time when switching from 0 to 1 is greater than the delay time when switching from 1 to 0 due to the output port characteristics of each system 100A, 100B, 100C, and 100D, as shown in FIG.
  • the one-man section of the clock gradually decreases and eventually the one-man section disappears.
  • the delay time when switching from 0 to 1 is less than the delay time when switching from 1 to 0, the interval of 1 of the clock gradually increases, and thus the interval of 0 is lost.
  • each clock assumes a period of one clock as 100% and a delay time when switching from 0 to 1 is 20% and a delay time when switching from 1 to 0 is 10%.
  • the waveform relationship between the lines 110A, 110B, 110C, and 110D and the data lines 120A, 120B, 120C, and 120D is shown.
  • the pulse width gradually decreases from the first 50% to 40%, 30% and 20%.
  • the clock and data input from the previous system must be transmitted to the next system without change.
  • One way to compensate for the clock and data is to use a very fast clock inside the system to transfer the clock input from the previous system to the next system.
  • this has made it difficult to make very fast clocks without being affected by factors such as ambient temperature or voltage applied to the system.
  • the present invention is to solve the above problems, in the system that can not synchronize the communication clock and data with the system clock, the clock or data input from the previous system to compensate for the pulse width, phase, delay time, etc. It is an object of the present invention to provide a method of compensating communication clock or communication data, which can be output by using the same method.
  • a communication clock compensation method has a structure in which a plurality of systems are connected side by side to sequentially transmit a communication clock and data, thereby inverting a clock input from a previous system.
  • the output is as follows.
  • the method of compensating communication data according to the present invention has a structure in which a plurality of systems are connected side by side to sequentially transmit a communication clock and data, and when the system receives data at the falling edge of the clock, The data received from the previous system is output to the next system at the falling edge of the input clock or the rising edge of the clock compensated by the compensation method.
  • the method of compensating communication data according to the present invention has a structure in which a plurality of systems are connected side by side to sequentially transmit a communication clock and data.
  • the data received from the previous system is output to the next system at the rising edge of the input clock or the falling edge of the clock compensated by the compensation method.
  • the clock received from the previous system is inverted and outputted to the next system, and the data received from the previous system is outputted to the next system using the inputted clock to compensate for the clock and data, thereby effectively synchronizing them.
  • FIG. 1 is a conceptual diagram illustrating a structure in which a plurality of systems are connected side by side to sequentially transmit a communication clock and data.
  • FIG. 2 is a timing chart showing waveform relationships between clock and data in FIG. 1;
  • 3 and 4 are exemplary embodiments of a system for receiving data at a falling edge of a clock according to the present invention.
  • 5 and 6 are exemplary embodiments of a system for receiving data at a rising edge of a clock according to the present invention.
  • FIG. 7 is a timing diagram showing a waveform relationship between a clock and data when the present invention is applied as a system receiving data at the falling edge of the clock.
  • FIGS. 3 and 4 are examples of a system for receiving data on the falling edge of the clock according to the present invention
  • FIGS. 5 and 6 are examples of a system for receiving data on the rising edge of the clock according to the present invention.
  • FIG. 7 is a system in which data is input at the falling edge of the clock, and is a timing diagram showing the waveform relationship between the clock and data when the present invention is applied.
  • the compensation method of a communication clock is a structure in which a plurality of systems are connected side by side to sequentially transmit a communication clock and data, and inverts a clock input from a previous system to output the next system.
  • the pulse width of the clock is reduced in any system, then the pulse width of the clock is increased again by that amount in the next system.
  • the pulse width of the clock in any system increases, then the pulse width of the clock in the next system again decreases by that amount.
  • the pulse width of the clock will always be the same as before as it passes through the two systems.
  • the method of compensating communication data according to the present invention has a structure in which a plurality of systems are connected side by side so as to sequentially transmit a communication clock and data, and is compensated for data received from a previous system and received to transmit to a next system. Use the clock.
  • the clock input from the previous system is inverted by the action of the flip-flop 10 and the inverter 20.
  • the data input from the previous system may be output to the next system at the falling edge of the input clock or the rising edge of the clock compensated by the compensation method while outputting to the next system. Then, there is always a margin as long as 1 section of the compensated clock.
  • the clock input from the previous system is inverted by the action of the flip-flop 10 and the inverter 20.
  • the data received from the previous system may be output to the next system at the rising edge of the clock received while the output to the next system or the falling edge of the clock compensated by the compensation method. Then there will always be a margin as long as the interval is zero of the compensated clock.
  • the first clock line is assuming that the period of one clock is 100% and the delay time when switching from 0 to 1 is 20% and the delay time when switching from 1 to 0 is 10%.
  • the one-man section of 110A is 50% but the one-man section of the second clock line 110B is reduced to 40%.
  • the section 1 of the third clock line 110C has 50% again.
  • the first section of the fourth clock line 110D is reduced to 40% again, but the first section of the fourth clock line 110D recovers to 50%.
  • the received data is output again on the falling edge of the input clock or on the rising edge of the clock compensated by the compensation method.
  • There is a spare section by one section so that the first data line 120A has 50% until the falling edge of the clock after data change, and the second data line 120B has 40% until the falling edge of the clock after data change.
  • the first data line 120C there is a 50% margin until the falling edge of the clock after the change of data
  • the fourth data line 120D there is a 40% spare period until the falling edge of the clock after the change of data.
  • the pulse width is reduced.
  • the reduced pulse width at will return to normal as it passes through the next system.
  • the data received from the previous system is always synchronized because the data received from the previous system is output to the next system.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

L'invention concerne un procédé de compensation d' horloge de communication qui inverse une horloge provenant d'un système précédent et délivre l'horloge inversée à un système suivant dans une structure dans laquelle plusieurs systèmes sont connectés en parallèle pour transmettre séquentiellement des données et une horloge de communication. L'invention concerne également un procédé de compensation de données de communication. En relation avec la structure, le procédé de compensation de données de communication délivre les données du système précédent au système suivant pendant le front descendant de l'horloge reçue ou le front montant de l'horloge compensée au moyen du procédé de compensation d'horloge de communication dans un système qui reçoit des données pendant le front montant de l'horloge. En outre, le procédé de compensation d'horloge de communication délivre les données provenant du système précédent au système suivant pendant le front montant de l'horloge reçue ou le front descendant de l'horloge compensée au moyen du procédé de compensation d'horloge de communication dans un système qui reçoit des données pendant le front descendant de l'horloge.
PCT/KR2009/006017 2008-11-12 2009-10-19 Procédé de compensation d'horloge de communication et données de communication WO2010076956A2 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR20080112016 2008-11-12
KR10-2008-0112016 2008-11-12
KR1020090000112A KR20100053401A (ko) 2008-11-12 2009-01-02 통신 클럭 또는 통신 데이터의 보상방법
KR10-2009-0000112 2009-01-02

Publications (2)

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WO2010076956A2 true WO2010076956A2 (fr) 2010-07-08
WO2010076956A3 WO2010076956A3 (fr) 2010-08-19

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000025299A (ko) * 1998-10-09 2000-05-06 김영환 케스케이드 버스 시스템의 피드백 경로 클록 동기화장치
KR100321981B1 (ko) * 1999-05-12 2002-02-04 윤종용 클럭지연 보상장치
KR20030046686A (ko) * 2001-12-06 2003-06-18 삼성전자주식회사 이동 통신 시스템에서 망동기 클럭을 생성하기 위한 클럭생성 장치
JP2004086905A (ja) * 2002-08-28 2004-03-18 Samsung Electronics Co Ltd データ検出回路及びデータ検出方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000025299A (ko) * 1998-10-09 2000-05-06 김영환 케스케이드 버스 시스템의 피드백 경로 클록 동기화장치
KR100321981B1 (ko) * 1999-05-12 2002-02-04 윤종용 클럭지연 보상장치
KR20030046686A (ko) * 2001-12-06 2003-06-18 삼성전자주식회사 이동 통신 시스템에서 망동기 클럭을 생성하기 위한 클럭생성 장치
JP2004086905A (ja) * 2002-08-28 2004-03-18 Samsung Electronics Co Ltd データ検出回路及びデータ検出方法

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KR20100053401A (ko) 2010-05-20
WO2010076956A3 (fr) 2010-08-19

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