KR20100053401A - 통신 클럭 또는 통신 데이터의 보상방법 - Google Patents

통신 클럭 또는 통신 데이터의 보상방법 Download PDF

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Publication number
KR20100053401A
KR20100053401A KR1020090000112A KR20090000112A KR20100053401A KR 20100053401 A KR20100053401 A KR 20100053401A KR 1020090000112 A KR1020090000112 A KR 1020090000112A KR 20090000112 A KR20090000112 A KR 20090000112A KR 20100053401 A KR20100053401 A KR 20100053401A
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KR
South Korea
Prior art keywords
clock
data
communication
falling edge
previous
Prior art date
Application number
KR1020090000112A
Other languages
English (en)
Korean (ko)
Inventor
공경식
Original Assignee
주식회사 테라칩스
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 테라칩스 filed Critical 주식회사 테라칩스
Priority to PCT/KR2009/006017 priority Critical patent/WO2010076956A2/fr
Publication of KR20100053401A publication Critical patent/KR20100053401A/ko

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
KR1020090000112A 2008-11-12 2009-01-02 통신 클럭 또는 통신 데이터의 보상방법 KR20100053401A (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/KR2009/006017 WO2010076956A2 (fr) 2008-11-12 2009-10-19 Procédé de compensation d'horloge de communication et données de communication

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020080112016 2008-11-12
KR20080112016 2008-11-12

Publications (1)

Publication Number Publication Date
KR20100053401A true KR20100053401A (ko) 2010-05-20

Family

ID=42278530

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020090000112A KR20100053401A (ko) 2008-11-12 2009-01-02 통신 클럭 또는 통신 데이터의 보상방법

Country Status (2)

Country Link
KR (1) KR20100053401A (fr)
WO (1) WO2010076956A2 (fr)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000025299A (ko) * 1998-10-09 2000-05-06 김영환 케스케이드 버스 시스템의 피드백 경로 클록 동기화장치
KR100321981B1 (ko) * 1999-05-12 2002-02-04 윤종용 클럭지연 보상장치
KR20030046686A (ko) * 2001-12-06 2003-06-18 삼성전자주식회사 이동 통신 시스템에서 망동기 클럭을 생성하기 위한 클럭생성 장치
KR100486255B1 (ko) * 2002-08-28 2005-05-03 삼성전자주식회사 데이터 검출회로 및 데이터 검출 방법

Also Published As

Publication number Publication date
WO2010076956A3 (fr) 2010-08-19
WO2010076956A2 (fr) 2010-07-08

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E902 Notification of reason for refusal
E601 Decision to refuse application