WO2010070771A1 - Carte de circuit imprimé multicouche et son procédé de fabrication - Google Patents

Carte de circuit imprimé multicouche et son procédé de fabrication Download PDF

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Publication number
WO2010070771A1
WO2010070771A1 PCT/JP2008/073243 JP2008073243W WO2010070771A1 WO 2010070771 A1 WO2010070771 A1 WO 2010070771A1 JP 2008073243 W JP2008073243 W JP 2008073243W WO 2010070771 A1 WO2010070771 A1 WO 2010070771A1
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WIPO (PCT)
Prior art keywords
conductive
hole
conductor
multilayer printed
resin films
Prior art date
Application number
PCT/JP2008/073243
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English (en)
Japanese (ja)
Inventor
悟 座間
賢一 大賀
Original Assignee
古河電気工業株式会社
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Publication date
Application filed by 古河電気工業株式会社 filed Critical 古河電気工業株式会社
Priority to KR1020117016658A priority Critical patent/KR101489034B1/ko
Priority to PCT/JP2008/073243 priority patent/WO2010070771A1/fr
Priority to CN2008801323987A priority patent/CN102257887B/zh
Publication of WO2010070771A1 publication Critical patent/WO2010070771A1/fr

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/462—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar double-sided circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/361—Assembling flexible printed circuits with other printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/04—Assemblies of printed circuits
    • H05K2201/041—Stacked PCBs, i.e. having neither an empty space nor mounted components in between
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/05—Flexible printed circuits [FPCs]
    • H05K2201/058—Direct connection between two or more FPCs or between flexible parts of rigid PCBs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09109—Locally detached layers, e.g. in multilayer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10666—Plated through-hole for surface mounting on PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/0455—PTH for surface mount device [SMD], e.g. wherein solder flows through the PTH during mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/281—Applying non-metallic protective coatings by means of a preformed insulating foil
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards

Definitions

  • the present invention relates to a multilayer printed circuit board and a method for manufacturing the same.
  • Patent Document 1 Conventionally, as a method for producing a multilayer printed board, for example, there are methods for producing a multilayer board disclosed in Patent Document 1, Patent Document 2, and the like.
  • Patent Document 1 a plurality of double-sided substrates with interlayer connection are manufactured, and the plurality of double-sided substrates are stacked via a film-like insulator that has been processed to allow interlayer connection, thereby having electrodes on both sides of the substrate.
  • a method of manufacturing a multilayer substrate is disclosed.
  • Patent Document 2 a single-sided conductor pattern film in which a conductor pattern is formed only on one side of a resin film is laminated, and the multilayer film having electrodes on both sides is manufactured by removing the resin film so that the electrodes are exposed.
  • a method is disclosed. Further, in Patent Document 2, except for a single-sided conductor pattern film forming the surface of a multilayer substrate, a bottomed via hole having a conductive pattern as a bottom surface is formed in the single-sided conductor pattern film, and a conductive paste is placed in the bottomed via hole. The technique of making the conductor pattern of adjacent single-sided conductor pattern films conductive through this conductive paste by filling is disclosed. According to this, each conductive pattern layer of the multilayer substrate can be made conductive by the conductive paste in the via hole. JP 2000-38464 A (Patent No. 3355142) JP 2003-86948 A (Patent No. 3407737)
  • the present invention has been made in view of such conventional problems, and an object of the present invention is to reduce the number of parts to reduce the manufacturing cost, and to provide a multilayer printed board having high interlayer connection reliability and the manufacturing thereof. It is to provide a method.
  • a multilayer printed board according to the invention described in claim 1 is formed integrally with the conductor pattern on a through hole, a conductor pattern formed on one side, and an inner wall of the through hole.
  • a plurality of resin films each having a conductive through hole are stacked in the same vertical direction, and the conductive pattern and the conductive through hole facing each other between two adjacent resin films of the plurality of resin films.
  • Each of the conductors provided between the two land portions is bonded to the metal.
  • a plurality of resin films having a conductor pattern and a conductive through hole formed on one side are overlapped in the same vertical direction, and between two adjacent resin films among the plurality of resin films.
  • the conductor is metal-to-metal coupled with the opposing conductor pattern and conductive through hole.
  • the opposing conductor pattern and the conductive through hole are electrically connected by the conductor and mechanically coupled.
  • the interlayer connection between the conductive patterns of each resin film can be integrated with the conductive pattern without interposing another resin film between two adjacent resin films. This is done through a through hole and a conductor. Therefore, the number of parts can be reduced to reduce the manufacturing cost, and the interlayer connection reliability is high.
  • the conductive pattern and the conductive through-hole have a two-layer structure having a base metal layer and a conductive layer, the adhesiveness between the conductive layer and the resin film is improved. Further improve.
  • the base metal layer is formed of a Ni—P alloy having a P of 2 to 6% and a thickness of 0.05 microns, and the conductor layer is made of Cu. It is formed.
  • the multilayer printed board according to the invention described in claim 4 is characterized in that the conductor is a metal containing Sn.
  • the multilayer printed board according to the invention described in claim 5 is characterized in that the resin film is a thermoplastic resin having a glass transition point and a melting point of 150 ° C. or higher and 350 ° C. or lower.
  • the multilayer printed circuit board according to the invention of claim 6 is characterized in that the resin film is a film in which crystals have optical anisotropy.
  • the multilayer printed circuit board according to the invention of claim 7 is characterized in that the resin film is made of a polyaryl ketone resin and an amorphous polyetherimide.
  • a method for manufacturing a multilayer printed board includes a through hole, a conductor pattern formed on one side, and the conductor pattern integrally formed on an inner wall of the through hole.
  • the plating layers containing Sn are interposed between the conductive pattern and the conductive through-holes, which are arranged in the same vertical direction and face each other between the two adjacent resin films.
  • a plurality of resin films having a conductor pattern and a conductive through hole formed on one side are overlapped in the same vertical direction, and between two adjacent resin films among the plurality of resin films.
  • a conductor formed by melting a plating layer containing Sn by a heat fusion press is metal-to-metal bonded to the opposing conductor pattern and the land portion of the conductive through hole.
  • the opposing conductor pattern and the land portion of the conductive through hole are electrically connected by the conductor and mechanically coupled.
  • a manufacturing method of a multilayer printed circuit board according to an invention described in claim 9 includes a through hole, a conductor pattern formed on one side, and an integral part of the conductor pattern on an inner wall of the through hole.
  • a step of producing resin films each having a formed conductive through hole; and a plurality of the resin films having the same vertical direction, and the conductive pattern facing the two adjacent resin films and the conductive pattern And stacking the conductive paste or metal powder with the conductive paste or the metal powder interposed between the land portions of the conductive through-holes, and stacking a plurality of stacked layers of the resin films by a heat fusion press.
  • a plurality of resin films having a conductor pattern and a conductive through hole formed on one side are overlapped in the same vertical direction, and between two adjacent resin films among the plurality of resin films.
  • the conductor formed by curing the conductive paste metalizes the opposing conductor pattern and conductive through hole.
  • the opposing conductor pattern and the conductive through hole are electrically connected by the conductor and mechanically coupled.
  • the interlayer connection between the conductive patterns of each resin film can be integrated with the conductive pattern without interposing another resin film between two adjacent resin films. This is done through a through hole and a conductor. Therefore, the number of parts can be reduced to reduce the manufacturing cost, and the interlayer connection reliability is high.
  • a base metal layer is formed by electroless plating on one side of the resin film and the inner wall of the through hole, A conductive layer is formed on the underlying metal layer by electroplating, and then the conductive pattern is formed on the conductive layer.
  • the conductor of the conductor pattern and the conductive through hole have a two-layer structure having the base metal layer and the conductor layer, thereby improving the adhesion of the conductor layer.
  • the interlayer connection reliability is further improved.
  • the base metal layer is formed by electroless plating, the conductor thickness of the conductor pattern and the conductive through hole can be reduced. Thereby, a fine conductor pattern can be formed.
  • the conductor pattern is formed after the copper foil is fusion-pressed to the film, so the thickness of the copper foil is limited, and the fine processing Not suitable.
  • the connection reliability is high and the conductor thickness of the conductive pattern and the conductive through hole is uniform.
  • the method for manufacturing a multilayer printed board according to the invention of claim 11 is characterized in that the conductive paste is made of metal powder containing at least Sn, Cu, and Ag.
  • the present invention it is possible to reduce the number of components and reduce the manufacturing cost, and it is possible to obtain a multilayer printed board having high interlayer connection reliability.
  • FIG. 3 is a cross-sectional view illustrating a schematic configuration of a part of the multilayer printed board according to the first embodiment.
  • or (D) is process drawing which shows the preparation procedures of a resin film.
  • or (D) is process drawing which shows the preparation procedures of a resin film.
  • FIG. 1 is a cross-sectional view showing a schematic configuration of a part of the multilayer printed board according to the first embodiment
  • FIG. 2 is an enlarged partial cross-sectional view of a part of FIG.
  • the multilayer printed board 10 shown in FIG. 1 is formed as a three-layer multilayer printed board as an example.
  • the multilayer printed board 10 includes resin films 15A and 15B each having a through hole 11, a conductor pattern 12 formed on one side, and a conductive through hole 14 formed integrally with the conductor pattern 12 on the inner wall of the through hole 11. , 15C are stacked in the same vertical direction.
  • three resin films 15A, 15B, and 15C having the same shape are overlapped. These three resin films 15A, 15B, and 15C are overlaid so that the centers of the conductive through holes 14 coincide.
  • the conductive through holes 14 of the resin films 15A, 15B, and 15C are bent from the inner wall of the through hole 11 to the surface opposite to the surface on which the conductor pattern 12 is formed.
  • Each has an extended land 14a (see FIG. 3D).
  • the opposing conductor pattern 12 and the conductive through Conductors 23 that are metal-to-metal bonded to the land portions 14a of the holes 14 are provided.
  • the conductor 23 is plated with Sn (Sn plating) on the land portion 14a of the conductive through-hole 14 to form a Sn plating layer 23A (see FIG. 3E).
  • Sn plating Sn plating
  • the Sn plating layer 23A is melted after pressing.
  • the conductive pattern 12 and the land portion 14a of the conductive through hole 14 facing each other between the two adjacent resin films 15A and 15B and between the resin films 15B and 15C are electrically connected via the conductor 23. Mechanically coupled.
  • the multilayer printed board 10 includes a resist film 41 that covers the entire conductor pattern 12 of one of the resin films 15A and 15C (resin film 15C) on both sides thereof, and a land of the conductive through hole 14 on the other side (resin film 15A). And a resist film 42 covering the whole 14a.
  • the resist film 41 is formed with a through hole 41a for exposing a part of the conductor pattern 12 (a portion serving as an electrode).
  • a through hole 42 a for exposing the land 14 a of the conductive through hole 14 is formed in the resist film 42.
  • each resin film 15A, 15B, 15C are formed in one conductor 13.
  • the conductor 13 has a base metal layer 13a and a conductor layer 13b formed on the base metal layer 13a.
  • the conductor pattern 12 is formed on the conductor layer 13b on one side of each resin film 15A, 15B, 15C.
  • the resin films 15A, 15B, 15C and the resist films 41, 42 are made of, for example, the same film base material.
  • a general glass cloth base epoxy resin or BT resin may be used, but it is more convenient to use a thermoplastic resin for the film base from the viewpoint of joining a plurality of sheets by a fusion press. It is.
  • the thermoplastic film include a liquid crystal polymer film, PEEK (Polyetheretherketone), PES (Polyethersulfone), PPE (Polyphenyeneether), PTFE (Polytetrafluoroethylene) and the like.
  • Thermoplastic polyimide may also be used.
  • the multilayer printed circuit board 10 having the above configuration is integrated by a heat fusion press in a state where the resin films 15A, 15B, and 15C and the resist films 41 and 42 are stacked as shown in FIG.
  • Sn in the Sn plating layer 23A is melted to form the conductor 23 which is metal-to-metal bonded to the conductor pattern 12 and the land 14a of the conductive through hole 14.
  • another conductive film is not interposed between two adjacent resin films of the resin films 15A, 15B, and 15C, and the conductive patterns 12 of the respective resin films are interposed.
  • the interlayer connection is made through the conductive through hole 14 and the conductor 23 integral with the conductor pattern 12.
  • FIG. 3 is a process diagram showing the production procedure of the resin film
  • FIG. 4 is an explanatory diagram showing the arrangement order of the respective constituent members before the heat fusion press.
  • resin films 15 ⁇ / b> A, 15 ⁇ / b> B, 15 ⁇ / b> C each having a through hole 11, a conductive pattern 12 formed on one side, and a conductive through hole 14 formed integrally with the conductive pattern 12 on the inner wall of the through hole 11.
  • the process of producing is implemented. Since these resin films 15A, 15B, and 15C have the same configuration, here, a process of manufacturing the resin film 15A will be described.
  • a through hole 11 is formed in the resin film 15A shown in FIG. 3A by drilling (see FIG. 3B).
  • a conductor 13 (having a base metal layer 13a and a conductor layer 13b formed on the base metal layer 13a on both surfaces of the resin film 15A and the inner wall of the through-hole 11). 2).
  • the base metal layer 13a is formed by electroless plating.
  • the conductor layer 13b is formed by electroplating.
  • the conductor pattern 12 is formed by photoetching or the like on the conductor layer 13b (see FIG. 2) of the conductor 13 on one side of the resin film 15A among the conductors 13 (see FIG. 3D). Further, the conductor on the surface opposite to the conductor pattern 12 of the resin film 15A is removed by etching or the like leaving the land 14a of the conductive through hole 14.
  • Sn plating (Sn electroplating) is performed on the conductive through holes 14 and the land portions 14a of the resin films 15B and 15C to form the Sn plating layer 23A. (See FIG. 3E).
  • Sn electroplating solution 1st tin sulfate 40g / L Sulfuric acid 100mL / L Additive Lonastan EC-J Temperature 20 ° C Current density 2A / dm 2
  • Sn—Cu alloy plating plating bath: Top Freed BR manufactured by Okuno Pharmaceutical Co., Ltd.
  • Sn-Ag alloy plating may be used.
  • the Sn plating method is not limited to electroplating, and displacement plating may be used.
  • the conductive patterns on both sides were removed by etching, and then immersed in the following plating solution (any of three types) to replace the copper surface to form Sn with a thickness of 2 microns.
  • the resin films 15A, 15B, and 15C are stacked in the same vertical direction as shown in FIG. 4, and the resist film 41 is placed on the resin film 15C, and the resist film 42 is placed under the resin film 15A.
  • a process of stacking the stacked layers and stacking the stacked layers by a heat fusion press is performed.
  • the conductive paste 23A provided between each conductor pattern 12 and both end portions 25a of the conductive through hole 25 is cured, and the conductive pattern 12 and the end portions 14a of the conductive through hole 14 are connected to the metal.
  • the multilayer printed circuit board 10 shown in FIG. 1 is completed.
  • the Sn plating layer 23A provided between each conductor pattern 12 and the land portion 14a of the conductive through hole 14 is melted by the heat fusion press, and is bonded to the conductor pattern 12 and the land portion 14a of the conductive through hole between the metals.
  • the conductor (metal containing Sn) 23 is formed.
  • heat may be applied again to the Sn melting point or higher to melt the Sn to form a metal-bonded conductor.
  • the conductive through holes 14 of the resin films 15A, 15B, and 15C are coaxial.
  • the conductive through holes 14 do not necessarily have to be coaxial.
  • the conductor pattern 12 and the land portion 25a of the conductive through hole 25 of the resin film 22 may be bonded to each other by the conductor 23 between two adjacent resin films.
  • a resin film 15A, 15B, 15C (a plurality of resin films) having a conductor pattern 12 and a conductive through hole 14 formed on one side is overlapped with each other in two adjacent resin films.
  • the conductor 23 is metal-to-metal bonded to the opposing conductor pattern 12 and the land portion 14a of the conductive through hole 14.
  • the conductor 23 is obtained by melting Sn of the Sn plating layer 23A at the time of heat fusion pressing or after pressing. Thereby, between the two adjacent resin films, the opposing conductor pattern 12 and the conductive through hole 14 are electrically connected by the conductor 23 and mechanically coupled.
  • the interlayer connection between the conductive patterns of each resin film is integrated with the conductive pattern 12 without interposing another resin film between two adjacent resin films.
  • the conductive through hole 14 and the conductor 23 are used. Accordingly, it is possible to reduce the number of parts and reduce the manufacturing cost, and it is possible to obtain a multilayer printed board having high interlayer connection reliability.
  • Adhesiveness between the conductor layer 13b and the resin film is improved by forming a single conductor 13 in which the conductor pattern 12 and the conductive through hole 14 are formed into a two-layer structure having a base metal layer 13a and a conductor layer 13b. Therefore, the interlayer connection reliability is further improved.
  • the base metal layer 13a is formed by electroless plating, the conductor thickness of the conductor pattern 12 and the conductive through hole 14 can be reduced. Thereby, the fine conductor pattern 12 can be formed.
  • the conductor 23 that is metal-to-metal bonded to the conductor pattern 12 and the conductive through hole 14 is obtained by melting Sn of the Sn plating layer 23A.
  • the conductor 33 (see FIG. 5) bonded to the conductor pattern 12 and the conductive through-hole 14 between the metals is electrically conductive paste 33A (FIG. 6E). ) And FIG. 7) are cured. Thereby, the conductive pattern 12 and the conductive through hole 14 facing each other between two adjacent resin films, that is, between the resin films 15A and 15B and between the resin films 15B and 15C are electrically connected via the conductor 33. And mechanically coupled.
  • this multilayer printed circuit board 10A the conductive through hole 14 formed in the inner wall of the conductive through hole 11 in the resin film 15 (15A, 15B, 15C) and the conductive through hole 25 in the conductor 33 and the resin film 22 are formed. Used for interlayer connection.
  • the other configuration of the multilayer printed board 10A is the same as that of the multilayer printed board 10 of the first embodiment.
  • FIG. 6 is a process diagram showing the procedure for producing the resin film
  • FIG. 7 is an explanatory diagram showing the arrangement order of the constituent members before the heat fusion press.
  • the conductive paste 33A is interposed between the conductor pattern 12 and both land portions 25a of the second conductive through hole 25 (see FIG. 7E).
  • the conductive paste 33 ⁇ / b> A is applied on both land portions 25 a of the second conductive through holes 25.
  • the resist film 42, the first resin film 15, the second resin film 22, and the resist film 41 are stacked in the order shown in FIG. Thereby, the multilayer printed circuit board 10A shown in FIG. 1 is completed.
  • the conductive paste 33A provided between each conductor pattern 12 and both land portions 25a of the second conductive through hole 25 is cured by the heat fusion press, and both the conductive pattern 12 and the second conductive through hole 25 are cured.
  • the land portion 25a and the conductor 33 are metal-bonded.
  • Example 1 Method for Manufacturing Multilayer Printed Circuit Board 10 or 10A> Sn plating was performed on the land portion 14 a and the inner wall of the conductive through hole 14. In the Sn plating, an Sn plating layer 23A having a thickness of 1 micron was formed.
  • the pressing temperature was in the range of 150 to 350 ° C., and the pressing pressure was in the range of 0.5 to 10 MPa.
  • Example 1 shown in Table 1 below Sn plated on the land portion 14a is melted by a 1 MPa press at 280 ° C., and the conductive through hole is bonded between the conductor pattern and the metal to establish electrical connection. It was.
  • Example 2 a liquid crystal polymer film (BIAC (registered trademark) BC manufactured by Japan Gore-Tex Co., Ltd.) having a thickness of 50 ⁇ m was used as the film substrate.
  • BIAC registered trademark
  • Example 3 PEEK / PEI (IBUKI (registered trademark) manufactured by Mitsubishi Plastics, Inc.) having a thickness of 50 ⁇ m was used as a film substrate.
  • the press pressure and the press temperature were heat-sealed under the conditions shown in Table 1.
  • Examples 4 to 6 multilayer substrates were produced using the resin films and press conditions shown in Table 1.
  • Ag paste was used for the connection between the conductive through hole of the second film and the conductor pattern of the first resin film.
  • the conductive paste 33A is applied by screen printing, and the conductive paste 33A is cured by a heat fusion press, and the conductor 33 (see FIG. 6) in which each conductive paste 33A is cured becomes a conductive pattern and a second conductive through. Bonded between hole and metal.
  • As the conductive paste 33A Dotite XA-824 made by Fujikura Kasei was used as the Ag paste.
  • the pressing conditions are shown in Table 1.
  • Examples 7 to 9 multilayer substrates were produced using the resin films and press conditions shown in Table 1.
  • An AgSn paste was used for connection between the conductive through hole of the second film and the conductor pattern of the first resin film.
  • the one described in paragraph 0075 of Japanese Patent No. 3473601 was used.
  • a multilayer substrate was produced in the same manner as in Examples 4-6.
  • a through hole 11 was formed by a carbon dioxide laser.
  • the through-hole 11 may be not only a carbon dioxide laser but also a UV-YAG laser or an excimer laser with a small diameter. Moreover, you may process the through hole 11 with a mechanical drill.
  • Film roughening / desmear The drilled first resin film 15 was immersed in a strong alkali to dissolve the surface and roughen it.
  • the surface was dipped in a 10 N potassium hydroxide solution at 80 ° C. for 15 to 30 minutes to form irregularities on the surface.
  • the resin smear generated during the formation of the through hole 11 was dissolved and removed, and the inner wall surface of the through hole 11 was also roughened.
  • the surface of the resin film 15 was plated with Ni—P as a base plating (base metal layer 13a) by electroless plating.
  • a film metal-clad laminate was manufactured by sequentially performing a conditioner treatment, a nickel-phosphorous alloy electroless plating treatment, a heat treatment, and a copper electroplating treatment.
  • Electroless plating In the conditioner treatment, the surface of the polymer film was washed with an OPC-350 conditioner manufactured by Okuno Pharmaceutical Co., Ltd.
  • an OPC-80 catalyst manufactured by Okuno Pharmaceutical Co., Ltd. was used as a catalyst-providing liquid containing palladium, and an OPC-500 accelerator was used as an activator.
  • nickel (P) -phosphorus (P) plating was performed on both surfaces of the first resin film 15.
  • a commercially available nickel-phosphorous plating solution was selected as one having a phosphorus concentration of 5% or less.
  • a nickel nickel thickness of 0.2 microns was formed using chemical nickel EXC manufactured by Okuno Pharmaceutical Co., Ltd.
  • the plating solution is not limited to this, and Enplate Ni-426 of Meldex Co., Ltd., Top Nicolon LPH-LF of Okuno Pharmaceutical Co., Ltd., etc. may be used.
  • heat treatment may be performed. Heating was performed at a temperature of 230 to 250 ° C. for 30 seconds to 30 minutes. In this example, heating was performed at 240 ° C. for 3 minutes.
  • Copper electroplating Further, copper electroplating was performed to form a conductor layer 13b of the conductor 13 with a thickness of 1 to 10 microns. In the electroplating process of copper (Cu), copper was formed so that the conductor thickness of the conductor layer 13b was 5 microns. The following copper electroplating solution was used. As an additive, Cubelite TH-RIII manufactured by Sugawara Eugleite Co., Ltd. was used.
  • conductor pattern 12 formed a circuit on both surfaces (the conductor layer 13b of the conductor 13) of the first resin film 15 by a subtractive method. A photosensitive resist was applied, exposed to ultraviolet light, and developed. Next, after performing an etching process to form a conductor pattern, the resist was peeled off.
  • a semi-additive method may be used in which the electrolytic copper plating thickness (conductor thickness) is set to 2 to 3 microns, the plating resist is formed, and then the copper pattern is plated on the conductor pattern portion. I do not care.
  • a conductive paste 33A was applied to both lands 25a of each second conductive through hole 25 by screen printing.
  • the resist film 42, the first resin film 15, the second resin film 22, and the resist film 41 were stacked in the order shown in FIG.
  • the pressing temperature was in the range of 150 to 350 ° C., and the pressing pressure was in the range of 0.5 to 10 MPa.
  • the conductor 33 and the conductor pattern 12 of the resin film 15 were electrically connected.
  • the conductive paste 33A Dotite XA-824 made by Fujikura Kasei was used as the Ag paste.
  • the conductive paste 33A was an AgSn paste. For the details of the paste, the one described in paragraph 0075 of Japanese Patent No. 3473601 was used.
  • Example 2 a liquid crystal polymer film (Vecstar (registered trademark) CT-50N manufactured by Kuraray Co., Ltd.) having a thickness of 50 ⁇ m was used as a film substrate.
  • Vecstar registered trademark
  • CT-50N manufactured by Kuraray Co., Ltd.
  • Example 3 PEEK / PEI (IBUKI (registered trademark) manufactured by Mitsubishi Plastics, Inc.) having a thickness of 50 ⁇ m was used as a film substrate.
  • IBUKI registered trademark manufactured by Mitsubishi Plastics, Inc.
  • Example 4 In Examples 4, 5, 7 and 8, the same film substrate as in Example 2 was used. In Examples 6 and 9, the same film substrate as in Example 3 was used.
  • Example 2 the multilayer substrate was produced in the same manner as in Example 1, and the press pressure and temperature were the conditions according to Table 1.
  • Comparative example As Comparative Examples 1 to 6, a single-area layer plate and a double-sided laminated plate in which a copper foil and a film were bonded together were used, and for the interlayer connection, a blind via hole formed in a film was filled with a conductive paste by heat fusion pressing. A multilayer substrate was prepared. The conditions are shown in Table 2 below.
  • a method for producing the multilayer substrates of Comparative Examples 1 to 6 is shown below.
  • a conductor pattern was formed by etching using a copper clad laminate in which a copper foil and a film were heat-sealed. Via holes were formed with a laser.
  • the conductive paste was applied to the via hole of the film by a screen printing method.
  • a plurality of films fused with conductive paste embedded were superposed and batch heat fusion press was performed.
  • the pressing temperature was in the range of 230 to 350 ° C. and the pressing pressure in the range of 0.5 to 10 MPa. In this press, the films were fused together, the conductive paste filled in the via holes of the film was cured, and the conductive paste and the conductive pattern of the film were electrically connected.
  • connection reliability comparison A six-layer substrate having a conductor pattern according to L in Fig. 2.1 of JIS C 5012 was produced. However, the hole diameter of the interlayer connection portion was 100 microns, the land diameter was 0.5 mm, the wiring width was 0.3 mm, and the interval between the through holes was 7.62 mm. In the comparative example, a via hole having a diameter of 100 microns was formed at the same position of the through hole as in the present invention and filled with a conductive paste. In the present invention, a temperature cycle test corresponding to 9.1.3 description condition 1 of JIS C 5012 was performed, and the interlayer connection reliability was investigated. When the resistance value increased by 20% or more with respect to the initial resistance, it was regarded as a connection failure.
  • the deformation amount of the press thickness after the fusion press is small. Through hole connection reliability is high.
  • this invention can also be changed and embodied as follows.
  • the number of resin films stacked is not limited to “3”, and the present invention can be widely applied to a multilayer printed circuit board in which a plurality of resin films are stacked.
  • metal powder may be used instead of the conductive paste 33A.

Abstract

La présente invention concerne une carte de circuit imprimé multicouche (10), dans laquelle une pluralité de pellicules de résine (15) se chevauchent tout en accordant leurs directions verticales. Chaque pellicule de résine comporte un trou traversant (11), un motif conducteur (12) sur une surface et un trou traversant conducteur (14) intégralement formé avec le motif conducteur (12) sur une paroi intérieure du trou traversant. Des corps conducteurs (23) dont chacun est lié intermétalliquement au motif conducteur (12) qui lui fait face et le trou traversant conducteur (14) sont disposés entre deux pellicules de résine parmi les pellicules de résine (15). Une connexion intercouche entre les motifs conducteurs (12) des pellicules de résine est réalisée à travers le trou traversant conducteur (14) intégré avec le motif conducteur (12) et le corps conducteur (23) sans qu'une autre pellicule de résine soit insérée entre les deux pellicules de résine adjacentes.
PCT/JP2008/073243 2008-12-19 2008-12-19 Carte de circuit imprimé multicouche et son procédé de fabrication WO2010070771A1 (fr)

Priority Applications (3)

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KR1020117016658A KR101489034B1 (ko) 2008-12-19 2008-12-19 다층 프린트 기판 및 그의 제조 방법
PCT/JP2008/073243 WO2010070771A1 (fr) 2008-12-19 2008-12-19 Carte de circuit imprimé multicouche et son procédé de fabrication
CN2008801323987A CN102257887B (zh) 2008-12-19 2008-12-19 多层印刷基板及其制造方法

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013044002A1 (fr) * 2011-09-23 2013-03-28 Harris Corporation Procédé permettant de fabriquer une carte de circuit imprimé multicouche avec un composé intermétallique et cartes de circuit imprimé associées
JP2015211048A (ja) * 2014-04-23 2015-11-24 トヨタ自動車株式会社 多層基板、及びその製造方法
EP3478037A1 (fr) * 2017-10-20 2019-05-01 Toyota Jidosha Kabushiki Kaisha Procédé de fabrication d'un substrat multicouche

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102496404B (zh) * 2011-12-27 2013-10-30 华东理工大学 一种高效晶硅太阳电池用电极银浆

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62114297A (ja) * 1985-11-13 1987-05-26 富士通株式会社 多層プリント板の製造方法
JPH09246683A (ja) * 1996-03-13 1997-09-19 Nec Corp 電子部品の実装構造およびその製造方法
JP2006179827A (ja) * 2004-12-24 2006-07-06 Toyo Kohan Co Ltd フレキシブル基板用基材およびそれを用いたフレキシブル基板ならびそれらの製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3512225B2 (ja) * 1994-02-28 2004-03-29 株式会社日立製作所 多層配線基板の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62114297A (ja) * 1985-11-13 1987-05-26 富士通株式会社 多層プリント板の製造方法
JPH09246683A (ja) * 1996-03-13 1997-09-19 Nec Corp 電子部品の実装構造およびその製造方法
JP2006179827A (ja) * 2004-12-24 2006-07-06 Toyo Kohan Co Ltd フレキシブル基板用基材およびそれを用いたフレキシブル基板ならびそれらの製造方法

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013044002A1 (fr) * 2011-09-23 2013-03-28 Harris Corporation Procédé permettant de fabriquer une carte de circuit imprimé multicouche avec un composé intermétallique et cartes de circuit imprimé associées
CN103918357A (zh) * 2011-09-23 2014-07-09 贺利实公司 用以制作具有金属间化合物及相关电路板的多层电路板的方法
US8904632B2 (en) 2011-09-23 2014-12-09 Harris Corporation Method to make a multilayer circuit board with intermetallic compound and related circuit boards
KR101536544B1 (ko) * 2011-09-23 2015-07-13 해리스 코포레이션 금속간 화합물로 다층 회로기판을 구성하는 방법 및 관련된 회로기판
CN103918357B (zh) * 2011-09-23 2016-08-17 贺利实公司 用以制作具有金属间化合物及相关电路板的多层电路板的方法
US9655236B2 (en) 2011-09-23 2017-05-16 Harris Corporation Method to make a multilayer circuit board with intermetallic compound and related circuit boards
JP2015211048A (ja) * 2014-04-23 2015-11-24 トヨタ自動車株式会社 多層基板、及びその製造方法
EP3478037A1 (fr) * 2017-10-20 2019-05-01 Toyota Jidosha Kabushiki Kaisha Procédé de fabrication d'un substrat multicouche
US10766238B2 (en) 2017-10-20 2020-09-08 Denso Corporation Method of manufacturing multilayer substrate

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