Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
  • H04B1/06—Receivers
  • H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
  • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
  • G05F1/10—Regulating voltage or current 
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M1/00—Details of apparatus for conversion
  • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M3/00—Conversion of DC power input into DC power output
  • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
  • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
  • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
  • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
  • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
  • H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B15/00—Suppression or limitation of noise or interference

Definitions

• the present disclosure relates generally to integrated circuits, and more specifically to switching voltage regulators in wireless communication devices.
• Wireless communication devices require a battery or external DC power supply for a power source.
• ICs integrated circuits
• These ICs typically operate at a much lower DC voltage than either a battery or an external DC power supply attached to the wireless communication device.
• a switching voltage regulator is usually required to convert either an external DC power supply or battery voltage to the integrated circuits lower supply voltage.
• a switching voltage regulator provides the highest power efficiency when the difference between the battery voltage (VBAT) and the integrated circuits supply voltage (VDD) is more than a couple hundred millivolts.
• the battery is composed of a Li-ion cell with a 3.6V nominal voltage and the integrated circuits operate at 1.8V. Therefore, the difference between the battery voltage and the integrated circuits voltage is 3.6 V - 1.8 V or 1.8 V.
• a switching voltage regulator is strongly preferred over a linear regulator.
• a linear regulator would experience the full 1.8V drop between the battery and the load. The power dissipated by a linear regulator is equal to 1.8V * IDD (the load current of the integrated circuits).
• a switching voltage regulator may dissipate only 10% of the energy used by the integrated circuit (over a wide range of load current), whereas a linear regulator would dissipate 100% of the energy used by the integrated circuit regardless of the load current. Switching voltage regulators are often used in wireless communication devices for this reason.
• Switching voltage regulators may convert between a higher input voltage and a lower output voltage using one or more electronic switches in conjunction with energy storage devices (inductors or capacitors) to transfer energy between a higher external DC power supply voltage and a lower integrated circuit voltage.
• energy storage devices inductors or capacitors
• a switching voltage regulator frequency is dictated by the output voltage ripple requirement, the size of the series inductor and load filtering capacitor within a switching voltage regulator, output DC load current, and desired power efficiency of a switching voltage regulator.
• a switcher frequency of the switching voltage regulator can cause interference with other such components in the wireless communication device.
• This interference appears as voltage ripple on the VDD and ground connections of the RF transceiver circuit.
• This voltage ripple is composed of discrete frequency components.
• Each frequency component is a harmonic of the switcher frequency of the switching voltage regulator.
• a power level of each harmonic is dependent on (i) the duty cycle of the switcher frequency of the switching voltage regulator, (ii) the degree of capacitive filtering of the output voltage, as well as (iii) the type of coupling between the switching voltage regulator and the RF transceiver circuit.
• Radio frequency (RF) voltage-controlled oscillators are typically embedded in a RF transceiver and function as local oscillator(s) (LOs) to up-convert or down-convert communication signals from/to baseband to/from RF.
• LOs local oscillator
• voltage ripple at the output of the switching voltage regulator may combine with a frequency tuning element voltage of the RF VCO to create frequency modulation (FM) on the RF VCO output at offsets equal to the harmonics of the switching voltage regulator switcher frequency.
• FM frequency modulation
• the switching voltage regulator induced FM on the RF VCO causes harmonic spurious content to appear at offsets from the fundamental output carrier frequency of the RF VCO.
• This harmonic spurious content induced by the switching voltage regulator may interfere with the performance of a wireless communication device under certain operating conditions. For example, weak receive signal strength, the presence of external jammers at specific frequency offsets from a desired receive channel, and/or transmit leakage into a receive path in a full- duplex transceiver can all contribute to greater interference, in the presence of the switching voltage regulator, on the analog signals to be up- or down-converted to or from radio frequencies.
• Known ways to reduce the effect of switcher frequency spurious content caused by the switching voltage regulator in a wireless communication devices include: (i) adjusting the frequency of the switching voltage regulator continuously using pulse width modulation, pulse density modulation, or frequency hopping; b) toggling between a switching voltage regulator and a linear regulator during receive only modes of the wireless communication transceiver; and (iii) moving the switching voltage regulator as far away (using shielding and differential signal paths for improved isolation) from sensitive VCO and other components, all of which introduce a level of design complexity or inefficient use of circuit board or integrated circuit area.
• the switcher frequency is set by adjusting a frequency setting input to a programmable clock divider.
• a processor drives a programmable clock divider which receives a value representative of a dividing factor by which to divide a reference clock frequency signal to generate a desired switcher frequency for the switching voltage regulator. Values of the programmable clock divider are selectively varied to achieve optimal performance and mitigate the effect of switcher frequency spurious content for a given operating condition or conditions.
• FIG. 1 is a block diagram of a wireless communication device.
• FIG. 2 is a block diagram of a radio frequency (RF) transceiver.
• RF radio frequency
• FIG. 3 is a diagram of a radio frequency (RF) local oscillator (LO) generation block.
• RF radio frequency
• LO local oscillator
• FIG. 4 is a schematic diagram of a radio frequency voltage-controlled oscillator.
• FIG. 5 is a graphical illustration of RF VCO output frequency vs. RF VCO tuning voltage (Vt).
• FIG. 6 is a block diagram of a switching voltage regulator in accordance with a preferred embodiment.
• FIG. 7 shows a block diagram of the receive signal processing block of FIG.
• FIG. 8 is a graphical illustration showing the impact of interference from a switching voltage regulator on (i) RF LO output, (ii) transmit RF channel leakage, and
• FIG. 9 is an operational flow diagram of the process of selecting a switcher frequency for a switching voltage regulator utilizing a switching voltage regulator controller in accordance with a preferred embodiment.
• FIG. 10 is an operational flow diagram of the process of selecting an optimal switcher frequency, Fsw, for the switching voltage regulator in different operating frequency bands for CDMA mode in accordance with a preferred embodiment.
• FIG. 1 is a block diagram of a wireless communication device 10 in accordance with the present embodiment as shown.
• Wireless communication device 10 includes radio frequency (RF) antenna 12 connected to RF Front-End 14.
• RF Front-End 14 separates transmit and receive RF signal paths, and provides amplification and signal distribution.
• RF signals for transmit, TX_RF, and receive, RX_RF are passed between transceiver 20 and RF Front-End 14.
• Transceiver 20 is configured to down-convert a RX RF signal from RF to a signal for baseband I/Q demodulation by processor 70, which may be a baseband modem or the like. Transceiver 20 is similarly configured to up-convert a signal from processor 70, using baseband I/Q modulation, to a TX_RF signal. Signals to be up- converted and down-converted from/to baseband I/Q modulation are shown connected between transceiver 20 and processor 70.
• Memory 75 stores processor programs and data and may be implemented as a single integrated circuit (IC), as shown.
• IC integrated circuit
• Processor 70 is configured to demodulate incoming baseband receive I/Q signals, encode and modulates baseband transmit VQ signals, and run applications from storage, such as memory 75, to process data or send data and commands to enable various circuit blocks, all in a known manner.
• processor 70 generates control signals to transceiver 20 through a data bus, serial bus, or a dedicated set of signals.
• control signals may include, for example, turning transceiver 20 on and off, measuring received signal strength, setting transmit RF signal power or receive signal path gains, changing RF channels, detecting receiver signal jammers, and switching transmit/receive signal blocks between high power and power saving modes.
• Processor 70 is also configured to read the state of transceiver 20, and at the same time also receive one or more interrupt signals (not shown) from transceiver 20. Interrupt signals are used to initiate commands and algorithms between transceiver 20 and processor 70.
• processor 70 transceiver 20, and memory 75 are well known and understood by those skilled in the art, and that various ways of implementing the associated functions are also well known, including providing or combining functions across fewer integrated circuits (ICs), or even within a single IC.
• ICs integrated circuits
• DC power is conventionally provided from a generic DC power source 60.
• DC power source 60 may consist of either an external DC power supply 61a (output voltage labeled VEXT) or a battery 61b (output voltage labeled VBAT). Either output voltage VEXT from DC power supply 61a or the output voltage VBAT from battery 61b drive a supply voltage into switching voltage regulator 40.
• Switching voltage regulator 40 is configured to convert supply voltage of VEXT or VBAT to individual supply voltages for powering each of processor 70 (BB_VDD), transceiver 20 (TCVR_VDD), memory 75 (MEM_VDD), and RF Front- End 14 (PAJVDD and VBIAS). Switching voltage regulator 40 may also provide supply voltages to other blocks as necessary (not shown).
• Switching voltage regulator 40 is configured to convert between a higher input voltage and a lower output voltage by toggling on and off, at a switcher frequency (hereafter "Fsw”), one or more switches in conjunction with energy storage devices (inductors or capacitors) to transfer energy between the higher input voltage and lower output voltage.
• Fsw switcher frequency
• processor 70 controls the switcher frequency, Fsw, of switching voltage regulator 40, depending on one or more conditions of transceiver 20. As previously described in the background of the disclosure, switching voltage regulator 40 may interfere with transceiver 20 operation.
• Transceiver 20 conditions include an operating mode (CDMA, TDMA,
• FDMA frequency division multiple access
• OFDMA frequency division multiple access
• SC-FDMA GPS, Among other things, FDMA, OFDMA, SC-FDMA, GPS, ...) with associated receive signal bandwidth, operating frequency band (US cellular, US PCS, IMT, ...), and receive jamming detection circuit (jammer present, jammer power level, and jammer frequency offset from desired receive signal).
• REF_CLK reference clock frequency signal
• FIG. 2 is a block diagram of a radio frequency (RF) transceiver (transceiver 20) of FIG. 1 in accordance with the present embodiment as shown.
• Transceiver 20 includes transmit signal processing block 22, receive signal processing block 24, RF local oscillator (RF LO) generation block 28, and control and status block 26.
• Control and status block 26 provides digital control logic to/from processor 70 including a jammer detect signal.
• REF CLK from reference clock oscillator 80, feeds into RF LO generation block 28.
• Transceiver 20 while shown with just one transmit and receive signal processing block, may also exist with any combination of multiple receive blocks, multiple transmit blocks, or any number of possible transmit and receive signal processing block configurations.
• transmit signal processor block 22 and receive signal processing block 24 are shown as separate functional blocks but may be combined to some extent in a half duplex radio device mode.
• RF LO generation block 28 while logically shown as a separate common block disposed between transmit signal processing block 22 and receive signal processing block 24, other configurations are contemplated.
• Control and status block 26 can be similarly reconfigured without departing from the scope of the preferred embodiments described herein.
• FIG. 3 is a diagram of a radio frequency (RF) local oscillator (LO) generation block 28 of FIG. 2 in accordance with the present embodiment as shown.
• RF LO generation block 28 includes a RX LO generation block 29 and a TX LO generation block 37.
• RX LO generation block 29 includes a channel selection tuning block 31 comprising a RF PLL and loop filter.
• Channel selection tuning block 31 compares REF CLK from reference clock oscillator 80 to output signal, RX VCO, from RF VCO 33 to lock RF VCO 33 to a desired frequency.
• the output, Vt, from channel selection tuning block 31 is an analog control signal for tuning the frequency of output signal RX VCO of RF VCO 33.
• the output signal RX VCO is further processed by LO generation block 35 and frequency converted to a desired receive RF channel frequency, RX LO.
• LO generation block 35 may be implemented using frequency dividers, frequency mixers, switches, or a combination of all three types of elements to create a variety of frequency multiplication or division ratios between signals RX VCO and RX LO.
• the RX LO signal frequency is equal to the desired RX RF channel frequency in a particular operating frequency band (US cellular, US-PCS, IMT, GPS, etc).
• RX_L0 signal is connected to the receive signal processing block 24 of FIG. 2.
• FIG. 4 is a schematic diagram of the radio frequency voltage-controlled oscillator, RF VCO 33, of FIG. 3 in accordance with the present embodiment as shown.
• RF VCO 33 includes a fixed inductor Lvco 43 in parallel with two varactor elements 41 (VCAPl and VCAP2) to shift the frequency of output signal RXJVCO. This frequency
• &%fff$ is the total capacitance of the two varactor elements 41 (VCAPl and VCAP2).
• Frequency tuning is achieved by varying the total capacitance by adjusting the output, Vt, from channel selection tuning block 31 which is input across VCAPl and VCAP2.
• the output of RF VCO 33, RX VCO, is then input back to channel selection tuning block 31 and into LO generation block 35, as shown in FIG. 3.
• the circuit shown in FIG. 4 may apply across as many RF VCOs as required for multiple paths of both RX and TX.
• one RF VCO may cover multiple modes and operating bands as long as simultaneous operation in multiple frequency bands is not required.
• Other circuit topologies are known that can shift the output frequency of an RF VCO, but are functionally equivalent.
• FIG. 5 is a graphical illustration of RF VCO output frequency vs. tuning voltage (Vt) of FIG. 4 in accordance with the present embodiment as shown.
• Vt tuning voltage
• the frequency tuning range of RF VCO 33 is continuously adjusted by tuning voltage, Vt, between 0 and .7 volts DC.
• KV 5,000 MHz/V
• Kv 5000 MHz/V
• voltage ripple 1 uV
• Fsw 2 MHz
• FIG. 6 is a schematic diagram of a switching voltage regulator 40 in accordance with a preferred embodiment of FIG. 1.
• Switching voltage regulator 40 includes a voltage source input, VBAT, from power source 61b of FIG. 1, and voltage output, TCVR VDD for transceiver 20, PA VDD and VBIAS for RF Front-End 14, BBJVDD for processor 70, and MEMJVDD for memory 75 of FIG. 1.
• An alternate input voltage VEXT may also be used if selected by either switcher 40 or processor 70 in FIG. 1.
• Individual output voltages such as PA VDD, VBIAS, BB VDD and MEMJVDD may be generated separately with additional switching voltage regulators if different supply voltages are required.
• VEXT and TCVR_VDD are switches 61a and 61b along with a switching voltage regulator controller 63, a programmable clock divider 64, a series inductor Lsw 65, and a shunt filtering capacitor Csw 67.
• Switching voltage regulator controller 63 compares the output voltage TCVR_VDD (along with PA_VDD, VBIAS, BB_VDD, and MEM_VDD) to a programmable voltage setting value based on a reference voltage generator 62 output voltage and adjusts the duty cycle of Sl and S2 such that the output voltage, TCVR_VDD (along with PA_VDD, VBIAS, BB_VDD, and MEM_VDD), converges to the programmed voltage setting value.
• the programmed voltage setting value is set by processor 70 or can be hardware configured to a fixed value internal to switching voltage regulator 40.
• the switcher frequency, Fsw to the switching voltage regulator controller 63, is set by a switcher frequency setting value for programmable clock divider 64.
• Programmable clock divider 64 may be an integer frequency divider between REF_CLK (from reference clock oscillator 80 in this example), and the switcher frequency, Fsw, used to control switches 61a and 61b.
• REF_CLK output frequency is 19.2 MHz and the programmable clock divider 64 is set between 3 different frequency setting values (divide by 6, 7, or 8) depending on the process shown subsequently in FIG. 9.
• Switching voltage regulator 40 is coupled to transceiver 20 directly via the supply voltage TCVRJVDD as shown in FIGs. 1 and 6.
• the switcher frequency, Fsw, of the switching voltage regulator 40 may interfere with the performance of transceiver 20.
• the interference appears as voltage ripple on TCVR VDD.
• the voltage ripple is composed of discrete frequency components. Each frequency component is a harmonic of the switcher frequency, Fsw, of the switching voltage regulator 40.
• a power level of each harmonic is dependent on (i) the duty cycle of the switcher frequency, Fsw, of the switching voltage regulator 40, (ii) the degree of capacitive filtering of the output voltage TCVRJVDD, as well as (iii) the method of coupling between TCVRJVDD and sensitive circuits within transceiver 20.
• one of the most sensitive circuits within transceiver 20 is RF VCO 33.
• Voltage ripple at the output of the switching voltage regulator 40 may combine with the tuning voltage, Vt, of RF VCO 33 to create frequency modulation (FM) of the RF VCO 33 output, RX VCO, at frequency offsets equal to the harmonics of the switcher frequency, Fsw, of switching voltage regulator 40.
• FM frequency modulation
• the switcher frequency, Fsw, of switching voltage regulator 40 may interfere with the performance of wireless communication device 10 under certain operating conditions.
• the first operating condition is based on a current operating technology mode (GSM, CDMA, WCDMA, etc).
• GSM current operating technology mode
• CDMA CDMA
• WCDMA WCDMA
• Fch RF channel bandwidth
• the switcher frequency, Fsw, of the switching voltage regulator 40, associated with a given technology mode is adjusted such that it is greater than half the RF channel bandwidth (Fsw>Fch/2).
• This switcher frequency adjustment reduces or eliminates switcher voltage regulator 40 interference on transceiver 20 from appearing on the baseband analog receive signals (RX I FILT and RX Q FILT in FIG. 2) and transmit signals (TX_I, TX_Q of FIG. 2).
• wireless communication device 10 operating in full duplex mode
• setting the switcher frequency of switching voltage regulator 40 higher than half the RF channel bandwidth is particularly useful in mitigating interference.
• the RF operating band includes only one frequency band of interest for that technology mode (US cellular, US PCS, CDMA in the IMT band, etc.).
• the operating frequency band is one of several possible frequency bands.
• D 45 MHz.
• D 80 MHz.
• the transmit RF channel (at Ftx) must not mix with spurious content (from switching voltage regulator 40), as it may create interference at the receive RF channel frequency (at Frx).
• the switcher frequency, Fsw, of switching voltage regulator 40 must, in fact, not fall within a range of frequencies such that D - Fch ⁇ N*Fsw ⁇ D + Fch where N*Fsw is the nearest integer switcher frequency harmonic to D.
• FIG. 7 is a block diagram of receive signal processing block 24 in FIG. 2 in accordance with the present embodiment as shown.
• Receive signal processing block 24 includes RX RF I/Q down-converter 55, a pair of baseband analog low-pass filters 57a and 57b, and jamming detection block 59.
• Alternative embodiments may include low- noise amplifiers, RF filtering, multiple RF bands, and various forms of gain control circuitry.
• RX RF signal from RF Front-End block 14 is fed into VQ down- converter 55 as well as out-of-RX band interference prior to down-converting the receive RF signal using a direct-conversion (RF to baseband) VQ mixers within VQ down-converter 55.
• the outputs of I/Q down-converter 55, RX_I and RX_Q are filtered by low-pass filters 57a and 57b prior to further processing in either in analog (on either transceiver 20 or processor 70) or digital domain (after conversion with analog to digital converters on either transceiver 20 or processor 70).
• low-pass filters 57a and 57b may include fixed or variable gain to adjust RX I FILT and RX Q FILT amplitude prior to analog to digital conversion in processor 70.
• Jamming detection circuit 59 sends a jammer detect signal, which value communicates to processor 70 when jammers are present which are frequency offset from a selected receive channel.
• Jamming detection circuit 59 may take measurements in the baseband analog domain before or after analog low-pass filters 57a and/or 57b to detect the presence of jammers offset from the RX I and RX Q signals in frequency.
• jamming detection block 59 may be implemented in the digital domain in processor 70 or split between transceiver 20 and processor 70.
• the switcher frequency of the switching voltage regulator 40 is set so as to mitigate this interference in the baseband receive signal path when one or more jammers are present above a predefined and detectable threshold in the baseband receive signal path.
• the spurious content problem acting on receive signal processing block 24 as described above in connection with FIG. 2 and FIG. 7 may be graphically illustrated.
• FIG. 8 is a graphical illustration showing the impact of interference from a switching voltage regulator on (i) RF_LO output, (ii) transmit RF channel leakage, and (iii) receiver performance in the presence of jammers for FIGs. 1-7 in accordance with the present embodiment as shown.
• Illustration 90 includes an amplified/filtered RX RF signal input with receive signal at Frx, transmit signal leakage at Ftx, and a jammer signal at Fj I (from block 53 of FIG. 7) as input to VQ down-converter 55 (of FIG. 7).
• Illustration 90 also includes a RX_LO signal (from block 35 of FIG.
• Illustration 90 also includes a RX I signal from the in-phase, or I down-converter of VQ down-converter 55 of FIG. 7.
• the illustrated RX I signal shows the mixing products of RX RF and RX LO input signals at I/Q down-converter 55 baseband output.
• the desired receive baseband channel, RX BB in the RX I signal path is centered at DC.
• RX BB receive baseband channel
• spurious content that falls within the receive channel, RX BB, specifically Jl-3*Fsw and Dtx-N*Fsw (where N is an integer, N*Fsw is a harmonic of the switcher frequency of switching voltage regulator 40).
• FIG. 9 is an operational flow diagram of the process of selecting a switcher frequency for a switching voltage regulator utilizing a switching voltage regulator controller in accordance with a preferred embodiment.
• Operation flow diagram 100 starts with processor 70 identifying the current operating condition (e.g., current operating band, operating mode, and/or jammer detect value) (block 101).
• Processor 70 then generates a switcher frequency setting value on the basis of the current operating condition (block 103).
• Programmable clock divider 64 receives and processes the switcher frequency setting value in combination with reference frequency clock signal, REF_CLK, and generates the desired switching frequency (block 105).
• Switching voltage regulator controller 63 receives the switching frequency from programmable clock divider 64, the voltage setting value, for example, from processor 70, and the signal from the reference voltage regulator 62, to generate switch signals (block 107).
• the switch signals are used to toggle switches (61a, 61b) which have the effect of regulating the output voltage of switching voltage regulator 40 (block 109).
• the operation flow diagram 100 may restart if the current operating condition changes (back to block 101).
• FIG. 10 is an operational flow diagram of the process of selecting an optimal switcher frequency, Fsw, for the switching voltage regulator in different operating frequency bands for CDMA mode accordance with a preferred embodiment.
• Operation flow diagram 200 starts with a start block (block 201) followed by programming one or more registers within the transceiver 20 for the particular operating band to be used (block 203).
• programmable clock divider 64 in switching voltage regulator 40, is set to one of three different values 6, 7, or 8 such that the switcher frequency (Fsw) of switching voltage regulator 40 is equal to either 2.4 MHz (CDMA PCS band), 2.74 MHz (CDMA450/800 band), or 3.2 MHz (CDMA IMT band) based on a reference clock frequency signal, REF_CLK, of 19.2 MHz (block 205).
• the switcher frequency, Fsw is calculated based multiple parameters.
• Fsw must be greater than half of Fch to insure that the switching noise does not directly couple into the baseband VQ analog signals as shown in FIG. 1, 2, 7, and 8.
• Table 1 below shows Fch for different operating modes. Additional operating modes may be included. Operational flow diagram 200 is simplified to one operating mode, CDMA. Additional criteria will require that the switcher frequency, Fsw, be adjusted to higher values when there is transmit signal leakage and/or jamming tones present at the receiver input.
• the second criterion is that the transmit RF channel leakage (in a full duplex system such as CDMA) not corrupt the receive RF channel.
• the RF LO Generation block 28 will be contaminated with switcher frequency voltage ripple and corresponding harmonic frequencies from switching voltage regulator 40. If a switcher frequency harmonic is at a frequency offset close to the frequency separation between transmit RF and receive RF channels, the particular switcher harmonic will mix with the transmit RF channel leakage at VQ down-converter 55 (after the switcher frequency voltage ripple has coupled into the RF VCO 33 (RX VCO and RX LO signals) and generate receive signal processing interference.
• switcher frequency voltage ripple and corresponding harmonic frequencies can couple to RF VCO within the TX LO Generation block 37 and create spurious content in the output of transmit signal processing block 22 of transceiver 20. This transmit spurious content can fall within the receive RF channel and create receive RF channel interference.
• the receive RF channel to transmit RF channel separation for different operating bands is shown in Table 2 below.
• the third criterion is based on the presence of jamming interference close in frequency to the desired receive RF channel.
• the fundamental switcher frequency (coupled onto RF VCO 33) can mix with the offset jamming tones (FJl at RF, Jl at baseband of FIG. 8) to create interference within the receive baseband channel bandwidth (RX BB of FIG. 8) that cannot be filtered out or eliminated.
• the receive signal processing block 24 jamming specifications for different operating bands and modes may be applied such that the wireless device complies with the published minimum performance standards.
• the jammer frequency offsets from the desired RX RF channel (Jl offset for single-tone tests or Jl + J2 offsets for two-tone tests) are specified per the following operating bands as follows in Table 3.
• the switcher frequency may be adjusted such that Fsw > (Jl or J2) + Fch/2.
• Jl or J2 frequency offsets may be chosen from Table 3 for the above Fsw formula.
• the presence of jamming interference takes priority over TX signal leakage (second criterion) if there is no switcher frequency that satisfies both the second or third criteria.
• REF_CLK 19.2 MHz clock frequency signal
• optimal switcher frequencies, Fsw may be calculated for multiple operating conditions in CDMA mode and stored as shown in Table 4 below.
• 2.4 MHz is generated by dividing 19.2 MHz by 8
• 2.74 MHz is generated by dividing 19.2 MHz by 7
• 3.2 MHz is generated by dividing 19.2 MHz by 6.
• the switcher frequency values of 6, 7, and 8 are selected for different CDMA frequency bands with and without jammers.
• jamming detection circuit 59 is either polled or used as an interrupt (block 107).
• jammer detect signal is active (high logic level) in CDMA-PCS mode (according to Table 4)
• the switcher frequency (Fsw) is changed from 2.4 MHz to 2.74 MHz (block 109) by changing the switcher frequency value from 8 to 7.
• switcher frequency (Fsw) will be changed back to 2.4 MHz by changing the switcher frequency value to 8 (block 105 repeated) and jamming detection circuit 59 will continue monitoring (block 107, etc).
• switcher frequencies may be used depending on the available reference clock frequency signal, REF CLK, and divider ratios for programmable clock divider 64 such that the three criteria are optimally met.
• signals may be represented using any of a variety of different techniques. For example, data, instructions, signals that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, or any combination thereof.
• DSP digital signal processor
• ASIC application specific integrated circuit
• FPGA field programmable gate array
• a general- purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine.
• a processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
• the steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two.
• a software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
• An exemplary storage medium is coupled to the processor such that the processor may read information from, and write information to, the storage medium.
• the storage medium may be integral to the processor.
• the processor and the storage medium may reside in an ASIC.
• the ASIC may reside in a user terminal.
• the processor and the storage medium may reside as discrete components in a user terminal.

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• 2008
  • 2008-12-04 US US12/327,990 patent/US8294445B2/en active Active
• 2009
  • 2009-12-04 CN CN200980148539.9A patent/CN102239642B/zh active Active
  • 2009-12-04 WO PCT/US2009/066882 patent/WO2010065934A1/en active Application Filing
  • 2009-12-04 JP JP2011539765A patent/JP2012511285A/ja active Pending
  • 2009-12-04 TW TW103119281A patent/TWI533627B/zh active
  • 2009-12-04 TW TW98141652A patent/TWI472166B/zh active
  • 2009-12-04 CN CN201410158748.4A patent/CN103997211B/zh active Active
  • 2009-12-04 KR KR1020117015423A patent/KR101263814B1/ko active Active
  • 2009-12-04 EP EP14181948.2A patent/EP2827505B1/en active Active
  • 2009-12-04 EP EP09796513.1A patent/EP2371067B1/en not_active Not-in-force
• 2013
  • 2013-12-06 JP JP2013253675A patent/JP5805738B2/ja active Active
• 2014
  • 2014-06-11 IN IN4321CHN2014 patent/IN2014CN04321A/en unknown

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