WO2010057340A1 - 一种采用ligbt输出级的集成电路 - Google Patents

一种采用ligbt输出级的集成电路 Download PDF

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Publication number
WO2010057340A1
WO2010057340A1 PCT/CN2008/073107 CN2008073107W WO2010057340A1 WO 2010057340 A1 WO2010057340 A1 WO 2010057340A1 CN 2008073107 W CN2008073107 W CN 2008073107W WO 2010057340 A1 WO2010057340 A1 WO 2010057340A1
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Prior art keywords
output stage
ligbt
integrated circuit
ldmos
region
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PCT/CN2008/073107
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English (en)
French (fr)
Inventor
乔明
赵磊
张波
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深圳市联德合微电子有限公司
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Priority to PCT/CN2008/073107 priority Critical patent/WO2010057340A1/zh
Publication of WO2010057340A1 publication Critical patent/WO2010057340A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

Definitions

  • the present invention relates to semiconductor power devices and integrated circuits, and more particularly to an integrated circuit using an LIGBT output stage.
  • the high-voltage power integrated circuit integrates the high-voltage power device with the low-voltage control and protection circuit monolithically, reducing the number of components, the number of interconnections and the number of solder joints in the system, which not only improves the reliability and stability of the system, but also reduces the number of components. System power, size, weight and cost.
  • the lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOS) has a single-chip integration with low-voltage devices and circuits through internal connections because all the electrodes of the device are located on the surface of the chip, and its driving circuit is simple, making it widely used in high-voltage power integrated circuits. in.
  • the LDMOS has a large on-resistance as an output stage of the integrated circuit, which increases the conduction loss of the output stage of the integrated circuit.
  • FIG. 1 shows an integrated circuit using an LDMOS output stage.
  • 1 is the control circuit
  • 2 is the LDMOS low voltage source region
  • 3 is the LDMOS high voltage drain region.
  • the low voltage source region 2 of the structure surrounds the high voltage drain region 3 so that the high voltage is isolated inside the LDMOS. Due to the contradiction between the withstand voltage and the on-resistance of the LDMOS device, the output stage operates at a high voltage and a large current, and a larger LDMOS device area is required. In general, it is necessary to reduce the on-resistance of the output stage.
  • the current practice is usually to use multiple LDMOS devices in parallel and to use a larger LDMOS device area, which will undoubtedly increase the area of the integrated circuit and increase the cost of the chip.
  • the technical problem to be solved by the present invention is to provide a method for paralleling a plurality of LDMOS devices and using a larger LDMOS device area in the prior art, thereby increasing the area of the integrated circuit and increasing the cost of the chip.
  • the technical solution adopted by the present invention to solve the technical problem thereof is: constructing an integrated circuit using an LIGBT output stage, comprising a control circuit and an LDMOS output stage and an LIGBT output stage, the LDMOS output The gate of the stage and LIGBT output stage is connected to the control circuit, wherein
  • the source of the LDMOS output stage is connected to the cathode of the LIGBT output stage, said L
  • the drain of the DMOS output stage is connected to the anode of the LIGBT output stage.
  • control circuit and the LDMOS output stage and the LIGBT output stage are disposed on the integrated circuit module.
  • the LDMOS output stage includes a gate region, a low voltage source region, and a high voltage drain region
  • the LIGBT output stage includes a gate region, a low voltage cathode region, and a high voltage anode region.
  • the low voltage source region of the LDMOS output stage and the low voltage cathode region of the LIGBT output stage are not shared at the potential.
  • the low voltage source region of the LDMOS output stage and the low voltage cathode region of the LIGBT output stage are shared at the same potential, and the high voltage drain region and the LIGBT output of the LDMOS output stage are The high voltage anode regions of the stage are alternately formed.
  • the high voltage drain region of the LDMOS output stage has the same or different width as the high voltage anode region of the LIGBT output stage.
  • the LDMOS output stage and the LIGBT output stage are N-channel devices or P-channel devices.
  • the integrated circuit module is made of a silicon material, insulator silicon, silicon nitride or silicon carbide.
  • the integrated circuit for implementing the LIGBT output stage of the present invention has the following beneficial effects:
  • the on-resistance of the output stage of the integrated circuit is reduced by the conductance modulation effect of the output stage of the LIGBT, and the current capability of the output stage is improved, and the conventional LDMOS is solved.
  • the contradiction between the withstand voltage and the on-resistance of the output stage; in the same power processing capability, the area of the integrated circuit using the LIGBT output stage is lower than that of the integrated circuit using the LDMOS output stage, so various performances can be produced by the present invention.
  • Figure 1 is a schematic diagram of an integrated circuit using an LDMOS output stage
  • FIG. 2 is a logic block diagram of one embodiment of an integrated circuit employing an LIGBT output stage; 3 is a schematic structural view of a first embodiment of an integrated circuit of the present invention;
  • FIG. 4 is a schematic structural view of a second embodiment of an integrated circuit of the present invention.
  • Figure 5 is a block diagram showing the structure of a third embodiment of the integrated circuit of the present invention.
  • the core of the present invention is to provide a lateral insulated gate bipolar transistor LIGBT (Lateral Insulated-Gate Bipolar)
  • the integrated circuit structure of the output stage Compared with the traditional technology, the LIGBT is used as the output stage of the power integrated circuit, and the on-resistance of the output stage of the circuit is reduced by the conductance modulation effect to improve the current capability of the output stage, thereby solving the traditional LDMOS output stage withstand voltage and on-resistance. The contradiction between. With the same power handling capability, the area of the integrated circuit using the LIGBT output stage is reduced compared to the area of the integrated circuit using the LDMOS output stage.
  • FIG. 2 there is shown an embodiment of an integrated circuit for an LIGBT output stage of the present invention.
  • the integrated circuit shown includes a control circuit 1 and an LDMOS output stage 6 and an LIGBT output stage 7, a LDMO S output stage 6 and a gate of the LIGBT output stage 7 connected to the control circuit 1.
  • the source of the LD MOS output stage 6 is connected to the cathode of the LIGBT output stage 7, the drain of the LDMOS output stage 6 and the LIG
  • the invention utilizes the conductance modulation effect of the LIGBT device to reduce the on-resistance per unit area of the output stage, thereby improving the current capability per unit area of the output stage, thereby reducing the area of the integrated circuit and saving the chip cost.
  • the control circuit 1 and the LDMOS output stage 6 and the LIGBT output stage 7 are arranged on the integrated circuit module.
  • the LDMOS output stage 6 includes a gate region, a low voltage source region 2, and a high voltage drain region 3
  • the LIG BT output stage 7 includes a gate region, a low voltage cathode region 4, and a high voltage anode region 5.
  • the gate region, the source region 2 and the drain region 3 of the LDMO S output stage 6 are independent of the gate region, the anode region 4 and the cathode region 5 of the LIGBT output stage 7, respectively.
  • LDMOS low-voltage source region 2 and the LIGBT low-voltage cathode region 4 have the same potential, and can be short-circuited together to further reduce the chip area, wherein the LIGBT low-voltage cathode region 4 and the LDMOS low-voltage source region 2 are shared.
  • LDMOS low voltage source region 2 as shown in Figure 4;
  • LIGBT low voltage cathode region 4 and LDMOS low voltage source region 2 share LDMOS low voltage source region 2, LDMOS high voltage drain region 3 and LIGBT high voltage anode region 5 alternately, wherein LDMOS high voltage drain region 3 and LIGBT high voltage anode region 5 width They can be the same or different.
  • the integrated circuit of the LIGBT output stage of the present invention utilizes the conductance modulation effect to reduce the on-resistance of the output stage of the integrated circuit, improve the current capability of the output stage, and solve the contradiction between the withstand voltage and the on-resistance of the conventional LDMOS output stage. .
  • the area of the integrated circuit using the LIGBT output stage is reduced compared to the area of the integrated circuit using the LDMOS output stage.
  • a high-voltage N-channel device as shown in Figure 2.
  • LIGBT is used as the output stage of the integrated circuit.
  • the conductance modulation effect is used to reduce the on-resistance of the output stage of the integrated circuit, improve the current capability of the output stage, and solve the contradiction between the withstand voltage and the on-resistance of the conventional LDMOS output stage.
  • the area of the integrated circuit using the LIGBT output stage is reduced compared to the area of the integrated circuit using the LDMOS output stage.
  • the gates of 7 can be shorted together or controlled by different output signals of the control circuit 1.
  • the drain of the LDMOS output stage 6 and the anode of the LIGBT output stage 7, the source of the LDMOS output stage 6, and the cathode of the LIGBT output stage 7 can be shorted together or separately connected depending on the application requirements.
  • the on-resistance of the output stage of the integrated circuit is greatly reduced, reducing the area of the integrated circuit.
  • the LDMOS output stage 6 and the LIGBT output stage 7 are N-channel devices or P-channel devices.
  • the integrated circuit module can be made of silicon material, insulator silicon SOI (Silicon on
  • Silicon Nitride SIN Silicon Nitride
  • Silicon Carbide SIC Silicon Carbide
  • the integrated circuit of the LIGBT output stage of the present invention can improve the performance of the integrated circuit:
  • the on-resistance of the output stage of the circuit improves the current capability of the output stage and reduces the conduction loss of the output stage of the integrated circuit.
  • the present invention provides an integrated circuit for an LIGBT output stage. Since all the electrodes of the device are located on the surface of the chip, it is easy to integrate monolithic with low-voltage devices and circuits through internal connections, and the driving circuit is simple.
  • the conductance modulation effect is used to reduce the on-resistance of the output stage of the integrated circuit, improve the current capability of the output stage, and solve the contradiction between the withstand voltage and the on-resistance of the conventional LDMOS output stage.
  • the area of the integrated circuit using the LIGBT output stage is reduced compared to the area of the integrated circuit using the LDMOS output stage. Therefore, the present invention can be used to fabricate various high-voltage, high-speed, low-conduction loss integrated circuits with excellent performance.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

说明书 一种釆用 LIGBT输出级的集成电路
#細或
[1] 本发明涉及半导体功率器件和集成电路， 更具体地说， 涉及一种釆用 LIGBT输 出级的集成电路。
[2] 高压功率集成电路将高压功率器件与低压控制和保护电路单片集成， 减少了系 统中的元件数、 互连数和焊点数， 不仅提高了系统的可靠性、 稳定性， 而且减 少了系统的功耗、 体积、 重量和成本。 横向双扩散金属氧化物半导体场效应晶 体管 LDMOS由于器件所有电极均位于芯片表面， 易于通过内部连接实现与低压 器件和电路的单片集成， 并且其驱动电路简单， 使之广泛应用于高压功率集成 电路中。 然而， 由于 LDMOS器件耐压与导通电阻之间的矛盾， 使 LDMOS作为 集成电路输出级吋， 具有较大的导通电阻， 增加了集成电路输出级的导通损耗
[3] 图 1示出了釆用 LDMOS输出级的集成电路。 其中 1是控制电路， 2是 LDMOS低 压源极区， 3是 LDMOS高压漏极区。 该结构低压源极区 2将高压漏极区 3包围， 使得高压被隔离在 LDMOS内部。 由于 LDMOS器件耐压与导通电阻之间的矛盾 ， 使得输出级工作在高压大电流吋， 需釆用较大的 LDMOS器件面积。 总的来说 ， 需要降低输出级的导通电阻， 目前的做法通常是釆用多个 LDMOS器件并联以 及釆用较大的 LDMOS器件面积， 这样无疑会增加集成电路的面积而提高芯片的 成本。
[4] 本发明要解决的技术问题在于， 针对现有技术的上述釆用多个 LDMOS器件并 联以及釆用较大的 LDMOS器件面积， 因而增加集成电路的面积和提高芯片成本 的缺陷， 提供一种釆用 LIGBT输出级的集成电路。
[5] 本发明解决其技术问题所釆用的技术方案是： 构造一种釆用 LIGBT输出级的集 成电路， 其包括控制电路以及 LDMOS输出级与 LIGBT输出级， 所述 LDMOS输出 级及 LIGBT输出级的栅极与控制电路连接， 其中
[6] 在电位相同吋， 所述 LDMOS输出级的源极与 LIGBT输出级的阴极连接， 所述 L
DMOS输出级的漏极与 LIGBT输出级的阳极连接。
[7] 在本发明所述的集成电路中， 所述控制电路以及 LDMOS输出级与 LIGBT输出 级设置于集成电路模块上。
[8] 在本发明所述的集成电路中， 所述 LDMOS输出级包括栅极区、 低压源极区及 高压漏极区， 所述 LIGBT输出级包括栅极区、 低压阴极区及高压阳极区。
[9] 在本发明所述的集成电路中， 所述 LDMOS输出级的低压源极区与 LIGBT输出 级的低压阴极区在电位不同吋不共用。
[10] 在本发明所述的集成电路中， 所述 LDMOS输出级的低压源极区与 LIGBT输出 级的低压阴极区在电位相同吋共用， 所述 LDMOS输出级的高压漏极区与 LIGBT 输出级的高压阳极区交替构成。
[11] 在本发明所述的集成电路中， 所述 LDMOS输出级的高压漏极区与 LIGBT输出 级的高压阳极区的宽度相同或者不相同。
[12] 在本发明所述的集成电路中， 所述 LDMOS输出级与 LIGBT输出级为 N型沟道器 件或者 P型沟道器件。
[13] 在本发明所述的集成电路中， 所述集成电路模块由硅材料、 绝缘体硅、 氮化硅 或者碳化硅制成。
[14] 实施本发明的釆用 LIGBT输出级的集成电路， 具有以下有益效果： 利用 LIGBT 输出级的电导调制效应降低集成电路输出级的导通电阻， 提高输出级的电流能 力， 解决了传统 LDMOS输出级耐压与导通电阻之间的矛盾； 在相同功率处理能 力吋， 釆用 LIGBT输出级的集成电路面积较釆用 LDMOS输出级的集成电路面积 降低， 因此利用本发明可以制作各种性能优良的高压、 高速、 低导通损耗的集 成电路。
國删
[15] 下面将结合附图及实施例对本发明作进一步说明， 附图中：
[16] 图 1是釆用 LDMOS输出级的集成电路的示意图；
[17] 图 2是釆用 LIGBT输出级的集成电路的一个实施例的逻辑框图； [18] 图 3是本发明的集成电路的第一实施例的结构示意图；
[19] 图 4是本发明的集成电路的第二实施例的结构示意图；
[20] 图 5是本发明的集成电路的第三实施例的结构示意图。
難
[21] 为了使本发明所要解决的技术问题、 技术方案及有益效果更加清楚明白， 以下 结合附图及实施例， 对本发明进行进一步详细说明。 应当理解， 此处所描述的 具体实施例仅用以解释本发明， 并不用于限定本发明。
[22] 本发明的核心在于， 提供一种釆用横向绝缘栅双极型晶体管 LIGBT (Lateral Insulated-Gate Bipolar
Transistor) 输出级的集成电路结构。 与传统技术相比， 其釆用 LIGBT作为功率 集成电路的输出级， 利用电导调制效应降低电路输出级的导通电阻， 提高输出 级的电流能力， 从而解决传统 LDMOS输出级耐压与导通电阻之间的矛盾。 在相 同功率处理能力吋， 釆用 LIGBT输出级的集成电路面积较釆用 LDMOS输出级的 集成电路面积减小。
[23] 如图 2所示， 图中示出了本发明的釆用 LIGBT输出级的集成电路的一个实施例 。 所示的集成电路包括控制电路 1以及 LDMOS输出级 6与 LIGBT输出级 7， LDMO S输出级 6及 LIGBT输出级 7的栅极与控制电路 1连接。 其中， 在电位相同吋， LD MOS输出级 6的源极与 LIGBT输出级 7的阴极连接， LDMOS输出级 6的漏极与 LIG
BT输出级 7的阳极连接。 本发明利用 LIGBT器件的电导调制效应降低输出级单位 面积的导通电阻， 提高输出级单位面积的电流能力， 从而减小集成电路面积， 节约芯片成本。
[24] 如图 3所示， 所示的控制电路 1以及 LDMOS输出级 6与 LIGBT输出级 7设置于集 成电路模块上。 LDMOS输出级 6包括栅极区、 低压源极区 2及高压漏极区 3， LIG BT输出级 7包括栅极区、 低压阴极区 4及高压阳极区 5。 从图中可以看出， LDMO S输出级 6的栅极区、 源极区 2和漏极区 3分别独立于 LIGBT输出级 7的栅极区、 阳 极区 4和阴极区 5。 然而， 需要注意的是：
[25] 1、 上述 LDMOS低压源极区 2和 LIGBT低压阴极区 4在电位相同吋， 可短接在一 起， 进一步缩小芯片面积， 其中 LIGBT低压阴极区 4和 LDMOS低压源极区 2共用 LDMOS低压源极区 2， 如图 4所示；
[26] 2、 上述 LDMOS和 LIGBT输出级的各电极电位均相同吋， 可釆用如图 5所示的 集成电路结构。 LIGBT低压阴极区 4和 LDMOS低压源极区 2共用 LDMOS低压源极 区 2， LDMOS高压漏极区 3和 LIGBT高压阳极区 5交替构成， 其中 LDMOS高压漏 极区 3和 LIGBT高压阳极区 5的宽度可以相同， 也可以不同。
[27] 本发明的釆用 LIGBT输出级的集成电路利用电导调制效应降低集成电路输出级 的导通电阻， 提高输出级的电流能力， 解决传统 LDMOS输出级耐压与导通电阻 之间的矛盾。 在相同功率处理能力吋， 釆用 LIGBT输出级的集成电路面积较釆用 LDMOS输出级的集成电路面积降低。 这里以高压 N型沟道器件为例 （如图 2所示
Figure imgf000006_0001
[28] 由于器件所有电极均位于芯片表面， 易于通过内部连接实现与低压器件和电路 的单片集成； 并且由于输出级釆用 MOS栅结构， 其驱动电路简单。 釆用 LIGBT 作为集成电路的输出级， 利用电导调制效应降低集成电路输出级的导通电阻， 提高输出级的电流能力， 解决传统 LDMOS输出级耐压与导通电阻之间的矛盾。 在相同功率处理能力吋， 釆用 LIGBT输出级的集成电路面积较釆用 LDMOS输出 级的集成电路面积降低。
[29] LDMOS输出级 6和 LIGBT输出级 7的栅极由控制电路 1的输出信号控制， LDMO S 6禾口 LIGBT
7的栅极可以短接在一起， 也可以由控制电路 1的不同输出信号控制。 LDMOS输 出级 6的漏极和 LIGBT输出级 7的阳极， LDMOS输出级 6的源极和 LIGBT输出级 7 的阴极根据应用要求， 可以短接在一起， 也可以分别连接。 在 LDMOS输出级 6 和 LIGBT输出级 7并联应用吋， 由于 LIGBT器件的电导调制效应， 集成电路输出 级的导通电阻极大降低， 减小了集成电路面积。
[30] 根据本发明， LDMOS输出级 6与 LIGBT输出级 7为 N型沟道器件或者 P型沟道器 件。 此外， 集成电路模块可以由硅材料、 绝缘体硅 SOI (Silicon on
Insulator) 、 氮化硅 SIN (Silicon Nitride) 或者碳化硅 SIC (Silicon
Carbide) 等材料制成。
[31] 本发明的釆用 LIGBT输出级的集成电路， 可以提高集成电路性能： 降低: 路输出级的导通电阻， 提高输出级电流能力， 减小集成电路输出级的导通损耗 。 满足 150V~1200V集成电路对高压输出级的高耐压、 低导通电阻的要求。
[32] 综上所述， 本发明提供的一种釆用 LIGBT输出级的集成电路。 由于器件所有电 极均位于芯片表面， 易于通过内部连接实现与低压器件和电路的单片集成， 并 且其驱动电路简单。 利用电导调制效应降低集成电路输出级的导通电阻， 提高 输出级的电流能力， 解决传统 LDMOS输出级耐压与导通电阻之间的矛盾。 在相 同功率处理能力吋， 釆用 LIGBT输出级的集成电路面积较釆用 LDMOS输出级的 集成电路面积降低。 因此， 釆用本发明可以制作各种性能优良的高压、 高速、 低导通损耗的集成电路。
[33] 以上所述仅为本发明的较佳实施例而已， 并不用以限制本发明， 凡是本发明的 精神和原则之内所作的任何修改、 等同替换和改进等， 均应包含在本发明的保 护范围之内。

Claims

权利要求书
[1] 1、 一种釆用 LIGBT输出级的集成电路， 其特征在于， 包括控制电路 （1) 以及 LDMOS输出级 （6) 与 LIGBT输出级 （7) ， 所述 LDMOS输出级 （6) 及 LIGBT输出级 （7) 的栅极与控制电路 （1) 连接， 其中
在电位相同吋， 所述 LDMOS输出级 (6) 的源极与 LIGBT输出级 （7) 的阴 极连接， 所述 LDMOS输出级 (6) 的漏极与 LIGBT输出级 （7) 的阳极连接
[2] 2、 根据权利要求 1所述的集成电路， 其特征在于， 所述控制电路 （1) 以及
LDMOS输出级 (6) 与 LIGBT输出级 （7) 设置于集成电路模块上。
[3] 3、 根据权利要求 2所述的集成电路， 其特征在于， 所述 LDMOS输出级 (6
) 包括栅极区、 低压源极区 （2) 及高压漏极区 （3) ， 所述 LIGBT输出级 (7) 包括栅极区、 低压阴极区 （4) 及高压阳极区 （5) 。
[4] 4、 根据权利要求 3所述的集成电路， 其特征在于， 所述 LDMOS输出级 (6
) 的低压源极区 （2) 与 LIGBT输出级 （7) 的低压阴极区 (4) 在电位不同 吋不共用。
[5] 5、 根据权利要求 3所述的集成电路， 其特征在于， 所述 LDMOS输出级 (6
) 的低压源极区 （2) 与 LIGBT输出级 （7) 的低压阴极区 (4) 在电位相同 吋共用， 所述 LDMOS输出级 (6) 的高压漏极区 （3) 与 LIGBT输出级 （7 ) 的高压阳极区 （5) 交替构成。
[6] 6、 根据权利要求 5所述的集成电路， 其特征在于， 所述 LDMOS输出级 (6
) 的高压漏极区 （3) 与 LIGBT输出级 （7) 的高压阳极区 （5) 的宽度相同 或者不相同。
[7] 7、 根据权利要求 1至 6任一项所述的集成电路， 其特征在于， 所述 LDMOS 输出级 （6) 与 LIGBT输出级 （7) 为 N型沟道器件或者 P型沟道器件。
[8] 8、 根据权利要求 2所述的集成电路， 其特征在于， 所述集成电路模块由硅 材料、 绝缘体硅、 氮化硅或者碳化硅制成。
PCT/CN2008/073107 2008-11-19 2008-11-19 一种采用ligbt输出级的集成电路 WO2010057340A1 (zh)

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Citations (5)

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Publication number Priority date Publication date Assignee Title
US4901127A (en) * 1988-10-07 1990-02-13 General Electric Company Circuit including a combined insulated gate bipolar transistor/MOSFET
GB2295052A (en) * 1994-11-14 1996-05-15 Fuji Electric Co Ltd Integrated circuits
JP2001257348A (ja) * 2000-03-10 2001-09-21 Denso Corp 半導体装置及びその製造方法
US20080012043A1 (en) * 2006-07-14 2008-01-17 Cambridge Semiconductor Limited Semiconductor device and method of operating a semiconductor device
CN101420219A (zh) * 2008-11-19 2009-04-29 深圳市联德合微电子有限公司 一种采用ligbt输出级的集成电路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4901127A (en) * 1988-10-07 1990-02-13 General Electric Company Circuit including a combined insulated gate bipolar transistor/MOSFET
GB2295052A (en) * 1994-11-14 1996-05-15 Fuji Electric Co Ltd Integrated circuits
JP2001257348A (ja) * 2000-03-10 2001-09-21 Denso Corp 半導体装置及びその製造方法
US20080012043A1 (en) * 2006-07-14 2008-01-17 Cambridge Semiconductor Limited Semiconductor device and method of operating a semiconductor device
CN101420219A (zh) * 2008-11-19 2009-04-29 深圳市联德合微电子有限公司 一种采用ligbt输出级的集成电路

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