WO2010050543A1 - レベルシフタ回路、負荷駆動装置、液晶表示装置 - Google Patents
レベルシフタ回路、負荷駆動装置、液晶表示装置 Download PDFInfo
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- WO2010050543A1 WO2010050543A1 PCT/JP2009/068556 JP2009068556W WO2010050543A1 WO 2010050543 A1 WO2010050543 A1 WO 2010050543A1 JP 2009068556 W JP2009068556 W JP 2009068556W WO 2010050543 A1 WO2010050543 A1 WO 2010050543A1
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- level shifter
- liquid crystal
- signal
- output
- shifter circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018557—Coupling arrangements; Impedance matching circuits
- H03K19/018571—Coupling arrangements; Impedance matching circuits of complementary type, e.g. CMOS
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3614—Control of polarity reversal in general
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
Definitions
- the present invention relates to a level shifter circuit, a load driving device (for example, a liquid crystal driving device) and a liquid crystal display device using the level shifter circuit.
- FIG. 6 is a circuit diagram showing a conventional example of a level shifter circuit.
- the conventional level shifter circuit includes inverters INVa and INVb, P-channel MOS field effects Pa to Pd, and N-channel MOS field effect transistors Na to Nd. It had been.
- the inverters INVa and INVb are respectively provided between the application terminal of the positive potential VDDI (for example, 1.6 [V]) and the application terminal of the ground potential VSS (0 [V]).
- the transistors Pa, Pb, Na, and Nb are connected between the application terminal of the positive potential VDDI and the application terminal of the negative potential MVDD (for example, ⁇ 6.0 [V]), respectively.
- Pc, Pd, Nc, and Nd were connected between the application terminal of the ground potential VSS and the application terminal of the negative potential MVDD, respectively.
- Patent Document 1 can be cited as an example of the related art related to the above.
- an input signal IN pulse-driven between the ground potential VSS and the positive potential VDDI is used as an output signal OUT pulse-driven between the ground potential VSS and the negative potential MVDD. Can be output after being converted to.
- the conventional level shifter circuit is configured to receive the input signal IN pulse-driven between the ground potential VSS and the positive potential VDDI at the gates of the P-channel MOS field effect transistors Pa and Pb. In order to reliably turn on and off Pa and Pb, it is necessary to apply the positive potential VDDI instead of the ground potential VSS to the sources of the transistors Pa and Pb.
- the gates and sources of the transistors Pa to Pc and the transistors Na to Nc, the gates and drains, or the source and source Since a maximum potential difference (for example, 7.6 [V]) between the positive potential VDDI and the negative potential MVDD is applied between the drains, the above-described potential difference is applied to the transistors Pa to Pc and the transistors Na to Nc.
- a high breakdown voltage element for example, 28 [V] breakdown voltage
- the high withstand voltage element has a larger gate capacity than a medium withstand voltage element (for example, 6 [V] withstand voltage) or a low withstand voltage element (for example, 1.8 [V] withstand voltage) having a lower withstand voltage. Since a large amount of current is required, the ON / OFF response speed is reduced and the through current is increased accordingly (as a result, the operating current consumed in the entire level shifter circuit is increased).
- a medium withstand voltage element for example, 6 [V] withstand voltage
- a low withstand voltage element for example, 1.8 [V] withstand voltage
- the high breakdown voltage element has a large layout area compared to the medium breakdown voltage element and the low breakdown voltage element, which has hindered miniaturization of the semiconductor device.
- the level shifter circuit is enlarged in the width direction (long side direction) due to the PAD pitch limitation. Therefore, in order to secure the layout area, the level shifter circuit has to be enlarged in the vertical direction (short side direction), and it is difficult to meet the demand for a framed LCD panel. .
- the present invention is a level shifter circuit capable of realizing reduction of power consumption, improvement of response speed, and reduction of layout area, while minimizing the number of high voltage elements used, and
- An object is to provide a load driving device and a liquid crystal display device using the same.
- a level shifter circuit uses a differential input stage comprising a pair of N-channel field effect transistors connected between a ground potential application terminal and a negative potential application terminal. An input signal pulsed between the ground potential and the positive potential is received in a differential format and differentially amplified to thereby output a pulse drive between the ground potential and the negative potential. It is set as the structure (1st structure) which has the differential amplifier which produces
- the pair of N-channel field effect transistors forming the differential input stage among the plurality of transistors forming the level shifter circuit includes the positive potential and the negative potential.
- a high-breakdown-voltage element that can withstand a potential difference from the potential is used, and the remaining transistors are preferably a medium-breakdown-voltage element or a low-breakdown-voltage element with a lower breakdown voltage (second configuration).
- the level shifter circuit having the second configuration samples an enable control unit for turning on / off the differential amplifier according to a first control signal, and samples an output signal of the differential amplifier according to a second control signal.
- / Latch output unit for holding (third configuration).
- the load driving device includes m level shifter circuits that level-shift m input signals (m is an integer of 2 or more) to generate m output signals; A digital / analog conversion circuit that receives a signal as an m-bit digital signal, converts the signal into an analog signal, and outputs the analog signal; and an amplifier circuit that supplies the analog signal to the load as a load drive signal; An integer greater than or equal to 1) of the plurality of level shifter circuits, wherein an input signal that is pulse-driven between a ground potential and a positive potential is transmitted between the ground potential and the negative potential.
- the level shifter circuit for converting to a pulse-driven output signal has a configuration (fourth configuration) which is a level shifter circuit having the third configuration.
- the load driving device having the fourth configuration generates first and second control signals that are pulse-driven between the ground potential and the negative potential, and outputs them to the plurality of level shifter circuits.
- the shared level shifter circuit may be configured (fifth configuration).
- the load may be configured to be a liquid crystal pixel (sixth configuration).
- the liquid crystal display device may have a configuration (seventh configuration) including the load driving device having the sixth configuration and a liquid crystal pixel driven by the load driving device. .
- the liquid crystal display device having the seventh configuration distributes n system output signals output from the load driving device to each of the z systems (z is an integer of 1 or more) (n ⁇ z) systems.
- the output signal may be generated and a multiplexer (8th configuration) for supplying the output signal to the liquid crystal pixel may be used.
- the load driving device includes a multiplexer timing generator that performs timing control of the multiplexer in accordance with the generation operation of the n systems of output signals ( The ninth configuration may be used.
- the power consumption can be reduced, the response speed can be improved, and the layout area can be reduced while minimizing the number of high voltage elements used. It becomes possible.
- FIG. 1 is a schematic diagram showing a first configuration example of a liquid crystal display device using a level shifter circuit according to the present invention.
- the liquid crystal display device of this configuration example includes a glass substrate 10, a logic unit 20, and a flexible cable 30.
- liquid crystal pixels 11 are formed, and a liquid crystal driving device 12 (liquid crystal driver IC) is directly mounted on the blank area (frame area) by the COG [Chip On Glass] method.
- liquid crystal driving device 12 liquid crystal driver IC
- the liquid crystal driving device 12 includes a source driver unit, a gate driver unit, a common driver unit, and the like as means for driving the liquid crystal pixels 11, and in particular, the source driver unit of the liquid crystal driving device 12 is illustrated in FIG. As shown in the figure, a level shifter circuit group 121, a digital / analog conversion circuit group 122, and a source amplifier group 123 are provided.
- the source driver unit of the liquid crystal driving device 12 includes m level shifters for level-shifting m system input signals (where m is an integer of 2 or more) to generate m system output signals.
- the circuit (depicted as a single block element labeled “LS ⁇ m” in the example of FIG. 1) and the m output signals are received as m-bit digital signals and converted into analog signals.
- a digital / analog conversion circuit in the example of FIG. 1, depicted as a block element labeled “DAC”), and a source amplifier circuit (FIG. 1) that supplies the analog signal to the liquid crystal pixel 11 as a source signal.
- AMP block element labeled
- n sets where n is an integer of 1 or more).
- the source signal supplied to the liquid crystal pixel 11 as the liquid crystal driving signal is inverted in polarity between every predetermined frame from the viewpoint of preventing the liquid crystal pixel 11 from being burned. Therefore, in the liquid crystal drive device 12 of the present embodiment, the first drive system (positive level shifter circuit, digital / analog conversion) that generates a positive source signal in accordance with an input signal (video signal) from the logic unit 20. Circuit and source amplifier circuit) and a second drive system (negative level shifter circuit, digital / analog conversion circuit, and source amplifier circuit) for generating a negative polarity source signal are prepared separately. A configuration is adopted in which the liquid crystal pixels 11 are driven while alternately switching the.
- the level shifter circuit according to the present invention is suitably used as the above-described negative level shifter circuit, and the configuration thereof will be described later in detail.
- the logic unit 20 is connected to the liquid crystal driving device 12 on the glass substrate 10 through the flexible cable 30, and the control signal (source signal, gate signal, common signal, etc.) of the liquid crystal pixel 11 through the liquid crystal driving device 12. ) Is output.
- the flexible cable 30 is a signal transmission path in which printed wiring is formed on a flexible thin film, and connectors for establishing electrical connection with the liquid crystal driving device 12 and the logic unit 20 are provided at both ends thereof. It has been.
- the configuration in which the liquid crystal driving device 12 is mounted on the glass substrate 10 by the COG method is described as an example.
- the configuration of the present invention is not limited to this, and the configuration is not limited to this.
- the liquid crystal driving device 12 may be mounted by a COF [Chip On Film] method.
- FIG. 2 is a circuit diagram showing a first embodiment of the level shifter circuit according to the present invention.
- the level shifter circuit according to the present embodiment has an input signal IN (pulse-driven between a ground potential VSS (0 [V]) and a positive potential VDDI (for example, 1.6 [V]).
- Video signal from the logic unit 20) is converted into an output signal OUT that is pulse-driven between a ground potential VSS and a negative potential MVDD (for example, ⁇ 6.0 [V]).
- a differential amplifier 2 and an output buffer 3 are provided.
- the input buffer 1 includes inverters INV1 and INV2.
- the differential amplifier 2 includes P-channel MOS field effects P1 to P3 and N-channel MOS field effect transistors N1 to N4.
- the output buffer 3 includes an inverter INV3.
- the input end of the inverter INV1 is connected to the application end of the input signal IN.
- the input terminal of the inverter INV2 is connected to the output terminal of the inverter INV1.
- the first power supply terminals of the inverters INV1 and INV2 are both connected to the application terminal for the positive potential VDDI.
- the second power supply terminals of the inverters INV1 and INV2 are both connected to the application terminal of the ground potential VSS.
- the sources of the transistors P1 and P2 are both connected to the application terminal of the ground potential VSS.
- the gates of the transistors P1 and P2 are both connected to the drain of the transistor P1.
- the drains of the transistors N1 and N2 are connected to the drains of the transistors P1 and P2, respectively.
- the gate of the transistor N1 is connected to the output terminal of the inverter INV2.
- the gate of the transistor N2 is connected to the output terminal of the inverter INV1.
- the sources of the transistors N1 and N2 are both connected to the drain of the transistor N3.
- the gate of the transistor N3 is connected to the application terminal for the bias potential BIAS.
- the drain of the transistor N3 is connected to the application terminal for the negative potential MVDD.
- the source of the transistor P3 is connected to the application terminal of the ground potential VSS.
- the gate of the transistor P3 is connected to the drain of the transistor P2.
- the drain of the transistor P3 is connected to the drain of the transistor N4.
- the gate of the transistor N4 is connected to the application terminal for the bias potential BIAS.
- the source of the transistor N4 is connected to the application terminal for the negative potential MVDD.
- the input terminal of the inverter INV3 is connected to the drain of the transistor P3.
- the output terminal of the inverter INV3 is connected to the output terminal of the output signal OUT.
- the first power supply terminal of the inverter INV3 is connected to the application terminal of the ground potential VSS.
- the second power supply terminal of the inverter INV3 is connected to the application terminal of the negative potential MVDD.
- the operation of the level shifter circuit configured as described above will be described.
- the high level (VDDI) is applied to the gate of the transistor N1
- the low level (VSS) is applied to the gate of the transistor N2.
- the current flowing through the transistor N1 increases and the current flowing through the transistor N2 decreases.
- the gate potential of the transistor P3 increases and the drain potential of the transistor P3 (the output level of the differential amplifier 2) decreases. Therefore, the final output signal OUT output via the inverter INV3 is at a high level (VSS).
- the input signal IN is at the low level (VSS)
- the low level (VSS) is applied to the gate of the transistor N1
- the high level (VDDI) is applied to the gate of the transistor N2, so that the current flows to the transistor N1.
- the current decreases and the current flowing through the transistor N2 increases.
- the gate potential of the transistor P3 decreases, and the drain potential of the transistor P3 (output level of the differential amplifier 2) increases. Therefore, the final output signal OUT output via the inverter INV3 is at a low level (MVDD).
- the level shifter circuit configured as described above receives the input signal IN (video signal from the logic unit 20) that is pulse-driven between the ground potential VSS and the positive potential VDDI as the ground potential VSS and the negative potential MVDD. It is converted into an output signal OUT that is pulse-driven between and output.
- the potential difference between the positive potential VDDI and the negative potential MVDD (maximum) between the gate and the source of the transistors N1 and N2 forming the differential amplifier 2 (particularly the differential input stage) (for example, 7.6 [V]) is applied. Therefore, it is necessary to use a high breakdown voltage element (for example, 28 [V] breakdown voltage) that can withstand the transistors N1 and N2, but the differential amplifier 2 is formed.
- a high breakdown voltage element for example, 28 [V] breakdown voltage
- the ground potential VSS is negative. Since only a potential difference (for example, 6.0 [V]) from the potential MVDD is applied, these transistors have a medium withstand voltage element having a lower withstand voltage. It is possible to use (for example, 6.0 [V] tolerance).
- the differential input including the pair of N-channel field effect transistors N1 and N2 connected between the application terminal of the ground potential VSS and the application terminal of the negative potential MVDD.
- the input signal IN pulse-driven between the ground potential VSS and the positive potential VDDI is received in a differential format, and is differentially amplified so that it is between the ground potential VSS and the negative potential MVDD.
- the number of high voltage elements is reduced as much as possible, power consumption is reduced, response speed is improved, and layout is performed. It is possible to reduce the area.
- the liquid crystal drive device 12 can be reduced by using the level shifter circuit of this embodiment. Since shrinking can be performed in the vertical direction (short side direction), it is possible to reduce the chip cost of the liquid crystal driving device 12 (for example, about 30%), and to meet the demand for a framed liquid crystal panel. It becomes possible to respond.
- FIG. 3 is a circuit diagram showing a second embodiment of the level shifter circuit according to the present invention.
- the level shifter circuit of the second embodiment is a further improvement based on the first embodiment. Therefore, the same components as those in the first embodiment are denoted by the same reference numerals as those in FIG. 2, thereby omitting a redundant description. In the following, description will be given with an emphasis on the components unique to the second embodiment. Do.
- the level shifter circuit includes an enable control unit that turns on / off the differential amplifier 2 according to the amplifier enable signal EN1 in addition to the components of the first embodiment described above. 4 and a latch unit 5 that samples / holds the output signal of the differential amplifier 2 in response to the latch enable signal EN2.
- the enable control unit 4 includes P-channel MOS field effect transistors P4 to P6 and an N-channel MOS field effect transistor N5.
- the latch unit 5 includes an inverter INV5, a three-state inverter INV6, and a pass switch SW1. Further, an inverter INV4 is added to the output buffer 3 for the purpose of logical matching of the output signal OUT.
- the source of the transistor P4 is connected to the application terminal of the ground potential VSS.
- the gate of the transistor P4 is connected to the application end of the amplifier enable signal EN1.
- the drain of the transistor P4 is connected to the gate of the transistor P3.
- the source of the transistor P5 is connected to the application terminal of the ground potential VSS.
- the gate of the transistor P5 is connected to the application end of the amplifier enable signal EN1.
- the drain of the transistor P5 is connected to the drain of the transistor P3.
- the transistor P6 is inserted between the application terminal of the bias potential BIAS and the gates of the transistors N3 and N4.
- the gate of the transistor P6 is connected to the application terminal of the inverting amplifier enable signal EN1B (logic inversion signal of the amplifier enable signal EN1).
- the drain of the transistor N5 is connected to the gates of the transistors N3 and N4.
- the gate of the transistor N5 is connected to the application terminal of the inverting amplifier enable signal EN1B.
- the source of the transistor N5 is connected to the application terminal for the negative potential MVDD.
- the input terminal of the inverter INV5 is connected to the drain of the transistor P3 via the pass switch SW1.
- the output terminal of the inverter INV5 is connected to the input terminal of the inverter INV3.
- the input terminal of the three-state inverter INV6 is connected to the output terminal of the inverter INV5.
- the output terminal of the three-state inverter INV5 is connected to the input terminal of the inverter INV5.
- the first power supply terminals of the inverter INV5 and the three-state inverter INV6 are both connected to the application terminal of the ground potential VSS.
- the second power supply terminals of the inverter INV5 and the three-state inverter INV6 are both connected to the application terminal for the negative potential MVDD.
- the control terminals of the pass switch SW1 and the three-state inverter INV5 are connected to the application terminal of the latch enable signal EN2, respectively.
- the inverter INV4 is inserted between the output terminal of the inverter INV3 and the output terminal of the output signal OUT.
- the first power supply terminal of the inverter INV4 is connected to the application terminal of the ground potential VSS.
- the second power supply terminal of the inverter INV4 is connected to the application terminal of the negative potential MVDD.
- FIG. 4 is a timing chart showing an example of the amplifier enable signal EN1 and the latch enable signal EN2.
- the input signal IN, the amplifier enable signal EN1, and the latch enable signal EN2 are shown in order from the top.
- the logic unit 20 sets both the amplifier enable signal EN1 and the latch enable signal EN2 to a low level based on the recognition that the data of the input signal IN is unchanged until the time t1 arrives. Level.
- the enable control unit 4 since the transistors P4 and P5 and the transistor N5 are all turned on and the transistor P6 is turned off, the supply of the operating current to the differential amplifier 2 is interrupted, and the differential amplifier 2 Output logic (drain potential of the transistor P3) is fixed.
- the pass switch SW1 is cut off and the output of the three-state inverter INV6 is permitted to form a loop including the inverter 5 and the three-state inverter 6, and the output of the differential amplifier 2 The logic is latched.
- the logic unit 20 changes only the amplifier enable signal EN1 to the high level prior to the data update of the input signal IN.
- the enable control unit 4 since the transistors P4 and P5 and the transistor N5 are all turned off and the transistor P6 is turned on, the supply of the operating current to the differential amplifier 2 is resumed, and the differential amplifier 2
- the output logic (the drain potential of the transistor P3) becomes variable according to the input signal IN.
- the timing for starting the differential amplifier 2 may be appropriately set in consideration of the time required for starting the differential amplifier 2.
- the logic unit 20 updates the data of the input signal IN, while changing the latch enable signal EN2 to high level.
- the pass switch SW1 is turned on and the output of the three-state inverter INV6 is disabled (high impedance state), so that the output logic of the differential amplifier 2 passes through the inverter INV5.
- the logic unit 20 sets both the amplifier enable signal EN1 and the latch enable signal EN2 to the low level based on the recognition that the data of the input signal IN is unchanged.
- the differential amplifier 2 is stopped, and the output logic of the differential amplifier 2 is latched in the latch unit 5. Note that the timing at which the differential amplifier 2 is stopped may be appropriately set in consideration of the time required for the sample / hold operation of the latch unit 5.
- the level shifter circuit according to the second embodiment when the level shifter circuit is not used (when the data of the input signal IN is not changed), the supply of the operating current to the differential amplifier 2 is interrupted, and the differential amplifier 2 Since the output logic can be held by the latch unit 5 at the subsequent stage, it is possible to realize a reduction in power consumption (for example, about 1/5 of the conventional level).
- the level shifter circuit of the second embodiment is suitable for mounting on an IC that is driven by a battery.
- the liquid crystal driving device 12 of the present embodiment shifts the level of a control signal that is pulse-driven between the positive potential VDDI and the ground potential VSS, thereby causing the ground potential VSS and the negative potential MVDD to be shifted.
- shared level shifter circuits 124a and 124b that generate an amplifier enable signal EN1 and a latch enable signal EN2 that are pulse-driven between the first and second level shifters and output them to a plurality of level shifter circuits. With this configuration, it is possible to minimize the number of shared level shifter circuits 124a and 124b that need to be operated at all times.
- FIG. 7 is a block diagram showing a second configuration example of the liquid crystal display device using the level shifter circuit according to the present invention.
- the liquid crystal display device of this configuration example (or an application such as a mobile phone terminal equipped with this) includes a liquid crystal display panel A1, a multiplexer A2, a source driver circuit A3, and a gate driver circuit A4.
- the liquid crystal display panel A1 is a TFT [Thin Film Transistor] that uses a liquid crystal element whose light transmittance changes according to the voltage value of display data (analog voltage signal) supplied from the source driver circuit A3 via the multiplexer A2 as a pixel. ] Video output means.
- the multiplexer A2 distributes the n display data output from the source driver circuit A3 to each of the z systems (z is an integer of 1 or more) based on the timing signal input from the source driver circuit A3 (n Xz) System display data is generated and supplied to the liquid crystal display panel A1.
- the source driver circuit A3 converts display data in digital format input from the video source A7 into display data in analog format (analog voltage signal), and converts this to each pixel (more accurately in the liquid crystal display panel A1 via the multiplexer A2). Is supplied to the source terminal of the active element connected to each pixel of the liquid crystal display panel A1.
- the source driver circuit A3 has a function of receiving an input of a command or the like from the MPUA 6, a function of supplying power to each part of the liquid crystal display device (such as the multiplexer A2), each part of the liquid crystal display device (the multiplexer A2, the gate driver circuit A4, and the external A function of controlling the timing of the DC / DC converter A5) and a function of supplying a common voltage to the liquid crystal display panel A1.
- the gate driver circuit A4 performs vertical scanning control of the liquid crystal display panel A1 based on the timing signal input from the source driver circuit A3.
- the external DC / DC converter A5 generates a power supply voltage necessary for driving the gate driver circuit A4 based on the timing signal input from the source driver circuit A3.
- the MPUA 6 is a main body that controls the entire set on which the liquid crystal display device is mounted, and supplies various commands, clock signals, simple display data used in the 8-color display mode, and the like to the source driver circuit A3.
- the video source A7 supplies display data and a clock signal used in the normal display mode to the source driver circuit A3.
- FIG. 8 is a block diagram showing a configuration example of the source driver circuit A3.
- the source driver circuit A3 of this configuration example includes an MPU interface B1, a command decoder B2, a data register B3, a partial display data RAM [Random Access Memory] B4, and a data control unit B5.
- the MPU interface B1 exchanges various commands, clock signals, simple display data used in the 8-color display mode, and the like with the MPUA 6.
- the command decoder B2 performs a decoding process on commands and simple display data acquired via the MPU interface B1.
- the data register B3 temporarily stores various setting data acquired via the MPU interface B1 and initial setting data read from the OTPROMB10.
- the partial display data RAMB4 is used as a development destination of simple display data.
- the data control unit B5 performs read control of the simple display data developed in the partial display data RAM B4.
- the display data interface B6 exchanges display data and clock signals used in the normal display mode with the video source A7.
- the image processing unit B7 performs predetermined image processing (luminance dynamic range correction, color correction, various noise removal corrections, etc.) on the display data input via the display data interface B6.
- predetermined image processing luminance dynamic range correction, color correction, various noise removal corrections, etc.
- the data latch unit B8 latches display data input through the image processing unit B7 or simple display data input through the data control unit B5.
- the source driver unit B9 controls the driving of the liquid crystal display panel A1 based on display data or simple display data input via the data latch unit B8.
- the OTPROMB 10 stores the initial setting data to be stored in the data register B3 in a nonvolatile manner. Note that data can be written to the OTPROMB 10 only once.
- the control register B11 temporarily stores the command acquired by the command decoder B2 and simple display data.
- the address counter B12 reads the simple display data temporarily stored in the control register B11 based on the timing signal generated by the timing generator B13, and writes it in the partial display data RAM B4.
- the timing generator B13 generates a timing signal necessary for synchronous control of the entire liquid crystal display device based on the internal clock signal input from the oscillator B14, and each part of the source driver circuit A3 (data latch unit B8, address counter B12, Common voltage generator B15, multiplexer timing generator B16, gate driver timing generator B17, external DC / DC timing generator B18, and liquid crystal display power supply circuit B19).
- the oscillator B14 generates an internal clock signal having a predetermined frequency and supplies it to the timing generator B13.
- the common voltage generator B15 generates a common voltage based on the timing signal input from the timing generator B13, and supplies it to the liquid crystal display panel A1.
- the multiplexer timing generator B16 generates a multiplexer timing signal based on the timing signal input from the timing generator B13, and supplies this to the multiplexer A2.
- the gate driver timing generator B17 generates a gate driver timing signal based on the timing signal input from the timing generator B13, and supplies this to the gate driver circuit A4.
- the external DC / DC timing generator B18 generates an external DC / DC timing signal based on the timing signal input from the timing generator B13, and supplies this to the external DC / DC converter A5.
- the power supply circuit B19 for liquid crystal display device generates a power supply voltage for the liquid crystal display device based on the timing signal input from the timing generator B13, and supplies it to each part (such as the multiplexer A2) of the liquid crystal display device.
- FIG. 9 is a block diagram illustrating a configuration example of the source driver unit B9. As shown in FIG. 9, the source driver unit B9 of this configuration example controls the polarity inversion of the output signal applied to the liquid crystal element when the liquid crystal display panel A1 is driven.
- the level shifter circuits C1 (1) to C1 (n) respectively shift the level of the m-bit display data input from the data latch unit B8 and transmit it to the subsequent stage.
- This is a positive level shifter circuit that converts the output signal into a pulse driven output signal.
- the level shifter circuits C1 (1) to C1 (n) have m level shifter circuits connected in parallel so that m-bit display data can be received in parallel. Further, the circuit configuration of the present invention described with reference to FIGS. 2 to 3 can be applied to the negative level shifter circuit C1 (j).
- Digital / analog conversion circuits C2 (1) to C2 (n) convert m-bit display data input via the level shifter circuits C1 (1) to C1 (n) into analog signals and output the analog signals.
- the odd-numbered digital / analog conversion circuit C2 (i) is driven between the ground potential and the positive potential, and the digital display data is converted into analog display data (positive voltage). Convert.
- the first gradation voltage (positive polarity) of 2 m gradation is input to the digital / analog conversion circuit C2 (i) from the first gradation voltage generation unit C16. That is, the analog format display data generated by the digital / analog conversion circuit C2 (i) has a 2 m gradation according to the digital format display data (m bits) input from the level shifter circuit C1 (i). Any one of the first gradation voltages (positive polarity) is selected.
- the digital / analog conversion circuit C2 (j) in the even-numbered column is driven between a ground potential and a negative potential, and converts digital display data into analog display data (negative voltage).
- the second gradation voltage (negative polarity) of 2 m gradation is input to the digital / analog conversion circuit C2 (j) from the second gradation voltage generation unit C17. That is, the analog format display data generated by the digital / analog conversion circuit C2 (j) has 2 m gradations in accordance with the digital format display data (m bits) input from the level shifter circuit C1 (j). Any one of the second gradation voltages (negative polarity) is selected.
- the source amplifier circuits C3 (1) to C3 (n) amplify the analog display data generated by the digital / analog conversion circuits C2 (1) to C2 (n) and output them to the subsequent stage.
- the source amplifier circuit C3 (i) in the odd-numbered column is driven between the ground potential and the positive potential, and display data (positive signal) input from the digital / analog conversion circuit C2 (i). The current capability is increased and output to the subsequent stage.
- the source amplifier circuit C3 (j) in the even-numbered column is driven between a ground potential and a negative potential, and has a current capability of display data (negative signal) input from the digital / analog conversion circuit C2 (j). Increase and output to later stage.
- the polarity inversion control path switches C4 (1) to C4 (n) are respectively connected between the output terminals C6 (i) and C6 (j) adjacent to each other in the positive polarity circuits (C1 (i) to C3 ( i)) and the negative polarity circuits (C1 (j) to C3 (j)) to be shared one by one, the source amplifier circuits C3 (i) and C3 (j) and the output terminals C6 (i) and C6 (j ) Switch the connection relationship.
- the source amplifier circuit C3 (i) and the output terminal C6 (i) are connected, and the source amplifier C3 (j) and the output terminal C6 (j) are connected.
- On / off control of the path switches C4 (1) to C4 (n) is performed.
- a positive analog signal generated by the odd-numbered column source amplifier C3 (i). Is selected, and the negative analog signal generated by the even-numbered source amplifier C3 (j) is selected as the output signal output to the liquid crystal element from the even-numbered output terminal C6 (j).
- the source amplifier circuit C3 (i) and the output terminal C6 (j) are connected, and the source amplifier C3 (j) and the output terminal C6 (i) are connected.
- switches C4 (1) to C4 (n) is performed.
- the negative polarity analog signal generated by the even-numbered column source amplifier C3 (j). Is selected, and the positive analog signal generated by the odd-numbered source amplifier C3 (i) is selected as the output signal output from the even-numbered output terminal C6 (j) to the liquid crystal element.
- the common voltage of the liquid crystal display panel A1 (the voltage that is commonly applied to the counter electrodes of all liquid crystal elements) can be fixed to the ground potential. It is not necessary to charge / discharge the opposing capacitance of the liquid crystal display panel A1, and it is possible to reduce power consumption.
- the positive polarity circuits (C1 (i) to C3 (i)) are respectively connected between the output terminals C6 (i) and C6 (j) adjacent to each other. Since the negative polarity circuits (C1 (j) to C3 (j)) can be shared one by one, it is possible to contribute to the downsizing (chip area reduction) of the source driver circuit A3.
- the 8-color display mode path switches C5 (1) to C5 (n) are connected to the output terminal C6 (1) in the 8-color display mode (an operation mode in which video display is performed based on the simple display data input from the MPUA 6). From C6 (n), it is used when outputting a binary voltage of only high level / low level, not a gradation voltage of 2 m gradation. More specifically, the odd-color eight-color display mode pass switch C5 (i) includes a first pass switch connected between the output terminal of the source amplifier C3 (i) and the positive voltage application terminal; It has a second pass switch connected between the output terminal of the source amplifier C3 (i) and the ground potential application terminal, and outputs either a positive potential or a ground potential based on the simplified display data.
- the even-numbered 8-color display mode pass switch C5 (j) includes a third pass switch connected between the output terminal of the source amplifier C3 (j) and the negative potential application terminal, and the source amplifier C3 ( j) having a fourth pass switch connected between the output terminal and the ground potential application terminal, and outputting either one of the negative potential and the ground potential based on the simplified display data. 1.
- On / off control of the second path switch is performed exclusively (complementary).
- the level shifter circuits C1 (1) to C1 (n), the digital / analog conversion circuits C2 (1) to C2 (n), and the source amplifier circuits C3 (1) to C3 (n) The power supply is cut off and each operation is stopped. With such a configuration, unnecessary power consumption can be reduced in the 8-color display mode.
- Output terminals C6 (1) to C6 (n) are external terminals for supplying n-system output signals from the source driver circuit A3 to the multiplexer A2.
- the resistance ladder C7 generates a plurality of divided voltages by dividing a predetermined reference voltage (Vref) by resistance.
- the selectors C8 to C11 each select one from a plurality of divided voltages generated by the resistance ladder C7. Note that the divided voltage selected by the selector C8 and the divided voltage selected by the selector C9 have different voltage values. Also, the divided voltage selected by the selector C10 and the divided voltage selected by the selector C11 have different voltage values.
- the amplifiers C12 and C13 are all driven between a ground potential and a positive potential, and amplify the divided voltages respectively input from the selectors C8 and C9 to generate positive first and second amplified voltages.
- the amplifiers C14 and C15 are both driven between a ground potential and a negative potential, and amplify the divided voltages respectively input from the selectors C10 and C11 to generate negative third and fourth amplified voltages.
- the first gradation voltage generation unit C16 is a 2 m floor that discretely changes between a positive first amplification voltage input from the amplifier C12 and a positive second amplification voltage input from the amplifier C13. A first gradation voltage (positive polarity) is generated.
- the second gradation voltage generation unit C17 is a 2 m floor that discretely changes between the negative third amplified voltage input from the amplifier C14 and the negative fourth amplified voltage input from the amplifier C15. A tone second gradation voltage (negative polarity) is generated.
- the output capacitors C18 to C21 are connected to the output terminals of the amplifiers C12 to C15, respectively, and smooth the first to fourth amplification voltages.
- FIGS. 10A and 10B are schematic diagrams showing a first connection form and a second connection form of the liquid crystal display panel A1 and the source driver circuit A3, respectively.
- the depiction of the multiplexer A2 is omitted for the sake of simplicity.
- the source driver circuit A3 has a function of changing the output sequence of the source signal in accordance with the wiring state so as to correspond to two types of wiring selection.
- a liquid crystal display is provided from an output terminal provided between the long side center portion of the source driver circuit A3 and one long side end portion (upper end portion on the paper surface).
- the source signal S0 / S1 for the 0th column / first column of the panel A1,... 236th / 237th column source signals S236 / S237 are sequentially output, and the other side center portion of the source driver circuit A3 and the other side From the output terminal provided between the long side end portion (the lower end portion on the paper) of the second row / third row source signal S2 / S3 of the liquid crystal display panel A1,... 238th row / 239 Column source signals S238 / S239 are sequentially output. That is, in the wiring state of FIG. 10A, the source signals are alternately and sequentially allocated on both sides of the source driver circuit A3 with the central portion of the long side as a boundary.
- the 0th column of the liquid crystal display panel A1 from the output terminal provided between the central portion of the long side of the source driver circuit A3 and one long side end (upper end on the paper surface), the 0th column of the liquid crystal display panel A1.
- the 118th / 119th column source signals S118 / S119 are sequentially output, and the long side center of the source driver circuit A3 and the other long side end.
- the 120th / 121st row source signal S120 / S121 of the liquid crystal display panel A1 From the output terminal provided between (the lower end of the page), the 120th / 121st row source signal S120 / S121 of the liquid crystal display panel A1, the 238th / 239th row source signal S238 / S239 are sequentially output.
- the first half of the source signal is sequentially allocated to one long side end side with the long side center portion of the source driver circuit A3 as a boundary, and the other long side end side to the other side.
- the latter half of the source signal is assigned sequentially.
- the source driver circuit A3 having such an output sequence change function can perform flexible wiring selection according to user needs.
- FIG. 11 is a block diagram for explaining the timing control of the source driver circuit A3.
- the source driver circuit A3 includes an oscillator D1, a timing generator D2, a display data interface D3, an address counter (RAM controller) D4, a partial display data RAM D5, and a source data timing controller D6.
- a new code is additionally attached to the function block already shown in FIG. 8.
- the oscillator D1 (corresponding to the oscillator B14 in FIG. 7) generates an internal clock signal having a predetermined frequency and supplies it to the timing generator D2.
- the timing generator D2 (corresponding to the timing generator B13 in FIG. 7) is based on the internal clock signal input from the oscillator D1 or the external clock signal input via the display data interface D3. Timing signals necessary for synchronization control are generated, and each part of the source driver circuit A3 (address counter D4, source data timing controller D6, OTP controller D8, external DC / DC timing generator D9, multiplexer / gate driver timing generator D10, And the power supply circuit D11) for the liquid crystal display device.
- the source driver circuit A3 address counter D4, source data timing controller D6, OTP controller D8, external DC / DC timing generator D9, multiplexer / gate driver timing generator D10, And the power supply circuit D11
- the display data interface D3 (corresponding to the display data interface B6 in FIG. 7) exchanges display data and clock signals used in the normal display mode with the video source A7.
- the display data interface D3 supplies an external clock signal input from the video source A7 to the timing generator D2.
- the address counter D4 (corresponding to the address counter B12 in FIG. 7) reads the simple display data temporarily stored in the control register (not shown in FIG. 11) based on the timing signal generated by the timing generator D2. This is written into the partial display data RAMD5.
- the partial display data RAMD5 (corresponding to the partial display data RAMB4 in FIG. 8) is used as a development destination of the simple display data.
- the source data timing controller D6 (corresponding to the data control unit B5 and the data latch unit B8 in FIG. 7) displays display data input from the display data interface D3 based on the timing signal generated by the timing generator D2.
- the simple display data developed in the partial display data RAMD5 is latched and output to the source driver unit (not shown in FIG. 11).
- OTPROMD 7 (corresponding to OTPROMB 10 in FIG. 7) stores initial setting data to be stored in a data register (not shown in FIG. 11) in a nonvolatile manner. Note that data can be written to the OTPROMD 7 only once.
- the OTP controller D8 performs access control to the OTPROMD 7 based on the timing signal generated by the timing generator D2.
- the external DC / DC timing generator D9 (corresponding to the external DC / DC timing generator B18 in FIG. 7) generates an external DC / DC timing signal based on the timing signal input from the timing generator D2. This is supplied to the external DC / DC converter A5.
- the multiplexer / gate driver timing generator D10 (corresponding to the multiplexer timing generator B16 and the gate driver timing generator B17 in FIG. 7), based on the timing signal input from the timing generator D2, Then, timing signals for the gate driver are respectively generated and supplied to the multiplexer A2 and the gate driver circuit A4.
- the liquid crystal display panel power supply circuit D11 (corresponding to the liquid crystal display device power supply circuit B19 in FIG. 7) generates a power supply voltage for the liquid crystal display device based on the timing signal input from the timing generator D2, and uses this to generate the liquid crystal. This is supplied to each part of the display device (such as multiplexer A2).
- FIG. 12 is a table showing an example of oscillation characteristics. As shown in the figure, the oscillation frequency fosc1 of the internal clock signal generated by the oscillator D1 is guaranteed to be 5 MHz (typ.).
- FIG. 13A and FIG. 13B are timing charts showing a first operation example and a second operation example in the 8-color display mode, respectively, and in order from the top, a chip select signal SCEX, a reset signal RESX, a data signal SDI, and a clock signal. SCL is depicted.
- the breakdown of the data signal SDI is that the first 1 bit is a data / command designation flag, the subsequent 2 bits are empty data, the subsequent 3 bits are the xth (final) pixel data (RGB), and the subsequent 3 bits This pixel data is ignored.
- the 3-bit pixel data (RGB) described above is used for switching control of the 8-color display mode path switches C5 (1) to C5 (n) shown in FIG.
- the reset operation of the source driver circuit A3 There are two types of reset methods for the source driver circuit A3: hardware reset and software reset.
- hardware reset initialization is performed according to the voltage level of the RESX terminal. When the RESX terminal is set to the low level, the reset state is immediately set regardless of the operation state inside the source driver circuit A3.
- software reset initialization is performed by issuing a software reset command. If the operation state of the source driver circuit A3 is “display ON” when the software reset command is recognized, the reset state is entered after execution of the automatic display off sequence. On the other hand, if the operation state of the source driver circuit A3 is “display OFF”, the reset state is immediately established.
- FIG. 14 is a table for explaining the reset method.
- FIG. 15 is a table for explaining the state after reset.
- FIG. 16 is a table for explaining the automatic display off sequence.
- the configuration in which the level shifter circuit according to the present invention is applied to a liquid crystal display device has been described as an example.
- the configuration of the present invention is not limited thereto.
- the present invention can be widely applied to all level shifter circuits used for other purposes.
- the present invention is a technique useful for reducing the number of high-breakdown-voltage elements that form a level shifter circuit. This is a preferred technique.
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Abstract
Description
11 液晶画素
12 液晶駆動装置
121 レベルシフタ回路群
122 デジタル/アナログ変換回路群
123 ソースアンプ回路群
124a、124b 共用レベルシフタ回路
20 ロジック部
30 フレキシブルケーブル
1 入力バッファ
2 差動アンプ
3 出力バッファ
4 イネーブル制御部
5 ラッチ部
N1、N2 Nチャネル型MOS電界効果トランジスタ(高耐圧素
子)
N3~N5 Nチャネル型MOS電界効果トランジスタ(中耐圧素
子)
P1~P6 Pチャネル型MOS電界効果トランジスタ(中耐圧素
子)
INV1、INV2 インバータ(低耐圧素子)
INV3~INV5 インバータ(中耐圧素子)
INV6 3ステートインバータ(中耐圧素子)
SW1 パススイッチ(中耐圧素子)
A1 液晶表示パネル(液晶画素)
A2 マルチプレクサ
A3 ソースドライバ回路
A4 ゲートドライバ回路
A5 外部DC/DCコンバータ
A6 MPU
A7 映像ソース
B1 MPUインタフェイス
B2 コマンドデコーダ
B3 データレジスタ
B4 部分表示データ用RAM
B5 データ制御部
B6 表示データインタフェイス
B7 画像処理部
B8 データラッチ部
B9 ソースドライバ部
B10 OTPROM
B11 制御用レジスタ
B12 アドレスカウンタ(RAMコントローラ)
B13 タイミングジェネレータ
B14 発振器
B15 コモン電圧生成部
B16 マルチプレクサ用タイミングジェネレータ
B17 ゲートドライバ用タイミングジェネレータ
B18 外部DC/DC用タイミングジェネレータ
B19 液晶表示装置用電源回路
C1(1)~C1(n) レベルシフタ回路
C2(1)~C2(n) デジタル/アナログ変換回路
C3(1)~C3(n) ソースアンプ回路
C4(1)~C4(n) パススイッチ(極性反転制御用)
C5(1)~C5(n) パススイッチ(8色表示モード用)
C6(1)~C6(n) 出力端子
C7 抵抗ラダー
C8~C11 セレクタ
C12~C15 アンプ
C16 第1階調電圧生成部(正極性)
C17 第2階調電圧生成部(負極性)
C18~C21 出力キャパシタ
D1 発振器
D2 タイミングジェネレータ
D3 表示データインタフェイス
D4 アドレスカウンタ(RAMコントローラ)
D5 部分表示データ用RAM
D6 ソースデータタイミングコントローラ
D7 OTPROM
D8 OTPコントローラ
D9 外部DC/DC用タイミングジェネレータ
D10 マルチプレクサ・ゲートドライバ用タイミングジェネレー
タ
D11 液晶表示装置用電源回路
Claims (9)
- 接地電位の印加端と負電位の印加端との間に接続された一対のNチャネル型電界効果トランジスタから成る差動入力段を用いて、前記接地電位と正電位との間でパルス駆動される入力信号を差動形式で受け取り、これを差動増幅することによって、前記接地電位と前記負電位との間でパルス駆動される出力信号を生成する差動アンプを有して成ることを特徴とするレベルシフタ回路。
- 前記レベルシフタ回路を形成する複数のトランジスタのうち、前記差動入力段を形成する前記一対のNチャネル型電界効果トランジスタは、前記正電位と前記負電位との電位差にも耐え得る高耐圧素子であり、その余のトランジスタは、より耐圧の低い中耐圧素子や低耐圧素子であることを特徴とする請求項1に記載のレベルシフタ回路。
- 第1制御信号に応じて前記差動アンプをオン/オフするイネーブル制御部と、第2制御信号に応じて前記差動アンプの出力信号をサンプル/ホールドするラッチ出力部と、を有して成ることを特徴とする請求項2に記載のレベルシフタ回路。
- m系統(mは2以上の整数)の入力信号を各々レベルシフトしてm系統の出力信号を生成するm個のレベルシフタ回路と;
前記m系統の出力信号をmビットのデジタル信号として受け取り、これをアナログ信号に変換して出力するデジタル/アナログ変換回路と;
前記アナログ信号を負荷駆動信号として前記負荷に供給するアンプ回路と;
をn組(nは1以上の整数)有して成る負荷駆動装置であって、
前記複数のレベルシフタ回路のうち、接地電位と正電位との間でパルス駆動される入力信号を前記接地電位と負電位との間でパルス駆動される出力信号に変換するレベルシフタ回路は、請求項3に記載のレベルシフタ回路であることを特徴とする負荷駆動装置。 - 前記接地電位と前記負電位との間でパルス駆動される第1、第2制御信号を生成して、これらを前記複数のレベルシフタ回路に出力する共用レベルシフタ回路を有して成ることを特徴とする請求項4に記載の負荷駆動装置。
- 前記負荷は、液晶画素であることを特徴とする請求項5に記載の負荷駆動装置。
- 請求項6に記載の負荷駆動装置と、前記負荷駆動装置によって駆動される液晶画素と、を有して成ることを特徴とする液晶表示装置。
- 前記負荷駆動装置から出力されるn系統の出力信号をそれぞれz系統(zは1以上の整数)に分配することで(n×z)系統の出力信号を生成し、これを前記液晶画素に供給するマルチプレクサを有して成ることを特徴とする液晶表示装置。
- 前記負荷駆動装置は、n系統の出力信号の生成動作に合わせて、前記マルチプレクサのタイミング制御を行うマルチプレクサ用タイミングジェネレータを有して成ることを特徴とする請求項8に記載の液晶表示装置。
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US13/125,068 US20110193848A1 (en) | 2008-10-30 | 2009-10-29 | Level shifter circuit, load drive device, and liquid crystal display device |
CN2009801434857A CN102204104A (zh) | 2008-10-30 | 2009-10-29 | 电平移位电路、负载驱动装置及液晶显示装置 |
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FR2976724B1 (fr) * | 2011-06-16 | 2013-07-12 | Nanotec Solution | Dispositif pour generer une difference de tension alternative entre des potentiels de reference de systemes electroniques. |
CN102394581A (zh) * | 2011-09-19 | 2012-03-28 | 张兴发 | 全差分运算放大器 |
KR101418141B1 (ko) * | 2011-12-13 | 2014-07-11 | 엘지디스플레이 주식회사 | 표시장치 |
TWI463472B (zh) * | 2012-09-07 | 2014-12-01 | Chunghwa Picture Tubes Ltd | 用以降低液晶面板閃爍的裝置和用以降低液晶面板閃爍的方法 |
US9099026B2 (en) * | 2012-09-27 | 2015-08-04 | Lapis Semiconductor Co., Ltd. | Source driver IC chip |
US10540924B2 (en) * | 2016-01-20 | 2020-01-21 | Silicon Works Co., Ltd | Source driver |
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US6940315B2 (en) * | 2003-03-14 | 2005-09-06 | Programmable Microelectronics Corporation | High speed sense amplifier for memory output |
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2009
- 2009-10-29 CN CN2009801434857A patent/CN102204104A/zh active Pending
- 2009-10-29 WO PCT/JP2009/068556 patent/WO2010050543A1/ja active Application Filing
- 2009-10-29 JP JP2010535834A patent/JPWO2010050543A1/ja active Pending
- 2009-10-29 US US13/125,068 patent/US20110193848A1/en not_active Abandoned
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JPS61244120A (ja) * | 1985-04-23 | 1986-10-30 | Nippon Telegr & Teleph Corp <Ntt> | 論理信号検出出力回路 |
JPH1127133A (ja) * | 1997-07-01 | 1999-01-29 | Mitsubishi Electric Corp | 半導体集積回路 |
Also Published As
Publication number | Publication date |
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JPWO2010050543A1 (ja) | 2012-03-29 |
US20110193848A1 (en) | 2011-08-11 |
CN102204104A (zh) | 2011-09-28 |
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