WO2010047040A1 - バリア膜とドレイン電極膜およびソース電極膜との間の密着強度に優れた薄膜トランジスター - Google Patents
バリア膜とドレイン電極膜およびソース電極膜との間の密着強度に優れた薄膜トランジスター Download PDFInfo
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- 239000010408 film Substances 0.000 title claims abstract description 226
- 239000010409 thin film Substances 0.000 title claims abstract description 37
- 230000004888 barrier function Effects 0.000 title claims abstract description 36
- 239000000853 adhesive Substances 0.000 title abstract 3
- 230000001070 adhesive effect Effects 0.000 title abstract 3
- 239000010949 copper Substances 0.000 claims abstract description 43
- 229910052802 copper Inorganic materials 0.000 claims abstract description 39
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 35
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 30
- 239000001301 oxygen Substances 0.000 claims abstract description 30
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 29
- 230000002708 enhancing effect Effects 0.000 claims abstract description 10
- 229910052791 calcium Inorganic materials 0.000 claims abstract description 5
- 239000011575 calcium Substances 0.000 claims abstract description 4
- 238000009826 distribution Methods 0.000 claims abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 25
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 25
- 239000004065 semiconductor Substances 0.000 claims description 12
- 230000002776 aggregation Effects 0.000 claims description 11
- 239000011521 glass Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 238000004220 aggregation Methods 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000005054 agglomeration Methods 0.000 claims description 3
- 239000000470 constituent Substances 0.000 claims description 2
- 239000004615 ingredient Substances 0.000 abstract 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 14
- 229910000881 Cu alloy Inorganic materials 0.000 description 11
- 230000003014 reinforcing effect Effects 0.000 description 10
- 239000001257 hydrogen Substances 0.000 description 8
- 229910052739 hydrogen Inorganic materials 0.000 description 8
- 238000009832 plasma treatment Methods 0.000 description 8
- 230000010354 integration Effects 0.000 description 7
- 238000000926 separation method Methods 0.000 description 7
- 238000004544 sputter deposition Methods 0.000 description 7
- 238000005259 measurement Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 238000011160 research Methods 0.000 description 4
- 229910000882 Ca alloy Inorganic materials 0.000 description 3
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910001882 dioxygen Inorganic materials 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000001275 scanning Auger electron spectroscopy Methods 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
Definitions
- the present invention relates to a thin film transistor used for various displays, and more particularly to a thin film transistor excellent in adhesion strength between a barrier film, a drain electrode film, and a source electrode film.
- Liquid crystal displays, plasma displays, organic EL displays, inorganic EL displays and the like are known as flat panel displays using thin film transistors driven by an active matrix method.
- wirings made of a metal film are formed in close contact with the surface of the glass substrate, and thin film transistors are provided at intersections of the grid wiring made of the metal film.
- the thin film transistor 110 includes a gate electrode film 2, a pure copper film 2, a silicon nitride film 3, a Si semiconductor film 4, and a silicon oxide, which are sequentially stacked on the surface of the glass substrate 1.
- the electrode film 6 includes a drain electrode film of pure copper film and a source electrode film of pure copper film (both in FIG. It is well known that it is composed of electrode film 6 ”.
- the separation groove 8 that partitions the drain electrode film and the source electrode film is formed by wet etching and plasma etching.
- the surface of the Si semiconductor film 4 exposed on the bottom surface of the separation groove 8 is in an extremely unstable state, increasing dangling bonds (dangling bonds), which becomes a surface defect. This surface defect increases the off-state current of the thin film transistor. As a result, problems such as a reduction in LCD contrast and a reduction in viewing angle occur.
- the surface of the Si semiconductor film 4 exposed on the bottom surface of the separation groove 8 is in an unstable state in which the above-described problems cannot be avoided.
- gas 100% hydrogen gas
- hydrogen gas flow rate 10 to 1000 SCCM
- hydrogen gas pressure 10 to 500 Pa
- RF current density 0.005 to 0.5 W / cm 2
- the treatment time may be subjected to a hydrogen plasma treatment under conditions of 1 to 60 minutes, and a dangling bond on the surface of the Si semiconductor film 4 is bonded to hydrogen atoms to be stabilized. It is known (see Patent Document 1).
- the increase in screen size and integration of various flat panel displays in recent years is remarkable, and accordingly, higher adhesion strength is required between the respective films of the laminated film constituting the thin film transistor 110. It is in.
- the conventional thin film transistor 110 between the glass substrate 1 and the gate electrode film 2 made of a pure copper film, between the gate electrode film 2 and the silicon nitride film 3, and between the silicon nitride film 3 and the Si semiconductor film 4.
- a high adhesion strength that can sufficiently satisfy the above requirements is secured between the Si semiconductor film 4 and the barrier film 5 of the silicon oxide film.
- the adhesion strength between the barrier film 5 of the silicon oxide film and the drain electrode film and the source electrode film (electrode film 6) of the pure copper film partitioned by the separation groove 8 is relatively low.
- the current situation is that it does not have high adhesion strength that can be satisfied.
- An object of the present invention is to provide a thin film transistor having excellent adhesion strength between a barrier film and a drain electrode film and a source electrode film.
- the present inventors made a barrier film of a silicon oxide film in a conventional thin film transistor and a drain electrode film and a source electrode film (hereinafter simply referred to as an electrode film) of a pure copper film partitioned by a separation groove. Research was conducted to ensure high adhesion strength. As a result, the following research results were obtained.
- a Cu-Ca-oxygen-containing Cu component is formed between the barrier film 5 of the silicon oxide film and the electrode film 6 of the pure copper film shown in the schematic longitudinal sectional view of FIG.
- An alloy film is formed.
- the Cu alloy film is formed by performing sputtering using a Cu—Ca alloy target and setting the sputtering atmosphere to an Ar + oxygen gas atmosphere containing oxygen gas.
- Ca contained as an alloy component during the hydrogen plasma treatment performed after the formation of the separation groove 8 together with the oxygen contained therein is in contact with the barrier film 5 of the silicon oxide film. It diffuses and moves to the interface.
- the Cu alloy film after the hydrogen plasma treatment becomes an adhesion enhancing film 7 composed of the following two zones (a) and (b).
- the adhesion reinforcing film 7 satisfying the conditions shown in the above (2) and (3) can be formed by the following method.
- the Cu alloy film (1) is formed as follows. A Cu—Ca alloy target containing 0.1 to 12 atomic% of Ca and containing Cu and inevitable impurities as the balance is used as a target, and the sputtering atmosphere is in a proportion of 1 to 20 in the total amount of Ar and Ar. Sputtering is performed as an Ar + oxygen gas atmosphere containing a volume% of oxygen. As a result, a Cu alloy film having a composition containing oxygen: 1 to 20 atomic% and Ca: 0.1 to 10 atomic% and the balance including Cu and inevitable impurities is formed with a target film thickness of 10 to 100 nm. . Thus, the Cu alloy film (1) can be formed. Then, the adhesion reinforcing film 7 is formed by the hydrogen plasma treatment described above. The research results shown in (1) to (4) above were obtained.
- the present invention has been made based on the above research results and has the following requirements.
- the thin film transistor having excellent adhesion strength between the barrier film and the drain electrode film and the source electrode film of the present invention comprises a glass substrate, a gate electrode film of a pure copper film formed on the surface of the glass substrate, and nitrided. It has a silicon film, a Si semiconductor film, a barrier film of a silicon oxide film, and an electrode film of a pure copper film.
- the electrode film includes a drain electrode film and a source electrode film.
- An adhesion enhancing film having a thickness of 10 to 100 nm is interposed between the barrier film of the silicon oxide film and the drain electrode film and the source electrode film of the pure copper film.
- the adhesion enhancing film is formed at an interface between (a) a pure copper zone formed on the drain electrode film and source electrode film side of the pure copper film, and (b) a barrier film of the silicon oxide film.
- the component is composed of two zones including a component aggregation zone composed of Cu, Ca, oxygen and Si. In the concentration distribution of Ca and oxygen in the thickness direction of the component agglomeration zone, the maximum content of Ca and oxygen-containing peaks is Ca: 5 to 20 atomic% and oxygen: 30 to 50 atomic%, respectively.
- the adhesion enhancing film is formed by the hydrogen plasma treatment described above, and the requirements for the adhesion enhancing film can be specified by measuring the cross-sectional structure in the thickness direction with a scanning Auger electron spectrometer. .
- the adhesion strength of the both is dramatically improved by interposing the adhesion reinforcing film having the above structure between the barrier film of the silicon oxide film and the electrode film of the pure copper film.
- each of the laminated films constituting the thin film transistor is bonded to each other with strong adhesion strength. For this reason, the extremely high film-to-film adhesion required for the large screen and high integration of the flat panel display can be provided throughout.
- the adhesion enhancing film 7 constituting the thin film transistor 1 of the present invention is limited to the above-described conditions.
- (1) Maximum content of oxygen-containing peak in component aggregation zone When the maximum oxygen content is less than 30 atomic%, a flat panel display is formed between the component aggregation zone and the adjacent silicon oxide film (barrier film 5). It is not possible to secure a strong adhesion strength that can be satisfactorily dealt with the increase in screen size and integration. On the other hand, when the maximum oxygen content exceeds 50 atomic%, the strength of the component agglomeration zone tends to decrease, which causes peeling. Based on the above, the maximum oxygen content was determined to be 30 to 50 atomic%.
- Target film thickness of adhesion reinforcing film 7 When the target film thickness is less than 10 nm, it is possible to secure a strong adhesion strength between the barrier film 5 of the silicon oxide film and the electrode film 6 of the pure copper film. Can not. On the other hand, even if the target film thickness exceeds 100 nm, a further improvement effect cannot be obtained in the adhesion strength between the two. For this reason, the target film thickness is set to 10 to 100 nm in consideration of economy.
- the adhesion strength between the barrier film of the silicon oxide film and the electrode film of the pure copper film will be specifically described with reference to the thin film transistor of the present invention.
- the film thickness 300 nm in order from the surface side of the glass substrate to the surface of a 1737 glass substrate made by Corning Inc. having dimensions of length: 320 mm ⁇ width: 400 mm ⁇ thickness: 0.7 mm.
- a pure copper film (gate electrode film), a silicon nitride film with a film thickness of 300 nm, a Si semiconductor film with a film thickness of 150 nm, and a silicon oxide film (barrier film) with a film thickness of 10 nm were sequentially laminated.
- the glass substrate having the film was placed in a sputtering apparatus. Then, as a target, a Cu—Ca alloy (including Cu and unavoidable impurities other than Ca) dissolved and prepared so as to have the Ca content shown in Table 1 was used, and the sputtering atmosphere was adjusted to the total amount of Ar. Sputtering was performed in an Ar + oxygen atmosphere in which oxygen in the proportions shown in Table 1 was mixed with Ar. Thereby, Cu alloy films having the compositions shown in Table 1 were formed on the silicon oxide film (barrier film) with the target film thicknesses shown in Table 1, respectively. In addition, the composition of the Cu alloy film shown in Table 1 is a result of measurement using a scanning Auger electron spectrometer.
- the thin film transistor samples 1 to 10 of the examples of the present invention were manufactured.
- a thin film transistor sample of a conventional example was manufactured under the same conditions except that an adhesion reinforcing film (Cu alloy film) was not formed.
- the cross section in the thickness direction was measured by a sample tilt rotation method (Zalar rotation method) using a scanning Auger electron spectroscopy analyzer. And the purity change of the film thickness direction in the pure copper film (electrode film) of the surface part was observed. Furthermore, the maximum content of the oxygen-containing peak and the Ca-containing peak in the component aggregation zone of the adhesion reinforcing film was measured, and the measurement results are shown in Table 1.
- FIG. 2 shows the measurement results of the thin film transistor sample 4 of the present invention using a scanning Auger electron spectrometer.
- a thin (10 nm) silicon oxide film (barrier film) cannot be confirmed, but in the structure observation by a transmission electron microscope, the adhesion enhancement film (component cohesive zone) and the Si semiconductor film are not observed. It was confirmed that a silicon oxide film (barrier film) was present.
- the pure copper film (electrode film) on the surface portion of the sample 4 exhibits a purity of 99.9 atomic% or more along the thickness direction. However, like the sample 4, the pure copper film (electrode film) was found to have a purity of 99.9 atomic% or more.
- cross-cut adhesion test According to JIS-K5400, on the surface of the sample, using a cutter, at a distance of 0.5 mm, 1 mm, 1.5 mm, and 2 mm, respectively, at a depth reaching the silicon oxide film from the surface in 11 vertical and horizontal directions, In addition, a groove (notch) was made with a groove width of 0.1 mm. As a result, 100 cells were formed at each interval.
- a 3M scotch tape was adhered and pasted over the entire cell, and then peeled off at once. And the number (pieces / 100) of the squares which peeled among 100 squares of the sample surface was measured. The measurement results are shown in Table 2.
- the thin film transistor samples 1 to 10 of the present invention example are formed by the adhesion reinforcing film interposed between the silicon oxide film (barrier film) and the pure copper film (electrode film). Compared to the conventional thin film transistor sample without the formation of the reinforcing layer, extremely high adhesion strength is ensured between them, and as a result, the adhesion between the constituent films is excellent overall. I understood it. As described above, the thin film transistor of the present invention can satisfactorily cope with the large screen and high integration of flat panel displays.
- the thin film transistor of the present invention since the adhesion strength between the barrier film and the electrode film is extremely high, it can sufficiently meet the above requirements and is suitable as a thin film transistor for a flat panel display having a large screen and high integration. Can be used.
- Transistor 110: Conventional thin film transistor.
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Abstract
Description
本願は、2008年10月24日に、日本に出願された特願2008-273728号に基づき優先権を主張し、その内容をここに援用する。
このため、露出したSi半導体膜4の表面に、ガス:100%水素ガス、水素ガス流量:10~1000SCCM、水素ガス圧:10~500Pa、RF電流密度:0.005~0.5W/cm2、処理時間:1~60分の条件で水素プラズマ処理を施して、Si半導体膜4の表面の未結合手(ダングリングボンド)を水素原子と結合させて安定化する処理が施されることも知られている(特許文献1参照)。
このCu合金膜においては、上記の分離溝8の形成後に施される水素プラズマ処理中に、合金成分として含有されるCaが、同じく含有される酸素と共に、前記酸化ケイ素膜のバリア膜5との界面部に拡散移動する。これにより、水素プラズマ処理後の前記Cu合金膜は、以下の(a)および(b)の2帯域で構成された密着強化膜7となる。
(a)純銅膜の電極膜6側に形成された純銅化帯域
(b)酸化ケイ素膜のバリア膜5との界面部に形成され、構成成分がCuと酸素とCaとSiからなる成分凝集帯域
(c)電極膜6側には純銅化帯域が形成されている。
(d)一方、バリア膜5側には、それぞれ酸素とCaの含有ピークが存在する成分凝集帯域が形成されている。
なお、上記の走査型オージェ電子分光分析装置による測定では、膜厚が薄い酸化ケイ素膜(バリア膜5)の存在を確認することができないが、透過型電子顕微鏡による組織観察で、その存在を明確に確認することができる。
さらに、前記Ca含有ピークの最高含有量が5~20原子%を示す場合に、Caによる酸素の前記バリア膜5側への拡散移動が十分に行われて、前記最高含有量が30~50原子%の酸素含有ピークの形成が可能となる。
純銅化帯域と、隣接する電極膜6とは、界面が高純度(99.9原子%以上の純度)の純銅同士となるので、これら両者間にはきわめて高い密着強度が確保される。また、前記純銅膜の電極膜6は99.9原子%以上の高純度を保持することから、前記電極膜6に電気的特性の低下は見られない。
前記(1)のCu合金膜は、以下のように形成される。ターゲットとして、Ca:0.1~12原子%を含有し、残部としてCuと不可避不純物を含むCu-Ca合金ターゲットを用い、スパッタ雰囲気を、ArにArとの合量に占める割合で1~20容量%の酸素を配合してなるAr+酸素ガス雰囲気として、スパッタを行う。これにより、酸素:1~20原子%、及びCa:0.1~10原子%を含有し、残部としてCuと不可避不純物を含む組成を有するCu合金膜を10~100nmの目標膜厚で形成する。以上により、前記(1)のCu合金膜が形成できる。そして、前述した水素プラズマ処理によって密着強化膜7が形成される。
以上(1)~(4)に示される研究結果を得たのである。
本発明のバリア膜とドレイン電極膜およびソース電極膜との間の密着強度に優れた薄膜トランジスターは、ガラス基板と、前記ガラス基板の表面に順次積層形成された、純銅膜のゲート電極膜、窒化珪素膜、Si半導体膜、酸化ケイ素膜のバリア膜、及び純銅膜の電極膜を有する。
前記電極膜は、ドレイン電極膜とソース電極膜からなる。
前記酸化ケイ素膜のバリア膜と、前記純銅膜のドレイン電極膜およびソース電極膜との間に、10~100nmの膜厚を有する密着強化膜が介在する。
前記密着強化膜は、(a)前記純銅膜のドレイン電極膜およびソース電極膜の側に形成された純銅化帯域と、(b)前記酸化ケイ素膜のバリア膜との界面部に形成され、構成成分がCuとCaと酸素とSiからなる成分凝集帯域との2帯域で構成される。
前記成分凝集帯域の厚さ方向におけるCaおよび酸素の濃度分布において、Caおよび酸素の含有ピークの最高含有量が、それぞれCa:5~20原子%、及び酸素:30~50原子%である。
この発明の薄膜トランジスター1を構成する密着強化膜7を、上述の通りの条件に限定した理由を説明する。
(1)成分凝集帯域の酸素含有ピークの最高含有量
酸素の最高含有量が30原子%未満の場合、成分凝集帯域と、隣接する酸化ケイ素膜(バリア膜5)との間に、フラットパネルディスプレイの大画面化および高集積化に十分満足に対応できる強固な密着強度を確保できない。一方、酸素の最高含有量が50原子%を越える場合、成分凝集帯域の強度に低下傾向が現れ、これが剥離の原因ともなる。以上により、酸素の最高含有量を30~50原子%と定めた。
Caの最高含有量が5原子%未満の場合、水素プラズマ処理時に、バリア膜5側への酸素の拡散移動が十分に行われず、この結果、最高含有量が30~50原子%の酸素含有ピークを得ることが困難になる。一方、Caの最高含有量が20原子%を越える場合、成分凝集帯域の強度に低下傾向が現れる。以上により、Caの最高含有量を5~20原子%と定めた。
その目標膜厚が、10nm未満の場合、前記酸化ケイ素膜のバリア膜5と純銅膜の電極膜6との間に強固な密着強度を確保することができない。一方、その目標膜厚が、100nmを超えても、両者間の密着強度において、より一層の向上効果は得られない。このため、経済性を考慮して、その目標膜厚を10~100nmと定めた。
従来の膜形成条件にしたがって、縦:320mm×横:400mm×厚さ:0.7mmの寸法をもったコーニング社製1737のガラス基板の表面に、ガラス基板の表面側から順に、膜厚:300nmの純銅膜(ゲート電極膜)、膜厚:300nmの窒化珪素膜、膜厚:150nmのSi半導体膜、および膜厚:10nmの酸化ケイ素膜(バリア膜)を順次積層した。
(水素プラズマ処理の条件)
ガス:100%水素ガス、水素ガス流量:500SCCM、水素ガス圧:100Pa、処理温度:300℃、RF電力流密度:0.1W/cm2、処理時間:2分。
また、比較の目的で、密着強化膜(Cu合金膜)の形成を行なわない以外は、同一の条件で、従来例の薄膜トランジスター試料を製造した。
また、図2に示される通り、前記試料4の表面部の純銅膜(電極膜)は、厚さ方向に沿って99.9原子%以上の純度を示しているが、これ以外のいずれの試料でも、前記試料4と同じく、純銅膜(電極膜)は99.9原子%以上の純度を有することがわかった。
碁盤目付着試験:
JIS-K5400に準じ、前記試料の表面に、カッターを用いて、0.5mm、1mm、1.5mm、および2mmの間隔で、それぞれ縦横11本ずつ、表面から酸化ケイ素膜に達する深さで、かつ0.1mmの溝幅で、溝(切り込み)を入れた。これにより、それぞれの間隔で100個の升目を形成した。この升目全体に亘って、3M社製スコッチテープを密着して貼り付けた後、一気に引き剥がした。そして、試料表面の100個の升目のうち、剥離した升目の数(個/100)を測定した。この測定結果を表2に示した。
上述のように、この発明の薄膜トランジスターは、フラットパネルディスプレイの大画面化および高集積化に十分満足に対応できるものである。
Claims (1)
- ガラス基板と、前記ガラス基板の表面に順次積層形成された、純銅膜のゲート電極膜、窒化珪素膜、Si半導体膜、酸化ケイ素膜のバリア膜、及び純銅膜の電極膜を有し、
前記電極膜は、ドレイン電極膜とソース電極膜からなり、
前記酸化ケイ素膜のバリア膜と、前記純銅膜のドレイン電極膜およびソース電極膜との間に、10~100nmの膜厚を有する密着強化膜が介在し、
前記密着強化膜は、(a)前記純銅膜のドレイン電極膜および前記ソース電極膜の側に形成された純銅化帯域と、(b)前記酸化ケイ素膜のバリア膜との界面部に形成され、構成成分がCuとCaと酸素とSiからなる成分凝集帯域との2帯域で構成され、
前記成分凝集帯域の厚さ方向におけるCaおよび酸素の濃度分布において、Caおよび酸素の含有ピークの最高含有量が、それぞれCa:5~20原子%、及び酸素:30~50原子%であることを特徴とするバリア膜とドレイン電極膜およびソース電極膜との間の密着強度に優れた薄膜トランジスター。
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