WO2010044358A1 - ウェハのパターン検査方法及び装置 - Google Patents

ウェハのパターン検査方法及び装置 Download PDF

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Publication number
WO2010044358A1
WO2010044358A1 PCT/JP2009/067442 JP2009067442W WO2010044358A1 WO 2010044358 A1 WO2010044358 A1 WO 2010044358A1 JP 2009067442 W JP2009067442 W JP 2009067442W WO 2010044358 A1 WO2010044358 A1 WO 2010044358A1
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WO
WIPO (PCT)
Prior art keywords
pattern
inspection
wafer
image
chip
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Application number
PCT/JP2009/067442
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English (en)
French (fr)
Japanese (ja)
Inventor
拓人 上村
隆 伊藤
孝明 石井
Original Assignee
株式会社トプコン
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Publication date
Application filed by 株式会社トプコン filed Critical 株式会社トプコン
Priority to CN2009801402786A priority Critical patent/CN102177429B/zh
Publication of WO2010044358A1 publication Critical patent/WO2010044358A1/ja

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84—Systems specially adapted for particular applications
    • G01N21/88—Investigating the presence of flaws or contamination
    • G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
    • G01N21/9501—Semiconductor wafers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84—Systems specially adapted for particular applications
    • G01N21/88—Investigating the presence of flaws or contamination
    • G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
    • G01N21/956—Inspecting patterns on the surface of objects
    • G01N21/95607—Inspecting patterns on the surface of objects using a comparative method
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/0002—Inspection of images, e.g. flaw detection
    • G06T7/0004—Industrial image inspection
    • G06T7/001—Industrial image inspection using an image reference approach
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/30—Subject of image; Context of image processing
    • G06T2207/30108—Industrial image inspection
    • G06T2207/30148—Semiconductor; IC; Wafer

Definitions

  • the present invention relates to a pattern inspection method and apparatus for inspecting a wafer pattern.
  • a wafer pattern comprising: means for determining pass / fail of the apparatus; means for storing the input inspection image as a new master image when the difference amount is equal to or less than a predetermined value; and means for outputting the determination result of pass / fail Inspection devices are known.
  • the conventional pattern matching inspection cannot be performed if the patterns are greatly different. This is because the difference amount is too large and the determination result may always be negative.
  • wafers having different patterns depending on the manufacturing process may be subject to inspection.
  • the difference in pattern may not be a problem in quality and performance.
  • Such products could not be properly inspected by wafer pattern matching inspection.
  • the inspection can be performed to some extent if the averaging of the reference image and the inspection sensitivity are reduced by the learning process.
  • the averaging or detection sensitivity of the reference image by the difference learning process is made too sweet, the defect detectability deteriorates.
  • the learning process is automatically performed, it is difficult to ensure desired defect detectability.
  • An object of the present invention is to provide a wafer pattern inspection method and apparatus that enable an automatic learning function for wafers having different patterns.
  • Examples of the solution means of the present invention for solving the above-described problems are as follows. (1.) A step of inputting an inspection image of a wafer pattern or chip to be inspected, comparing the input inspection image with a pre-stored reference image, and determining whether the wafer is good or bad based on the difference between the comparison images
  • a wafer pattern inspection method comprising: If the non-defective product rate falls below a predetermined threshold during the inspection, the learning process is performed again using the pattern or chip image being inspected to create a new reference image, or uniform after learning the pattern through the learning process.
  • a wafer inspection is performed by an inspection other than the pattern matching inspection, such as a pitch inspection.
  • a pattern matching inspection and a pitch inspection are simultaneously performed on the uniform pattern part.
  • a wafer pattern inspection method characterized by determining a sensitivity of pattern matching inspection from a result and inspecting a pattern or a chip on the entire surface of the wafer with the determined sensitivity.
  • a wafer pattern inspection apparatus comprising a processing means having a determination means for determining, When the non-defective product rate falls below a predetermined threshold during the inspection, the arithmetic processing means creates a new reference image by performing the learning process again using the image of the pattern or chip under inspection, or the pattern by the learning process.
  • a wafer pattern inspection apparatus characterized in that the sensitivity of the pattern matching inspection is determined from the result of the pitch inspection, and the pattern or chip on the entire wafer surface is inspected with the determined sensitivity. Even if there is a pattern or chip with greatly different pattern deviation or color unevenness from the original reference, it is judged whether it is a non-defective wafer as a product that does not cause a problem in product performance. Can maintain the non-defective rate. The best mode for carrying out the present invention will be described below.
  • the learning process is performed again. More specifically, after learning the pattern by the learning process, a uniform pattern is searched, and if it is a uniform pattern portion, the wafer is inspected by an inspection other than the pattern matching inspection such as a pitch inspection. (2) The pattern matching inspection and the pitch inspection are simultaneously performed on the uniform pattern portion, and the sensitivity of the pattern matching inspection is determined from the result of the pitch inspection. (3) The pattern or chip on the entire wafer surface is inspected with the sensitivity determined as described above.
  • the predetermined threshold can be arbitrarily set by the user of the apparatus (for example, a non-defective product between 90 and 95%). rate). However, the predetermined threshold value may be fixed to only one desired value, or only the lowest value may be fixed, and the desired value may be made variable and adjusted as necessary. Also good.
  • the lowest value may be fixed at 90%, and an arbitrary threshold value (for example, 95%) higher than that may be set.
  • the present invention includes a step of inputting an inspection image of a wafer pattern or chip, comparing the input inspection image with a pre-stored reference image, and determining whether the wafer is good or bad based on a difference amount of the comparison image.
  • the pattern inspection method and apparatus are improved.
  • the non-defective product rate is extremely lowered during inspection and becomes a predetermined value (for example, 90%, 95%, or other values)
  • the learning process is performed again on the pattern or chip image being inspected.
  • pattern matching inspection and pitch inspection are simultaneously performed on the uniform pattern portion to determine the sensitivity of the pattern matching inspection, and the pattern or chip on the entire wafer surface is inspected with the determined sensitivity.
  • FIG. 1A and 1B are diagrams showing an outline of a wafer pattern inspection apparatus according to the present invention.
  • FIG. 2 is a diagram for explaining recipe (reference) creation.
  • FIG. 3 is a diagram for explaining a chip in which a pattern shift, which is an object of the present invention, is generated.
  • FIG. 4 is a diagram for explaining creation of a reference image by relearning.
  • FIG. 5 is a diagram for explaining the inspection after re-learning.
  • FIG. 6 is a diagram for explaining a difference between pattern inspection and pitch inspection.
  • FIG. 7 is a flowchart.
  • FIG. 1 shows an appearance inspection apparatus 10 suitable for carrying out a wafer pattern (appearance) inspection method according to the present invention.
  • an appearance inspection apparatus 10 has each circuit pattern formed on a large number of semiconductor chips 11a formed in alignment on a semiconductor wafer 11 as shown in FIG. Used to determine if the defect is acceptable.
  • the present invention will be described along an example in which the present invention is applied to an inspection of a semiconductor chip 11 a formed on a semiconductor wafer 11.
  • the appearance inspection apparatus 10 controls the operation of the optical imaging mechanism 10a and the optical imaging mechanism, and performs arithmetic processing on the image information obtained by the optical imaging mechanism 10a.
  • the optical imaging mechanism 10a moves the moving unit 12 provided with the stage 12a for holding the semiconductor wafer 11 and the stage 12a of the moving unit in the X-axis direction and the Y-axis direction on the XY plane, and moves around the Z-axis.
  • the imaging unit 15 is constituted by, for example, a CCD imaging device and its optical system.
  • the control arithmetic means (arithmetic processing unit) 10 b includes an arithmetic processing circuit 16, and the arithmetic processing circuit 16 can be configured by a central processing unit (CPU) that operates in accordance with a program stored in the memory 17, for example. .
  • the arithmetic processing circuit 16 controls the operations of the driver 13, the illumination unit 14, and the imaging unit 15 of the optical imaging mechanism 10a via the control circuit 18, and is obtained by the imaging unit 15 according to the information stored in the memory 17.
  • the detected image is subjected to defect detection processing.
  • the arithmetic processing circuit 16 includes an area setting unit 16a for dividing the inspection region of the image obtained by the imaging unit 15 into a plurality of areas, and a defect by comparing the inspection region of the image with a template for inspection.
  • a defect extraction unit 16b for extracting a part a determination unit 16c for determining whether or not the defect part extracted by the defect extraction part is within an allowable range, and a pattern that is within the allowable range but has no problem in product performance.
  • a learning function unit 16d is provided that learns the image of the shifted pattern, the image of the chip, or the average image thereof as a reference image (reference image or reference image).
  • the arithmetic processing circuit 16 is connected to a monitor 19 having a display unit composed of, for example, a liquid crystal or a CRT, and an input unit 20 composed of, for example, a keyboard and a mouse.
  • the monitor 19 can display an image captured by the imaging unit 15 and an image processed by the arithmetic processing circuit 16, and can display information necessary for operating the optical imaging mechanism 10a. Based on the information displayed on the monitor 19, a command necessary for operating the appearance inspection apparatus 10 can be appropriately input from the input unit 20.
  • the imaging unit 15 captures a reference image (reference image or standard image) and an image for the object to be inspected. A desired inspection region is cut out from the surface image of the semiconductor chip 11 a photographed by the imaging unit 15 and displayed on the monitor 19. In FIG.
  • the image on the left is an example of the display screen 21A for the examination area cut out as described above.
  • This display screen 21A shows an example in which the semiconductor chip 11a is a memory chip.
  • FIG. 6 shows a pattern image and a chip image. In the surface image, a defective portion is observed at a position indicated by a star, that is, a star.
  • the observed defect is a defect such as adhesion of a foreign substance to the circuit pattern or a partial defect of the circuit pattern.
  • an average image is selected and used as a reference image (reference image).
  • This reference image (reference image) and the surface image 21A of the other semiconductor chip 11a that is the inspection object, that is, the inspection object, are compared by the arithmetic processing circuit 16 for defect extraction.
  • the arithmetic processing circuit 16 compares a reference image (reference image) with an image of the semiconductor chip 11a of the object to be inspected.
  • the sensitivity adjustment is performed for the reference image (reference image) and the entire pattern or chip of the object to be inspected.
  • shading processing for removing illumination unevenness by the illumination unit 14 multi-value processing for promoting the clarification of edges, and reducing the influence of pattern density and image shading upon edge detection
  • color tone conversion processing for color recognition, chromaticity conversion for facilitating pattern recognition, or expansion / contraction processing using an expansion / contraction filter for removing noise is performed. These processes can be performed by a well-known method. These can be appropriately selected and combined.
  • the arithmetic processing circuit 16 compares the reference image (reference image) with the image subjected to the image preprocessing of the object to be inspected, and uses the reference image (reference image) based on pattern density, image density, chromaticity, and the like. Adjust the detection sensitivity.
  • an image to be compared is registered in advance.
  • a reference image (reference image) as a reference for inspection is created (recipe creation).
  • the reference image (reference image) is, for example, one chip as shown on the left side of FIG. However, a plurality of chip images may be set as a reference image.
  • the reference image (reference image) is stored in a storage unit (memory) provided separately from the arithmetic processing unit of the apparatus, and is learned through the learning function of the arithmetic processing unit. After learning, the average image is stored in the storage unit as a reference image (reference image) as shown on the right side of FIG. As a result, as shown in FIG. 3, since the left pattern matches the reference image (reference image), it is determined to be inspected, but the right pattern is different from the reference image (reference image). , It is determined that the inspection is NG.
  • the non-defective product ratio ratio of non-defective products with a small difference from the reference image
  • a reference image reference image
  • the reference before the change on the left side is set to the reference on the right side (relearning, average image change).
  • the non-defective product rate has decreased to 95%, but a reference image is re-created using a wafer pattern (or chip) having a deviation that does not cause a problem in the product as a reference image.
  • the average image is changed, the reference image (reference image) is relearned, and the wafer pattern or chip inspection is restarted based on the reference image (reference image).
  • the inspection result is OK even if the pattern is different from the pattern before the reference image correction.
  • the re-learning process is immediately performed, and the reference image (reference image) is obtained. It is desirable to make it again.
  • the present invention is not limited to a fixed fixed product rate (95% or other set values), and the operator can achieve a predetermined minimum product rate (for example, 90%, but not limited to this).
  • the learning function can be adjusted to re-learn freely at any threshold within the range.
  • the arithmetic control unit has a function of automatically adjusting detection sensitivity in combination with a pattern matching inspection based on a reference image (reference image).
  • the automatic sensitivity adjustment refers to a function of automatically determining the sensitivity by comparing the detectability of the pattern matching inspection and the pitch inspection.
  • the entire chip is usually compared with the entire reference image (reference image) to check whether they match, as shown on the right side.
  • the sensitivity of the pattern matching inspection is adjusted so that the same defect can be detected by comparing the result of the pattern matching inspection with the result of the pitch inspection.
  • Pattern matching detection and pitch inspection are performed on the same inspection image, and the detection sensitivity of the pattern inspection is adjusted so that the defect detection performance is almost the same.
  • the pattern matching inspection can inspect the entire chip, but the pitch inspection can usually inspect only the uniform pattern portion.
  • FIG. 7 shows a flowchart.
  • an inspection recipe is created with the first wafer and wafer inspection is performed.
  • the non-defective product rate is lower than a set value (for example, 90%)
  • the learning process is performed on the wafer under inspection.
  • the inspection is performed again based on the re-learned reference image (reference image).
  • the inspection result of the re-learned reference image (reference image) is stored as the wafer inspection result, and the inspection is terminated.
  • the apparatus it is preferable to deal with the following in response to a chip whose pattern has shifted. Even if there is a shift in the pattern for each lot or for each wafer, it is possible to make it non-defective. If the pattern is misaligned, the generated wafer is subjected to the learning process again and inspected. Although it is not easy for the apparatus to automatically determine whether the cause of the decrease in the non-defective product rate is a pattern shift, it is preferable to perform the learning process again when the non-defective product rate falls below a predetermined threshold value. In a preferred aspect of the present invention, the learning process is performed again when the yield rate falls below a predetermined threshold.
  • the detection performance may be reduced by learning. For example, a significant decrease in detection performance appears on wafers with severe color irregularities and wafers with continuous defects at the same position. Therefore, it is possible to determine a pattern or chip that does not cause a problem in performance as a non-defective product, and to maintain the work efficiency of the inspection and the original good product rate.

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
PCT/JP2009/067442 2008-10-16 2009-09-30 ウェハのパターン検査方法及び装置 WO2010044358A1 (ja)

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JP2008267384 2008-10-16
JP2008-267384 2008-10-16
JP2008286708A JP5460023B2 (ja) 2008-10-16 2008-11-07 ウェハのパターン検査方法及び装置
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JP5941782B2 (ja) * 2012-07-27 2016-06-29 株式会社日立ハイテクノロジーズ マッチング処理装置、マッチング処理方法、及びそれを用いた検査装置
WO2014038419A1 (ja) * 2012-09-05 2014-03-13 コニカミノルタ株式会社 光学特性測定装置、プログラム、および制御装置
KR101661023B1 (ko) * 2014-07-23 2016-09-29 에스엔유 프리시젼 주식회사 패턴의 결함 검사 방법
US10186028B2 (en) * 2015-12-09 2019-01-22 Kla-Tencor Corporation Defect signal to noise enhancement by reducing die to die process noise
CN105702597B (zh) * 2016-02-05 2019-03-19 东方晶源微电子科技（北京）有限公司 多工作台或多腔体检测系统
US10192302B2 (en) * 2016-05-25 2019-01-29 Kla-Tencor Corporation Combined patch and design-based defect detection
JPWO2020071234A1 (ja) * 2018-10-05 2021-09-02 日本電産株式会社 画像処理装置、画像処理方法、外観検査システムおよびコンピュータプログラム

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JPH11326231A (ja) * 1998-05-21 1999-11-26 Hitachi Electron Eng Co Ltd パターン付きウエハの異物検査装置
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JPH0416752A (ja) * 1990-05-11 1992-01-21 Toshiba Corp 欠陥検査装置
JPH11326231A (ja) * 1998-05-21 1999-11-26 Hitachi Electron Eng Co Ltd パターン付きウエハの異物検査装置
JP2004020356A (ja) * 2002-06-17 2004-01-22 Kita Denshi Corp 印刷物検査方法及び装置
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JP2008014717A (ja) * 2006-07-04 2008-01-24 Matsushita Electric Ind Co Ltd 欠陥検査システムおよび欠陥検査方法

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JP5460023B2 (ja) 2014-04-02
KR20110090901A (ko) 2011-08-10
JP2010117132A (ja) 2010-05-27
CN102177429A (zh) 2011-09-07
CN102177429B (zh) 2013-12-04
TWI480541B (zh) 2015-04-11
TW201024716A (en) 2010-07-01

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