WO2009145196A1 - Puce de semi-conducteur, substrat intermédiaire et dispositif à semi-conducteur - Google Patents

Puce de semi-conducteur, substrat intermédiaire et dispositif à semi-conducteur Download PDF

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Publication number
WO2009145196A1
WO2009145196A1 PCT/JP2009/059619 JP2009059619W WO2009145196A1 WO 2009145196 A1 WO2009145196 A1 WO 2009145196A1 JP 2009059619 W JP2009059619 W JP 2009059619W WO 2009145196 A1 WO2009145196 A1 WO 2009145196A1
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Prior art keywords
wiring
electrode
semiconductor chip
electrodes
semiconductor
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PCT/JP2009/059619
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English (en)
Japanese (ja)
Inventor
秦　英恵
中村　真人
正樹 中西
木下　順弘
山口　欣秀
順平 紺野
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株式会社ルネサステクノロジ
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Publication of WO2009145196A1 publication Critical patent/WO2009145196A1/fr

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Definitions

  • the present invention relates to a semiconductor chip and a semiconductor device on which the semiconductor chip is mounted, and more particularly to a technique that is effective when applied to a semiconductor device having a structure in which the semiconductor chip is mounted on a substrate or another chip by solder bumps.
  • connection part by the solder bump is generally more reliable than the connection part by the Au bump. That is, in the connection part by the Au bump, the Au bump itself can be softly deformed. For example, when the Au bump is connected by melting a solder layer formed in advance on the substrate electrode, the hard and brittle AuSn is formed. Since the compound precipitates at the connection part, if the stress caused by the change of heat during actual use or the stress caused by the difference in thermal expansion coefficient between materials becomes large, these stresses cannot be absorbed by the connection part. , Cracks occur, leading to breakage. As a method that does not involve a solder layer, it is possible to directly connect Au bumps to Au plated substrate electrodes by ultrasonic connection, thermocompression bonding, etc., but it may be difficult to ensure interface strength and to cope with narrow pitch. .
  • solder bumps when solder bumps are used, the compound is mainly generated only at the electrode interface, and the inside of the connection portion is composed of a solder component.
  • Solder has various compositions, but conventional Sn-Pb solder, Pb-free solder Sn-based, Sn-Ag-based, Sn-Cu-based, Sn-Ag-Cu-based solder can be plastically deformed and used It is possible to absorb the stress caused by the heat of time, the stress caused by the coefficient of thermal expansion between the materials, etc., by the deformation of the structure in the solder. For this reason, the reliability of the connecting portion is high, and it is often used for semiconductor devices used in automobile equipment and the like in which shock and vibration are particularly important problems.
  • solder bumps Another reason for using solder bumps is that when the number of pins of a semiconductor chip is required due to further enhancement of the functionality of electronic equipment, the use of Au bumps on electrodes by Al pads arranged around the chip, Since the necessary number of pins must be secured on the outer periphery, the chip area increases. In the case of a portable electronic device, it is important to be small and thin, and a semiconductor chip used inside is also required to be small and thin. For this reason, even if the number of electrodes is increased due to higher functionality, an increase in chip area is not allowed. Therefore, it is necessary to narrow the pitch between the electrodes, but there is a manufacturing limit in narrowing the pitch.
  • WLP Wafer Level Package
  • WPP WPP
  • rewiring is performed on the chip using Cu or the like from the electrode by the Al pad around the chip, the electrode is drawn out over the entire chip area, and solder bumps are formed on this electrode.
  • a semiconductor chip structure called “Wafer Process Package” or the like is used (for example, Patent Document 1).
  • the electrodes after the rewiring may be arranged over the entire chip area or may be arranged in several rows around the chip due to the routing of the counterpart substrate electrode.
  • solder bumps on each redistributed electrode such as plating using a resist, solder ball mounting and melting, and solder paste printing.
  • the solder bump height and composition are easy to form.
  • the thickness of the chip has been reduced due to the demand for thinner portable electronic devices.
  • chips having a thickness of 200 ⁇ m or less have been put into practical use, but it is possible to reduce the thickness to about 20 ⁇ m in research and development.
  • the substrate on which the semiconductor chip is mounted is often connected to a mother substrate of the apparatus body, and is called an intermediate substrate, an interposer substrate, etc., and a conductor wiring layer and an interlayer insulating resin layer are laminated,
  • a printed wiring board is used in which a plurality of electrodes are formed on one or both outermost surfaces by the conductor wiring layer, and the other is covered with a surface insulating resin layer.
  • a wiring made of Cu is usually formed on the surface of a core layer made of an insulating resin material, an interlayer insulating resin layer is formed on the surface, and upper and lower wirings are connected by through holes.
  • a printed wiring board (a so-called build-up substrate) in which a wiring layer of a necessary number of layers is formed by repeating a process of forming a conductor wiring layer of Cu usually on the layer is used.
  • the conductor wiring layer is usually Cu
  • the electrode formed on the outermost surface is Cu, an organic layer as a surface protective film on Cu, or a Ni layer on Cu to improve wettability
  • the structure is such that an Au layer is formed on the surface, or an Au layer is formed on Cu, or an Ni layer is formed on Cu, a Pd layer is formed on the surface, and an Au layer is formed on the surface.
  • a solder resist is usually used for the surface insulating resin layer in order to prevent bridging between adjacent solder bumps and to protect the surface wiring layer other than the electrodes.
  • the semiconductor chip when connecting a semiconductor chip by solder bumps, if the semiconductor chip is thick, it is mounted in alignment with the mating substrate electrode or chip electrode and heated by a reflow furnace. Then, the solder can be melted and connected to the substrate electrode or the chip electrode.
  • the surface stress is different between the surface where the device is formed and the surface where the device is not formed, and the chip is warped.
  • the warpage is about 2 mm when the wafer thickness is 400 ⁇ m, but the warpage at 200 ⁇ m is about 10 mm and 100 ⁇ m.
  • the thickness is about 50 mm and 50 ⁇ m, the wafer becomes round, and the amount of warpage increases as the thickness becomes thinner. Therefore, in the case of a thin semiconductor chip, even if it is aligned and heated in a reflow furnace to sufficiently melt the solder bump, it does not come into contact with the mating substrate electrode or chip electrode, making connection impossible.
  • thermocompression bonding it is conceivable to use a method in which a thin semiconductor chip is vacuum-adsorbed on a flat tool to eliminate warpage, align with the other substrate electrode and chip electrode, and connect by thermocompression bonding.
  • a method in which a thin semiconductor chip is vacuum-adsorbed on a flat tool to eliminate warpage, align with the other substrate electrode and chip electrode, and connect by thermocompression bonding.
  • thermocompression bonding For example, using a flip chip bonder, vacuum bonding a thin chip to a flat bonding head, aligning it, supplying heat from the bonding head, and melting solder bumps can be used as substrate electrodes or chip electrodes. Press to make contact and solder. Thereby, even a thin semiconductor chip can be connected without a problem of warping.
  • the problem here is that when pressurizing molten solder bumps, the molten solder is a liquid, so the solder bumps are easily deformed and easily collapsed, and adjacent bumps come into contact with each other to form a solder bridge, etc. It occurs. Therefore, when solder bumps are thermocompression bonded, it is required to control with low load so as not to bridge.
  • preheating can also be performed, and it is possible to suppress heat distribution due to a difference in heat conduction between the chip, the substrate, and the like.
  • the present invention solves these problems, and is a thin semiconductor chip having solder bumps, and even if the wiring shape varies from electrode to electrode, thermocompression bonding is performed in a short time with a high yield, and a highly reliable connection portion.
  • the present invention provides a semiconductor device intended to form a semiconductor device.
  • the present invention solves these problems, and even with a printed wiring board having a plurality of electrodes, even when the wiring shape and the surrounding wiring structure are different for each electrode, thermocompression bonding is performed in a short time with a high yield.
  • a semiconductor device for the purpose of forming a reliable connection portion is provided.
  • the outline of a representative one is that a plurality of electrodes formed on the first electrode among a plurality of electrodes connected to a circuit formed in an element formation layer on a semiconductor substrate are formed one by one on each of the plurality of electrodes.
  • Heat conduction wiring is connected to reduce the difference in the melting state of the solder bumps (ideally to make the solder bump melting state uniform), and the heat conduction wiring is formed by rewiring. It is characterized by that. Specifically, when the electrodes are formed on the whole or part of the chip area by rewiring from the peripheral Al pad electrodes on the device surface of the semiconductor chip, the lead-out wiring of each electrode is only meant as electrical wiring.
  • the electrode structure is provided with a dummy wiring as the heat conduction wiring so that the heat supply amount is uniform to some extent.
  • the dummy wiring at this time may be only one direction in a direction that does not affect the electrical signal, but may be formed in any direction.
  • dummy wires may be provided in order to make the molten state of the solder uniform even with electrodes having ground wires, power supply wires, and signal wires.
  • the plurality of electrodes on the surface of the substrate corresponding to the semiconductor chip have a structure in which heat conductive wiring for making the temperature of the electrodes uniform when connected is formed.
  • the structure in which the heat conduction wiring is formed immediately below the surface insulating resin layer in contact with the electrode, and the shape of the heat conduction wiring are different structures depending on the heat distribution of the electrode.
  • dummy wirings may be provided in one direction or in several directions on the surface layer.
  • either or both of the semiconductor chip that has been subjected to temperature uniformity and the substrate that has been subjected to temperature uniformity are used.
  • a thin semiconductor chip having solder bumps which can be thermocompression bonded in a short time with a high yield and has a highly reliable connection even when the wiring shape varies from electrode to electrode. can do.
  • thermocompression bonding with high yield in a short time even on substrates having different wiring shapes for each electrode.
  • a semiconductor device having a highly reliable connection portion can be provided by using a semiconductor chip or a substrate with improved thermal uniformity as described above, but by using both in combination, a shorter time and a higher yield can be provided. Can connect.
  • the semiconductor chip of one embodiment of this invention it is a figure which shows the cross-section of WPP with a dummy wiring. It is a figure which shows another example of the electrode structure in which the dummy wiring was formed in the semiconductor chip of one embodiment of this invention. It is a figure which shows another example of the electrode structure in which the dummy wiring was formed in the semiconductor chip of one embodiment of this invention. It is a figure which shows the flip chip BGA which is a semiconductor device which mounted the semiconductor chip of one embodiment of this invention. It is a figure which shows the package of the CoC structure which is a semiconductor device which mounted the semiconductor chip of one embodiment of this invention.
  • FIG. 1 It is a figure which shows the electrode structure which formed the dummy wiring in the package of the CoC structure which is a semiconductor device which mounted the semiconductor chip of one embodiment of this invention.
  • the semiconductor device which mounted the semiconductor chip of one embodiment of this invention it is a figure which shows the structure of the connection part in the thermocompression bonding process of a semiconductor chip.
  • the semiconductor device which mounted the semiconductor chip of one embodiment of this invention it is a figure which shows another electrode structure in which the dummy wiring was formed in the semiconductor device which mounted the semiconductor chip of one embodiment of this invention.
  • FIG. 6 is a view showing the vicinity of an interface with a substrate electrode at a connection portion of an outermost solder bump in a conventional substrate.
  • FIG. 6 is a view showing the vicinity of the interface with the substrate electrode at the connection portion of the third solder bump from the outermost periphery in the substrate of the prior art.
  • 1 is a diagram showing an electrode structure in which dummy through holes are formed in a substrate electrode in a semiconductor device using a substrate according to an embodiment of the present invention. In the semiconductor device using the board
  • FIG. 1 is a diagram showing an electrode structure in which dummy wirings are formed on a surface layer of a substrate electrode in a semiconductor device using a substrate according to an embodiment of the present invention. It is a figure which shows the wiring structure in case there is no extraction wiring in the semiconductor chip of a prior art. It is a figure which shows the wiring structure with wiring for signals in the semiconductor chip of a prior art. It is a figure which shows the wiring structure connected with the wiring for power supplies, or the ground wiring in the semiconductor chip of a prior art.
  • the semiconductor device is a WLP in which rewiring is performed on a chip using Cu or the like from an electrode formed by an Al pad around the chip, an electrode is drawn out over the entire chip area, and a solder bump is formed on the electrode.
  • a semiconductor chip structure called WPP or the like is used.
  • the electrodes after the rewiring may be arranged over the entire chip area or may be arranged in several rows around the chip due to the routing of the counterpart substrate electrode.
  • a method is used in which a thin semiconductor chip is vacuum-adsorbed on a flat tool to eliminate warpage, align with the substrate electrode and chip electrode of the counterpart, and connect by thermocompression bonding.
  • a flip chip bonder vacuum bonding a thin chip to a flat bonding head, aligning it, supplying heat from the bonding head, and melting solder bumps can be used as substrate electrodes or chip electrodes. Press to make contact and solder. Thereby, even a thin semiconductor chip can be connected without a problem of warping.
  • the heat distribution differs depending on the wiring shape on the semiconductor chip due to the supply of heat from the back surface of the semiconductor chip during thermocompression bonding.
  • the electrodes with ground wiring, power wiring, and signal wiring The temperature rises rapidly due to heat conduction, and the solder bumps are sufficiently heated and melted, and the fluidity of the solder is ensured and can be spread in a spherical shape.
  • the temperature rise is slow and the solder bumps are not sufficiently heated, so that the melting is insufficient, the solder fluidity is low, the solder cannot spread in a spherical shape, and the surface oxide film It is thought that it became an irregular shape by the influence of.
  • the void detachability in the solder bumps is reduced due to the decrease in the solder fluidity.
  • shape change of the solder after thermocompression bonding was investigated in detail, it was found that the shape of the solder after thermocompression bonding was different when the wiring thickness was different between the ground wiring, the power supply wiring, and the signal wiring. The difference in the shape of these solders becomes more prominent when heat is not sufficiently applied during thermocompression bonding.
  • a thin semiconductor chip having solder bumps is formed by thermocompression bonding at a high yield in a short time to form a highly reliable connection portion even when the wiring shape varies from electrode to electrode.
  • FIGS. A semiconductor chip according to an embodiment of the present invention will be described with reference to FIGS.
  • description will be made in comparison with the prior art.
  • the present embodiment an example in which the present invention is applied to a semiconductor chip on which 432 solder bumps are formed at a pitch of 250 ⁇ m is shown.
  • FIG. 2 shows the entire semiconductor chip of the present embodiment (same as the prior art).
  • the semiconductor chip 10 has an Al pad 11 arranged in the periphery, and electrodes 12 made of solder bumps are formed in an area array on the semiconductor chip 10 by rewiring. Therefore, the pitch of the electrode 12 by the solder bump is wider than that of the Al pad 11, and the wiring of the board to be connected can be easily routed.
  • a circuit is formed in an element formation layer on a semiconductor substrate, and electrodes 12 by solder bumps are formed on the surface of the element formation layer by rewiring.
  • FIG. 3 shows a part of the rewiring of the semiconductor chip 10 of the prior art.
  • electrodes 12 by solder bumps are arranged on the chip device surface by rewiring, and signal wirings 13, power supply wirings, or ground wirings 14 are drawn out from the respective electrodes.
  • electrodes 15 that have no lead wires because of the relationship between the number of electrodes by the Al pads 11 around the semiconductor chip and the number of electrodes 12 by the solder bumps arranged in the center by rewiring.
  • the solder bump array is more symmetrical and the subsequent underfill material injection and thermal fatigue reliability of the connection are higher, so an asymmetrical array structure in which the solder bumps are thinned to equalize the number of electrodes. This is because I don't want to take it.
  • FIG. 4 shows the result of heating and pressing the solder bumps on the semiconductor chip 10.
  • the heating and pressing conditions were such that the back of the chip device surface was brought into contact with a heater at 260 ° C., and a load of about 150 g was applied to the entire semiconductor chip 10 so that the solder bumps were crushed by about 40 ⁇ m.
  • the atmosphere is in the air.
  • the solder bumps of the electrodes connected to the signal wiring 13 and the solder bumps connected to the power supply wiring or the ground wiring 14 are round and spread almost uniformly around the periphery. Protrusions were formed around the solder bumps with no electrode 15 and spread in an irregular shape.
  • solder bumps shown in FIG. 4 the result of observing the solder bumps 16 spreading in a crack by SEM is shown in FIG.
  • the solder bumps 16 spreading in a distorted manner have a shape in which the solder is not spherical but has a sharp periphery. Further, as can be seen from FIG. 4, it is considered that the solder having an irregular color on the solder surface is brown and a lot of surface oxide film remains.
  • the thermal conductivity differs depending on the shape of the lead-out wiring to the electrode of each solder bump, as shown in FIG. That is, when heated from the back of the chip device surface by the bonding head, the temperature rise rate differs for each solder bump, and the solder bump connected to the power supply wiring or ground wiring 14 is supplied with heat from the wiring and the melting point of the solder. Since it has sufficiently reached the above, the molten solder has high fluidity, good void detachability, can be spread around the circumference almost uniformly, and has high connection reliability.
  • solder bump on the electrode 15 having no lead-out wiring could not secure a time longer than the melting point of the solder, so that the solder fluidity is low and it is considered that the solder bump spread around the periphery. If it spreads in an irregular shape, the probability of bridging with adjacent bumps increases, and the surface oxide film remains, resulting in low wettability, insufficient void detachment, and low connection reliability. It is predicted.
  • the electrode connected to the power supply wiring or the ground wiring 14 has a large hole in the solder (the shading in FIG. 4). It is seen that the void has been removed), but a small hole was seen in the electrode connected to the signal wiring 13, but it was seen in the electrode connected to the power wiring or ground wiring 14. There wasn't enough holes. In the electrode 15 having no lead-out wiring, holes are not clearly seen, and it is considered that voids are not easily removed. Therefore, it is considered that there is a difference in the solder fluidity depending on the wiring shape from the electrode.
  • a semiconductor chip as shown in FIG. 6 (showing part of the rewiring of the semiconductor chip) is used.
  • a dummy wiring (heat conduction wiring) 17 is provided on the electrode 15 having no lead-out wiring, and the semiconductor chip 18 is provided with the dummy wiring.
  • FIG. 1 Details of the electrode structure in which the dummy wiring 17 is formed are shown in FIG.
  • a dummy wiring 17 is formed, and a surface layer 19 made of polyimide is formed on the surface around the electrode.
  • the polyimide surface layer 19 defines an opening 20 to which a solder bump is connected, and the actual rewiring layer 21 extends to a circular dotted line.
  • Solder bumps 22 are formed in the opening 20.
  • FIG. 7 shows a cross-sectional structure of a conventional WPP.
  • an Al pad 11 is formed around the semiconductor chip 10, and a passivation film 23 is formed on the surface.
  • a polyimide layer 24 having an Al pad 11 portion opened is formed on the surface of the passivation film 23 .
  • the polyimide layer 24 is formed by applying a photosensitive polyimide resin film over the entire surface, opening the Al pad 11 by heat treatment (pre-baking), exposure, and development, and then performing heat treatment to cure the polyimide resin film.
  • a Cr / Cu film 26, a Cu film 27, and a Ni film 28 are formed as a rewiring layer 25 in a laminated structure.
  • the rewiring layer 25 is formed by depositing Cr / Cu as a seed layer for electrolytic plating by sputtering, forming a resist layer having a rewiring groove on the seed layer by a photolithography technique. A Cu film 27 and then a Ni film 28 are formed only inside, and the resist layer and an unnecessary portion of the seed layer (Cr / Cu) are removed.
  • solder bumps 22 are formed in the openings of the surface layer 19 made of polyimide.
  • This solder bump 22 is formed by performing electroless Au plating on the Ni surface of the opening portion of the surface layer 19 made of polyimide, forming an Au plating film, and forming the solder bump 22 in the opening portion by a printing method, a solder ball mounting method, or the like. To do.
  • the above electroless Au plating layer is thin, it dissolves in the solder when solder bumps are connected and does not remain as a layer at the interface, so it is not shown in FIG.
  • the above is the conventional method for forming the redistribution layer of WPP.
  • FIG. 8 shows a cross-sectional structure of the WPP having the dummy wiring of the present embodiment.
  • the dummy wiring 17 is formed on the electrode 15 having no lead wiring.
  • the method for forming the rewiring layer 25 having the dummy wirings 17 is also the same as in the case of FIG. Therefore, in the WPP of the present embodiment, the dummy wiring 17 can be formed by the same rewiring forming process as that of the conventional WPP, which contributes to the improvement of the yield at the time of thermocompression bonding although it hardly leads to an increase in manufacturing cost. Is possible.
  • the dummy wiring 17 As the shape of the dummy wiring 17, it is important to draw it in a direction that does not affect the performance of the semiconductor chip. Therefore, in the example of FIG. 1 described above, the dummy wiring 17 is drawn out in one direction. However, as shown in FIG. 9 (another example of the electrode structure in which the dummy wiring is formed), a plurality of directions (four directions in FIG. 9) are used. In this example, the dummy wiring 17 may be drawn out. Therefore, when the dummy wiring 17 is used as shown in FIG. 6 described above, any solder bump has a uniform temperature rise at the time of heating and pressurization, and the solder bump having a low temperature rise does not spread in an irregular manner.
  • FIG. 10 shows another example of another electrode structure.
  • the rewiring layer 21 below the surface layer 19 made of polyimide is used as the opening of the polyimide layer. It is also possible to take an extremely larger value than 20.
  • FIG. 10 shows a conventional wiring structure 201 without a lead wiring
  • FIG. 25 shows a conventional wiring structure 203 with a signal wiring 202
  • FIG. 26 shows a conventional wiring structure 205 connected to a power supply wiring or a ground wiring 204. This is an example.
  • FIG. 24 and FIG. 10 are compared.
  • the diameter of the opening 20 to which the solder bump is connected which is defined by opening the polyimide, is the same in both cases.
  • the electrode area 206 is set larger than that of a normal rewiring layer formed under the surface layer 19 made of polyimide shown in FIG. By changing this shape, the temperature in the chip can be made more uniform.
  • the wiring structure shown in FIG. 10 is also clearly different from the conventional wiring structure shown in FIGS. 25 and 26 having lead-out wiring, and an opening 20 to which solder bumps are connected, which is defined by opening polyimide.
  • the diameters of all of these are the same, but there is no lead wiring, but the dummy wiring 17 is set to be larger than the electrode area 206 of the normal rewiring layer formed under the surface layer 19 of normal polyimide. It is a structure.
  • solder bumps on which the signal wirings 13 are formed have electrodes with a slow temperature rise, it is also effective to add dummy lead-out wirings.
  • the shape and width of this dummy wiring can be optimized by thermal simulation.
  • the detailed structure such as the redistribution layer, solder bump, dummy wiring, etc. of the semiconductor chip described above, and physical properties such as specific heat, density, thermal conductivity of each material are input, and the bonding tool on the back surface of the semiconductor chip 10 is input.
  • An optimum dummy wiring shape can be obtained by calculating the temperature of the solder bump portion after a certain period of time when heat is applied.
  • thermocompression bonding In order to reduce the heat distribution between the electrodes on the semiconductor chip, dummy electrodes that are particularly problematic during thermocompression bonding are connected to the surrounding signal wiring, power wiring, and ground wiring. It is also possible to connect them. However, depending on the structure of the width and thickness of each layer of the semiconductor device and the rewiring layer, this method may affect the electrical characteristics of the semiconductor device through the polyimide layer and generate noise. For this reason, it is difficult to connect a dummy electrode, which is likely to be a problem at the time of thermocompression bonding, with surrounding electrodes, and using a dummy wiring is also effective in terms of electrical characteristics.
  • ⁇ Flip chip BGA> A semiconductor device mounted with a semiconductor chip according to an embodiment of the present invention will be described with reference to FIG.
  • the semiconductor shown in FIG. An example in which the chip 18 is actually applied will be shown.
  • the semiconductor device shown in FIG. 11 is a flip chip BGA (Ball Grid Array) 41, and a semiconductor chip 18 provided with dummy wirings is mounted on an interposer substrate (intermediate substrate).
  • the thickness of the interposer substrate 42 is 0.8 mm, and the material is mainly a glass epoxy organic substrate.
  • the semiconductor chip 18 was aligned with the interposer substrate 42, the solder bumps 43 were melted by thermocompression bonding, the electrodes were connected, and the resin 44 was sealed between the semiconductor chip 18 and the interposer substrate 42. Further, the upper part was sealed with a mold resin 45, and solder bumps 46 of external terminals were attached to the back surface of the interposer substrate 42.
  • thermocompression bonding is performed in the air, but the wettability is improved even if an inert gas such as N 2 is blown around the periphery. Further, it is effective to improve wettability by thinning the surface oxide film by performing Ar sputtering, plasma cleaning or the like on the solder surface before thermocompression bonding. In addition, it is also possible to supply flux to solder bumps or substrate electrodes and perform thermocompression bonding, and the use of flux improves wettability. In this case, cleaning may be performed, but if there is no problem in reliability thereafter, the resin may be sealed without cleaning.
  • the mold resin 45 may be omitted.
  • the semiconductor chip 18 When the semiconductor chip 18 generates a large amount of heat, it is possible to attach a heat radiation fin or the like to the upper surface of the semiconductor chip 18.
  • a memory or the like may be stacked on the upper surface of the semiconductor chip 18 and connected by wire bonding using Au wires to form a so-called stacked package structure.
  • an external terminal may be provided on the outer periphery of the interposer substrate 42 shown in FIG. 11 and connected to another package on which a memory or the like is mounted to form a PoP (Package on Package) structure.
  • PoP Package on Package
  • ⁇ CoC structure package> Another semiconductor device mounted with a semiconductor chip according to an embodiment of the present invention will be described with reference to FIG.
  • a semiconductor chip provided with dummy wirings has a CoC (Chip on Chip) structure.
  • CoC Chip on Chip
  • the semiconductor device shown in FIG. 12 is a package 51 having a CoC structure, but this semiconductor chip 52 is drawn from the electrode 53 in order to improve the thermal uniformity in the chip during thermocompression bonding as shown in FIG.
  • a dummy wiring 55 is provided in addition to the signal wiring 54.
  • a polyimide layer 56 is formed thereon.
  • a gap 57 is formed between the electrode 53 and the polyimide layer 56.
  • This part consists of another polyimide layer below the electrode 53 layer. Even when the signal wiring 54 is formed in this way, it is effective to use the dummy wiring if the temperature does not rise uniformly during thermocompression bonding.
  • the semiconductor chip 52 having this electrode structure was vacuum-adsorbed to the bonding head, and this was aligned with the electrode of another semiconductor chip 58, and thermocompression bonding was performed.
  • the solder bump 59 was uniformly melted in a short time and connected to the electrode of another semiconductor chip 58.
  • the resin 60 was sealed between the two chips, connected to the interposer substrate 61 by the die bond material 62, and the semiconductor chip 58 and the interposer substrate 61 were connected by the Au wire 63.
  • the periphery was sealed with resin 64, and solder bumps 65 for external terminals were formed.
  • the solder bump 59 may be formed only on the upper semiconductor chip 52 or the lower semiconductor chip 58, or may be formed on both semiconductor chips in order to increase the connection height. Further, dummy wiring can be provided on the semiconductor chip 58 or both, and the temperature distribution during thermocompression bonding can be reduced.
  • the cost can be reduced by shortening the connection time, and the reliability can be improved by uniformizing the connection portion structure and interface state. It is possible.
  • FIG. 14 shows a structure of a connection portion in a thermocompression bonding process in which a semiconductor chip is thermocompression bonded to an interposer substrate in the semiconductor device as described above.
  • a thin semiconductor chip 71 having a thickness of 100 ⁇ m was vacuum-adsorbed to the bonding head 72 to eliminate chip warpage, and then aligned with the electrode 74 of the interposer substrate 73.
  • the electrode 74 of the interposer substrate 73 has Ni plating (2 ⁇ m) on the Cu wiring and Au plating (0.1 ⁇ m) on the surface.
  • the composition of the solder bump 75 on the semiconductor chip 71 is Sn-0.5Ag-0.7Cu, and the amount of Ag is smaller than that of normal Sn-3Ag-0.5Cu, because the amount of Ag3Sn in the solder is reduced and the solder is reduced. This is to improve the ductility of the metal and relax the stress generated in the connecting portion to improve the reliability.
  • the pitch of the solder bumps 75 is 150 ⁇ m, and the height of the solder bumps 75 is 70 ⁇ m.
  • This solder bump 75 was formed by filling a ball mounting mask having an opening corresponding to the re-wired electrode 76 of the semiconductor chip 71 with the solder ball, transferring it, and heating it.
  • the semiconductor chip 71 is heated and pressed in the direction of the arrow (heat and pressure direction 77) in the drawing to melt the solder bump 75 and connect to the electrode 74 at the opening of the solder resist layer 81 on the interposer substrate 73. I let you.
  • the thermocompression bonding conditions were performed by setting the tool temperature to 280 ° C., applying a load of 20 g, and heating and pressing for 10 seconds.
  • FIG. 15 shows the wiring shape of one electrode in the semiconductor chip.
  • Dummy wirings 78 are formed in three directions on the electrode 74, and signal wirings 79 are formed in one direction.
  • a polyimide layer 80 is formed on the dummy wiring 78 and the signal wiring 79 except for the opening 82 of the polyimide layer.
  • the dummy wiring 78 is determined by measuring the actual heat distribution, but may be determined by simulation of the surface temperature. Moreover, it is also possible to determine by a simple method in which the area of the wiring occupying a certain area around the electrode is substantially the same.
  • the configuration of the electrode (also referred to as substrate electrode) 102 of the substrate 101 is the Ni layer 104 on the Cu layer 103 of the surface conductor layer, the Pd layer 105 on this surface, and further the Pd layer An Au layer 106 is formed on the surface of 105.
  • the periphery of the electrode 102 is surrounded by a solder resist 107 which is an insulating material.
  • the thermocompression bonding conditions are as follows. The surface opposite to the solder bump surface of the semiconductor chip 10 of FIG. 2 is vacuum-adsorbed to the bonding tool, aligned with the electrode 102 of the corresponding substrate 101, the bonding tool is lowered, and the solder contacts. After about 20 ⁇ m, the bonding tool was heated at 350 ° C.
  • FIG. 17 shows a cross section of the connecting portion 112 of the outermost solder bump (111 in FIG. 2) and the connecting portion 114 of the third solder bump (113 in FIG. 2) from the outermost periphery. From this, a flat interface compound layer 115 is formed at the interface between the outermost solder bump connection portion 112 and the substrate electrode 102, and the intermetallic compound 116 gathers in the solder structure near the electrode on the semiconductor chip 10 side.
  • connection portion 114 of the third solder bump 113 from the outermost periphery the interface 118 with the substrate electrode 102 is formed by the compound 118 dispersed in the solder structure as the flat interface compound layer 115 shown in FIGS.
  • one thin compound layer 119 was formed on the Ni layer 104.
  • the result of observing this connection interface with SEM is shown in FIG. From the observation result by SEM, a thin compound layer 119 was observed on the Ni layer 104, and the compound 118 dispersed in the solder structure 120 was observed.
  • connection interface for each solder bump was examined in detail for other solder bump positions, and it was found that there was a correlation with the wiring structure in the substrate. That is, as can be seen from FIG. 17, the Cu wiring 126 is located immediately below the Cu layer 103 of the substrate electrode 102 for the outermost solder bump 111 via the interlayer insulating resin layer 108 made of glass epoxy resin. However, Cu wiring is also provided in the interlayer insulating resin layer 108 and in the inner layer of the substrate via the interlayer insulating resin layer 108 directly below the Cu layer 103 of the substrate electrode 102 for the third solder bump 113 from the outermost periphery. No. This is because each of the semiconductor chip electrodes plays a role, and therefore, the routing of the wiring inside the substrate is different for each electrode, thereby taking a different wiring structure around each substrate electrode.
  • the heat transmitted through the semiconductor chip 10 and the connection part 112 in contact with the bonding tool is propagated to the surroundings by the Cu wiring 126. Therefore, it is considered that the time during which the solder bumps are actually melted is short.
  • the heat transferred through the semiconductor chip 10 and the connection portion 114 in contact with the bonding tool does not exist in the connection portion because there is no Cu wiring layer directly under the electrode 102. It is estimated that the time during which the solder bumps are actually melted is longer than that of the outermost solder bump 111.
  • a flat interface compound layer 115 is first formed at the connection interface with the substrate electrode 102.
  • the outermost solder bump connection portion 112 has a short melting time.
  • the temperature drops and solidifies, but the third solder bump connecting portion 114 from the outermost periphery is still melted at this stage, and the flat interfacial compound layer 115 generated at the beginning is peeled off, and the solder is formed in the solder. It is believed that it remained as dispersed compound 118.
  • the difference in the intermetallic compound 116 deposited in the vicinity of the electrodes of the semiconductor chip 10 is considered to have a correlation with the magnitude of the temperature gradient inside the solder bump connection portion. That is, in the connection portion 112 of the outermost solder bump 111, heat escapes into the substrate, so the temperature of the substrate electrode is predicted to be low and the temperature gradient in the connection portion is large. A large amount of the intermetallic compound 116 was collected because it was in the vicinity of the interface with. However, in the connection part 114 of the third solder bump 113 from the outermost periphery, it is predicted that the compound is dispersed inside the solder and the temperature gradient in the connection part is small.
  • the heating temperature of the substrate cannot be set high due to the heat resistance problem of the substrate, particularly in a short time thermocompression bonding process, and the difference between the bonding tool temperature and the substrate temperature becomes large, the wiring structure of the substrate Depending on the solder bump, the melted state is likely to be different for each solder bump, which appears to be a difference in the solder structure of the connecting portion and the connection interface structure.
  • solder bumps were made of Sn-3Ag-0.5Cu.
  • the connection structure is formed in the short-time thermocompression process by the wiring structure of the substrate. A difference has occurred.
  • connection portion 112 of the outermost solder bump 111 where 115 remains when stress is generated at the end of the substrate electrode 102 and the end of the semiconductor chip 10 due to a temperature change during actual use, cracks occur near both interfaces. It is easy to break.
  • connection portion 114 of the third solder bump 113 from the outermost periphery where the compound tends to be uniformly dispersed in the solder it is not easily broken when stress is concentrated on the electrode end portion, and the thermal fatigue reliability It is considered that the nature is high.
  • thermocompression bonding process since the actual heating temperature in the thermocompression bonding process varies from solder bump to solder bump, the amount of electrode material dissolved into the solder bump differs, resulting in differences in solder physical properties such as mechanical characteristics and melting characteristics. .
  • connection parts with different thermal fatigue characteristics, solder physical properties, etc.
  • the substrate electrode is Cu / Ni / Pd / Au
  • the surface layer is, for example, Cu / Ni / Au, Cu / Au, Cu alone, or an electrode obtained by subjecting Cu to rust prevention treatment.
  • the thickness of the compound layer is different, the amount of electrode material that dissolves in the solder is different, and the physical properties of the solder (mechanical properties, melting characteristics, etc.) are different. Therefore, it can be said that reliability design is difficult.
  • a conductor wiring layer and an interlayer insulating resin layer are laminated, and a plurality of electrodes are formed on one or both outer surfaces by the conductor wiring layer.
  • a dummy through hole is provided as a heat conduction wiring in the substrate so that the heat distribution between the electrodes in the substrate is uniform. It has a structure in which holes and dummy wirings are formed.
  • FIG. 20 shows an example in which a dummy through hole 121 is formed immediately below the electrode 102 on the surface of the substrate 101. The through-hole depth and diameter of the dummy through-hole can be adjusted according to the heat distribution. This example is shown in FIG. 21, but a dummy through-hole 122 having a small diameter is formed.
  • FIG. 22 shows an example in which a dummy wiring is formed as a heat conduction wiring instead of a through hole.
  • This substrate has a structure in which a dummy wiring 124 made of Cu is provided via an interlayer insulating resin layer 123 immediately below the electrode 102 on the surface of the substrate 101.
  • the dummy wiring 124 corresponds to a different shape according to the heat distribution.
  • the dummy wirings are difficult to distinguish from those of ordinary electrodes from the drawings showing one cross-sectional structure as shown in FIGS. Further, although not shown this time, it is difficult to understand the difference from the normal wiring structure from the diagram showing one planar structure. However, when considered three-dimensionally, the dummy wiring is characterized in that the leading end of the wiring is interrupted in the substrate, and unlike a normal wiring, the dummy wiring is electrically meaningless.
  • the structure of both the semiconductor chip 10 and the substrate 101 is improved by providing wiring for heat conduction such as dummy wiring and dummy through-hole, thereby shortening the tact time of the thermocompression bonding process. And a highly reliable semiconductor device can be obtained.
  • the effect obtained by a typical one is that when a thin semiconductor chip having solder bumps is connected by thermocompression bonding, the distribution of heat between each electrode on the semiconductor chip can be reduced, so that the connection margin is widened. Connection in a short time is possible, the number of production per unit time can be increased, and it can contribute to cost reduction.
  • the heat distribution between the electrodes is almost uniform, the actual temperature load of the solder bumps is almost uniform, and the state of the interface compound, the structure, etc. are almost uniform between the electrodes, and the reliability design Can be facilitated and contribute to high reliability.
  • the voids in the connection part which has been a problem in the past, can be improved in the void removability if the flowability of the solder can be sufficiently secured in any electrode, thereby contributing to the extension of the life of the connection part reliability.
  • the semiconductor chip of the present invention and a semiconductor device mounted with the semiconductor chip can be used for semiconductor devices used in information equipment, portable equipment, automobile equipment, and the like.
  • SYMBOLS 10 Semiconductor chip, 11 ... Al pad, 12 ... Electrode by solder bump, 13 ... Signal wiring, 14 ... Power supply wiring or ground wiring, 15 ... Electrode without lead-out wiring, 16 ... Solder bump spread in distorted, 17 ... dummy wiring, 18 ... semiconductor chip provided with dummy wiring, 19 ... surface layer made of polyimide, 20 ... opening to which solder bump is connected, 21 ... rewiring layer, 22 ... solder bump, 23 ... passivation film, 24 ... Polyimide layer, 25 ... redistribution layer, 26 ... Cr / Cu film, 27 ... Cu film, 28 ... Ni film, 41 ... flip chip BGA, 42 ...
  • interposer substrate 43 ... solder bump, 44 ... resin, 45 ... mold resin 46 ... Solder bumps of external terminals, 51 ... CoC structure package, 52 ... Semiconductor chip provided with dummy wirings, 53 Electrode, 54 ... Signal wiring, 55 ... Dummy wiring, 56 ... Polyimide layer, 57 ... Gap between polyimide layer and electrode, 58 ... Separate semiconductor chip, 59 ... Solder bump, 60 ... Resin, 61 ... Interposer substrate, 62 ... Die bond material, 63 ... Au wire, 64 ... Resin, 65 ... Solder bump of external terminal, 71 ... Semiconductor chip, 72 ... Bonding head, 73 ... Interposer substrate, 74 ...
  • the conventional wiring structure connected to the electrode 206, the electrode area of the normal rewiring layer formed under the surface layer of polyimide.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention porte sur un dispositif à semi-conducteur dans lequel une section de connexion très fiable est formée par réalisation d'un collage par thermocompression en une courte durée à haut rendement, même une forme de câblage varie par électrode dans une puce de semi-conducteur mince comprenant des bosses de soudure. Dans une puce de semi-conducteur (10), à une électrode (15) n'ayant pas de câblage d'extraction, parmi une pluralité d'électrodes connectées à un circuit formé sur une couche de formation d'élément sur un substrat semi-conducteur, un câblage fictif (17) est connecté pour uniformiser l'état de fusion de bosses de soudure (22) formées sur l'électrode, et le câblage fictif (17) est formé d'une couche de recâblage (21). Le câblage fictif (17) est extrait au besoin de l'électrode de façon à éliminer une distribution de température entre les bosses de soudure (22) sur la puce de semi-conducteur (10), et la chaleur entre les électrodes dans la puce de semi-conducteur (10) est uniformisée. En outre, sur un substrat qui correspond à la puce de semi-conducteur, un câblage fictif et un trou traversant sont formés correspondant à une distribution de chaleur, et une structure à distribution de chaleur réduite entre les électrodes est formée.
PCT/JP2009/059619 2008-05-27 2009-05-26 Puce de semi-conducteur, substrat intermédiaire et dispositif à semi-conducteur WO2009145196A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012043990A (ja) * 2010-08-19 2012-03-01 Fujikura Ltd 配線基板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0883865A (ja) * 1994-09-14 1996-03-26 Citizen Watch Co Ltd 樹脂封止型半導体装置
JPH0964049A (ja) * 1995-08-30 1997-03-07 Oki Electric Ind Co Ltd チップサイズパッケージ及びその製造方法
JPH10214911A (ja) * 1997-01-28 1998-08-11 Toshiba Corp 半導体装置搭載用基板
JP2005294720A (ja) * 2004-04-05 2005-10-20 Seiko Epson Corp 半導体装置及びその製造方法並びに電子機器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0883865A (ja) * 1994-09-14 1996-03-26 Citizen Watch Co Ltd 樹脂封止型半導体装置
JPH0964049A (ja) * 1995-08-30 1997-03-07 Oki Electric Ind Co Ltd チップサイズパッケージ及びその製造方法
JPH10214911A (ja) * 1997-01-28 1998-08-11 Toshiba Corp 半導体装置搭載用基板
JP2005294720A (ja) * 2004-04-05 2005-10-20 Seiko Epson Corp 半導体装置及びその製造方法並びに電子機器

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012043990A (ja) * 2010-08-19 2012-03-01 Fujikura Ltd 配線基板

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