WO2009144828A1 - Unité de tranche pour test et système de test - Google Patents

Unité de tranche pour test et système de test Download PDF

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Publication number
WO2009144828A1
WO2009144828A1 PCT/JP2008/060079 JP2008060079W WO2009144828A1 WO 2009144828 A1 WO2009144828 A1 WO 2009144828A1 JP 2008060079 W JP2008060079 W JP 2008060079W WO 2009144828 A1 WO2009144828 A1 WO 2009144828A1
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WO
WIPO (PCT)
Prior art keywords
test
unit
power supply
wafer
semiconductor
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PCT/JP2008/060079
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English (en)
Japanese (ja)
Inventor
芳雄 甲元
芳春 梅村
新一 濱口
康男 徳永
康 川口
Original Assignee
株式会社アドバンテスト
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社アドバンテスト filed Critical 株式会社アドバンテスト
Priority to PCT/JP2008/060079 priority Critical patent/WO2009144828A1/fr
Priority to PCT/JP2009/002370 priority patent/WO2009144948A1/fr
Priority to JP2010514379A priority patent/JPWO2009144948A1/ja
Priority to TW098118029A priority patent/TWI393200B/zh
Publication of WO2009144828A1 publication Critical patent/WO2009144828A1/fr

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G01R31/318511—Wafer Test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3004—Current or voltage test
    • G01R31/3008—Quiescent current [IDDQ] test or leakage current test

Definitions

  • the present invention relates to a test wafer unit.
  • the present invention relates to a test wafer unit including a test substrate having a plurality of current detection units for detecting a quiescent current supplied to each semiconductor chip in a semiconductor wafer on which a plurality of semiconductor chips are formed, and the test wafer
  • the present invention relates to a test system including a wafer unit.
  • the apparatus includes a probe card that can be electrically connected to a plurality of semiconductor chips on a semiconductor wafer in a lump, and can test a plurality of semiconductor chips at the same time.
  • the conventional test apparatus including the above apparatus includes a circuit that generates a test pattern, a circuit that detects a response signal from a semiconductor chip to be tested, etc. It was provided on the connected controller side. Therefore, when the power supply current in a stationary state is measured for a CMOS circuit of a semiconductor chip, since the measured current is very small, the detection error due to the influence of line noise is large. However, for example, it is difficult to mount probes and corresponding circuits as many as the number of semiconductor chips on the probe card in terms of the size of the probe card and the manufacturing cost.
  • an object of the present invention is to provide a test wafer unit that can solve the above-mentioned problems and a test system including the test wafer unit. This object is achieved by a combination of features described in the independent claims.
  • the dependent claims define further advantageous specific examples of the present invention.
  • a test wafer unit electrically connected to a plurality of semiconductor chips formed on a semiconductor wafer, the test wafer unit being disposed facing the semiconductor wafer.
  • a plurality of power supply terminals provided at least one for each semiconductor chip and electrically connected to a power input terminal of the corresponding semiconductor chip, and the test substrate.
  • the test wafer unit is provided with a plurality of current detectors provided at least one for each semiconductor chip and detecting a quiescent current supplied to the semiconductor chip via each power supply terminal.
  • a test system for testing a plurality of semiconductor chips formed on a semiconductor wafer, wherein the test wafer is electrically connected to the plurality of semiconductor chips formed on the semiconductor wafer. And a control device for controlling the test wafer unit.
  • the test wafer unit includes at least one test substrate disposed opposite to the semiconductor wafer and each semiconductor chip in the test substrate.
  • a plurality of power supply terminals electrically connected to the power input terminals of the corresponding semiconductor chips, and at least one power supply terminal for each semiconductor chip in the test substrate, and each power supply
  • a test system having a plurality of current detection units for detecting a quiescent current supplied to a semiconductor chip through a terminal is provided. It is.
  • FIG. 2 is a diagram showing an example of a cross section of a unit cell 111-1 of a test substrate 110 and a semiconductor chip 310-1 of a semiconductor wafer 300.
  • FIG. 2 is a schematic diagram illustrating an example of a circuit configuration of a CMOS circuit 330.
  • FIG. 3 is a block diagram illustrating a functional configuration example of a test circuit 130.
  • 3 is a block diagram illustrating a functional configuration example of a power supply current measuring unit 550.
  • FIG. It is the schematic which shows the structural example of the test system 401 which concerns on one Embodiment of this invention.
  • 2 is a diagram showing an example of a cross section of a unit cell 111-1 of a test substrate 140 and a semiconductor chip 310-1 of a semiconductor wafer 300.
  • FIG. 1 is a schematic diagram showing a configuration example of a test system 400 according to an embodiment of the present invention.
  • the test system 400 of this embodiment is a system for testing a semiconductor wafer 300 to be tested, and includes a control device 10 and a test wafer unit 100.
  • a semiconductor wafer 300 to be tested in the test system 400 includes a plurality of semiconductor chips 310 (310-) including CMOS circuits 330 (330-1, 330-2,...) As shown in FIG. 1, 310-2,...) May be a disk-shaped semiconductor substrate.
  • the plurality of semiconductor chips 310 may be formed on the semiconductor wafer 300 by using a semiconductor process such as exposure.
  • the test wafer unit 100 includes a test substrate 110.
  • the test substrate 110 may be a semiconductor substrate in which a predetermined circuit is formed on a wafer substrate having a shape corresponding to the semiconductor wafer 300, and is disposed to face the semiconductor wafer 300.
  • the semiconductor wafer 300 is a disk-shaped semiconductor substrate
  • the test substrate 110 has a circular shape, a semicircular shape, a sector shape, or the like that has substantially the same diameter as the semiconductor wafer 300 or a larger diameter than the semiconductor wafer 300. It may be a semiconductor substrate.
  • the shape of the test substrate 110 is not limited to this as long as it is a shape facing at least a part of the upper surface of the semiconductor wafer 300.
  • the test substrate 110 has a plurality of unit cells 111 (111-1, 111-2,%) Provided at positions corresponding to the plurality of semiconductor chips 310 in the semiconductor wafer 300.
  • Each of the plurality of unit cells 111 is provided with a test circuit 130 (130-1, 130-2,...) That generates a test signal for testing the corresponding semiconductor chip 310. That is, the unit cell 111-1 of the test substrate 110 is disposed to face the semiconductor chip 310-1 of the semiconductor wafer 300, and the test circuit 130-1 is provided in the unit cell 111-1.
  • the plurality of test circuits 130 may be formed on the test substrate 110 using a semiconductor process such as exposure.
  • the control device 10 controls a test program for the semiconductor wafer 300 by the test system 400.
  • the control device 10 may supply various control signals for testing the corresponding semiconductor chip 310 to each test circuit 130 of the test substrate 110. Further, the control device 10 may supply a power supply voltage to be applied to each semiconductor chip 310 via the test circuit 130.
  • Each test circuit 130 may generate a test signal corresponding to the test pattern and supply it to the corresponding semiconductor chip 310 in response to receiving the control signal from the control device 10.
  • each test circuit 130 detects a power supply current (IDDQ) at rest in various operating states of the CMOS circuit 330 provided in the corresponding semiconductor chip 310, and digital data corresponding to the detected power supply current (IDDQ). May be sent to In this case, the control device 10 may determine pass / fail of each semiconductor chip 310 based on the digital data received from the test circuit 130.
  • the power supply current at rest will be described in detail later.
  • the test wafer 110 having a shape corresponding to the semiconductor wafer 300 is provided with a plurality of test circuits 130 corresponding to the respective semiconductor chips 310, whereby the semiconductor wafer 300 is provided. All semiconductor chips 310 in can be tested simultaneously.
  • each test circuit 130 is formed on the test substrate 110 using a semiconductor process, a larger number of test circuits are provided on the test substrate 110 than when the test circuit is mounted on the printed circuit board. It can be formed easily.
  • FIG. 2 is a diagram illustrating an example of a cross section of the unit cell 111-1 of the test substrate 110 and the semiconductor chip 310-1 of the semiconductor wafer 300.
  • the unit cell 111-1 in the test substrate 110 and the semiconductor chip 310-1 facing the unit cell 111-1 in the semiconductor wafer 300 are extracted and shown. Since the unit cells 111 other than the unit cell 111-1 shown in FIG. 2 have the same configuration, description thereof is omitted. Also, the semiconductor chips 310 other than the semiconductor chip 310-1 have the same configuration, and thus the description thereof is omitted.
  • the test circuit 130-1 and the device side terminals 114 and 115 are provided on the back surface of the unit cell 111-1 facing the semiconductor chip 310-1 (hereinafter referred to as “the upper surface 112 of the unit cell 111-1”). .
  • the signal supply terminal 120 and the power supply terminal 121 are provided on the surface of the unit cell 111-1 that faces the semiconductor chip 310-1 (hereinafter referred to as “the lower surface 113 of the unit cell 111-1”).
  • the signal supply terminal 120 and the power supply terminal 121 may be provided at positions corresponding to the signal input terminal 320 and the power input terminal 321 provided on the upper surface of the semiconductor chip 310-1.
  • a plurality of vias 117 are provided penetrating from the upper surface 112 to the lower surface 113.
  • One end of the via 117-1 on the upper surface 112 side is electrically connected to the device-side terminal 114 and also electrically connected to the test circuit 130-1 via the pattern wiring 116 formed on the upper surface 112.
  • one end of the via 117-2 on the upper surface 112 side is electrically connected to the device side terminal 115 and also electrically connected to the test circuit 130-1 via the pattern wiring 116.
  • one end of the via 117-1 on the lower surface 113 side is electrically connected to the signal supply terminal 120 via the pattern wiring 116 formed on the lower surface 113.
  • One end of the via 117-2 on the lower surface 113 side is electrically connected to the power supply terminal 121 through the pattern wiring 116. Therefore, the signal supply terminal 120 and the power supply terminal 121 are electrically connected to the test circuit 130, respectively.
  • the signal input terminal 320 and the power input terminal 321 are electrically connected to the CMOS circuit 330-1 via the pattern wiring 316, respectively.
  • the unit cell 111-1 When testing the CMOS circuits 330-1 provided on the plurality of semiconductor chips 310-1 by the test system 400, the unit cell 111-1 is close to the semiconductor chip 310-1. At this time, the signal supply terminal 120 and the signal input terminal 320 are electrically connected, and the power supply terminal 121 and the power input terminal 321 are electrically connected. After these terminals are connected, the test circuit 130 sends a predetermined test signal to the CMOS circuit 330-1 via the signal input terminal 320 and supplies a predetermined power via the power input terminal 321. Supply.
  • the predetermined power may be a power supply voltage for driving the CMOS circuit 330-1, for example.
  • the signal supply terminal 120 and the power supply terminal 121 of the unit cell 111-1 are electrically connected to the signal input terminal 320 and the power supply input terminal 321 of the semiconductor chip 310-1 through conductive members such as anisotropic conductive sheets, respectively. May be connected.
  • each terminal of the unit cell 111-1 may be electrically connected to a corresponding terminal of the semiconductor chip 310-1 by electromagnetic induction.
  • the unit cell 111-1 may be connected to the semiconductor chip 310-1 via a transmission path for transmitting an optical signal.
  • FIG. 3 is a schematic diagram showing an example of the circuit configuration of the CMOS circuit 330.
  • the CMOS circuit 330 includes power supply lines 331 and 332 and a plurality of transistor circuit portions 335 (335-1, 335-2,...) Electrically connected to the power supply lines 331 and 332. And have.
  • CMOS circuit 330 is not limited to the form of this example, and may have at least one transistor circuit portion 335.
  • the transistor circuit unit 335-1 will be described below and the other transistor circuit units 335 (335-2,%) Description of is omitted.
  • the power supply line 331 is electrically connected to a power supply unit 542 and a power supply current measurement unit 550 described later of the test circuit 130 via the power input terminal 321 and the power supply terminal 121.
  • the power line 332 is grounded.
  • the transistor circuit unit 335 includes a p-type field effect transistor 336 and an n-type field effect transistor 337.
  • the drain terminal of the p-type field effect transistor 336 is electrically connected to the power supply line 331. Further, the source terminal of the n-type field effect transistor 337 is electrically connected to the power supply line 332.
  • the source terminal of the p-type field effect transistor 336 and the drain terminal of the n-type field effect transistor 337 are electrically connected to each other and are connected to another transistor circuit portion 335 (in this example, the transistor circuit portion 335-2). Connect electrically. Further, the gate terminal of the p-type field effect transistor 336 and the gate terminal of the n-type field effect transistor 337 are electrically connected to each other, and the test circuit 130 will be described later via the signal input terminal 320 and the signal supply terminal 120.
  • the driver 532 is electrically connected.
  • a power supply voltage (V DD ) is applied to the power supply line 331 from the control device 10 via the power supply unit 542 of the test circuit 130.
  • a voltage (V SS ) having a level different from that of the power supply voltage (V DD ) supplied to the power supply line 331 is applied to the power supply line 332.
  • V SS the magnitude of the voltage (V SS ) is substantially equal to 0V.
  • test signal is supplied from the driver 532 of the test circuit 130 to the gate terminals of the p-type field effect transistor 336 and the n-type field effect transistor 337.
  • the test signal may be a signal that switches from one of the different voltage levels of high and low to the other at a predetermined timing.
  • the p-type field effect transistor 336 and the n-type field effect transistor 337 are turned on or off, respectively. As a result, a signal having a voltage level corresponding to the test signal is supplied to the subsequent transistor circuit unit 335.
  • FIG. 4 is a block diagram showing a functional configuration example of the test circuit 130.
  • the test circuit 130 includes a pattern generation unit 522, a waveform shaping unit 530, a driver 532, a characteristic measurement unit 540, and a power supply unit 542.
  • the test circuit 130 may have the configuration shown in FIG. 4 for each input / output pin of the semiconductor chip 310 to be connected. These structures may be formed on the test substrate 110 by a semiconductor process such as exposure.
  • the pattern generator 522 generates a logic pattern of the test signal.
  • the pattern generation unit 522 of this example may store a logic pattern given from the control device 10 in an internal memory before the test is started. Then, the pattern generation unit 522 may output a logical pattern stored in an internal memory when the test is started. The pattern generator 522 may generate the logical pattern based on an algorithm given in advance.
  • the waveform shaping unit 530 shapes the waveform of the test signal based on the logic pattern given from the pattern generation unit 522 and the timing signal given from the control device 10. For example, the waveform shaping unit 530 may shape the waveform of the test signal by outputting a voltage corresponding to each logic value of the logic pattern for each predetermined bit period based on the timing of the timing signal.
  • the driver 532 outputs a test signal corresponding to the waveform given from the waveform shaping unit 530 at a predetermined timing.
  • the test signal output from the driver 532 is supplied to the CMOS circuit 330 of the corresponding semiconductor chip 310 via the signal supply terminal 120, the signal input terminal 320, and the like.
  • the test signal is applied to the gate terminals of the p-type field effect transistor 336 and the n-type field effect transistor 337 in the CMOS circuit 330.
  • the characteristic measurement unit 540 measures the voltage or current waveform output by the driver 532.
  • the characteristic measurement unit 540 may function as a determination unit that determines the quality of the semiconductor chip 310 based on whether the waveform of the current or voltage supplied from the driver 532 to the semiconductor chip 310 satisfies a predetermined specification. .
  • the power supply unit 542 supplies power for driving the semiconductor chip 310.
  • the power supply unit 542 uses the power supply voltage (V DD ) corresponding to the power supplied from the control device 10 as the power supply power for driving the CMOS circuit 330 of the semiconductor chip 310, and the power supply line 331 of the CMOS circuit 330. May be supplied.
  • the power supply unit 542 may supply drive power to all components including the CMOS circuit 330 of the test circuit 130.
  • the power supply current measuring unit 550 is connected to the power supply line 331 and the power supply line in a static state after the p-type field effect transistor 336 and the n-type field effect transistor 337 of the CMOS circuit 330 are switched to a predetermined operation mode according to the test signal. A current flowing between 332, that is, a quiescent current (IDDQ) is detected. Then, the power source current measuring unit 550 sends data corresponding to the detected current value to the control device 10.
  • IDDQ quiescent current
  • test circuit 130 Since the test circuit 130 has such a configuration, a test system with a reduced scale of the control device 10 can be realized.
  • a general-purpose personal computer or the like can be used as the control device 10.
  • FIG. 5 is a block diagram illustrating a functional configuration example of the power supply current measuring unit 550.
  • the power supply current measurement unit 550 includes a current detection unit 551, a transmission data generation unit 552, and a data transmission unit 553.
  • the current detection unit 551 is connected to a power supply line that electrically connects the power supply unit 542 and the CMOS circuit 330 of the corresponding semiconductor chip 310.
  • the current detection unit 551 detects the quiescent current from 350 of the CMOS circuit 330. Then, the current detection unit 551 sends a signal having a value corresponding to the detected current value of the quiescent current to the transmission data generation unit 552.
  • the current detection unit 551 may send a current obtained by amplifying or attenuating the detected current value of the quiescent current to a transmission data generation unit 552.
  • the transmission data generation unit 552 generates digital data corresponding to the value of the quiescent current detected by the current detection unit 551 and sends the digital data to the data transmission unit 553. For example, when the value of the quiescent current sent from the current detection unit 551 is larger than a predetermined level, the transmission data generation unit 552 generates digital data corresponding to a high logic value and generates the quiescent current. If the value of is less than a predetermined level, digital data corresponding to a low logic value may be generated. Instead of this, the transmission data generation unit 552 converts the value of the quiescent current sent from the current detection unit 551 into multivalued digital data corresponding to the magnitude and sends it to the data transmission unit 553. Also good.
  • the data transmission unit 553 transmits the digital data generated by the transmission data generation unit 552 to the outside of the test wafer unit 100.
  • the data transmission unit 553 may transmit the digital data sent from the transmission data generation unit 552 to the control device 10.
  • the data transmission unit 553 may be provided between the test wafer unit 100 and the control device 10 separately from the test wafer unit 100.
  • the power supply current (IDDQ) at rest in the CMOS circuit 330 of each semiconductor chip 310 can be detected by the power supply current measuring unit 550 provided in the corresponding test circuit 130. Then, since the detected value is converted into digital data by the power supply current measuring unit 550 and transmitted to the control device 10, a minute power supply current can be obtained without being affected by the line noise as compared with the case of detection by the control device 10. Can be detected.
  • FIG. 6 is a schematic diagram showing a configuration example of a test system 401 according to another embodiment of the present invention.
  • the test system 401 of the present embodiment is a system for testing a semiconductor wafer 300 to be tested in the same manner as the test system 400, and includes a control device 10 and a test wafer unit 101.
  • the same referential mark is attached
  • the test wafer unit 101 includes a test substrate 140 and a timing generation unit 150.
  • the test substrate 140 may be a semiconductor substrate having a shape corresponding to the semiconductor wafer 300, similar to the test substrate 110 included in the test wafer unit 100, and is disposed to face the semiconductor wafer 300.
  • the timing generator 150 changes the edge timing at which the logical value between the test signals generated by the respective test circuits 130 in the test substrate 140 changes.
  • the timing generation unit 150 delays the edge timing by a predetermined amount so that the edge timing of the timing signal given from the control device 10 to the waveform shaping unit 530 of each test circuit 130 is different for each test circuit 130. .
  • the test system 401 includes such a timing generator 150, for example, when testing the CMOS circuit 330 of the corresponding semiconductor chip 310 with each test circuit 130, the following effects can be obtained. That is, at the timing when the p-type field effect transistor 336 or the n-type field effect transistor 337 of the transistor circuit portion 335 is switched in accordance with a test signal given from the test circuit 130 to the CMOS circuit 330, the power supply lines 331 and 332 are instantaneously connected. A relatively large current flows.
  • the test system 401 can change the edge timing at which the logical value between the test signals generated by the respective test circuits 130 is changed by the timing generation unit 150 described above. It is not necessary to provide a power supply with a large current capacity.
  • FIG. 7 is a diagram showing an example of a cross section of the unit cell 111-1 of the test substrate 140 and the semiconductor chip 310-1 of the semiconductor wafer 300.
  • the configuration of the test substrate 140 will be described by taking the unit cell 111-1 of the test substrate 140 and the semiconductor chip 310-1 of the semiconductor wafer 300 as examples. Since the unit cells 111 other than the unit cell 111-1 have the same configuration, the description thereof is omitted.
  • the unit cell 111-1 of the test substrate 140 further includes a capacitor 500 and an insulator layer 510 in addition to the configuration of each of the unit cells 111 of the test substrate 110.
  • the capacitor 500 is provided on the test substrate 140 in correspondence with the power supply terminal 121 provided in each unit cell 111-1.
  • the capacitor 500 may be provided on the back surface of the test substrate 140 where the test circuit 130 is formed, that is, on the lower surface 113 side of the unit cell 111-1.
  • the capacitor 500 is formed by a semiconductor process. More specifically, the capacitor 500 includes the first electrode layer 501, the dielectric layer 502, and the second electrode layer 503 in the recess formed by etching on the lower surface 113 of the unit cell 111-1, and the test substrate 140. It may be formed by sequentially laminating in a direction perpendicular to the lower surface 113 of the substrate.
  • the first electrode layer 501 is formed of a conductive member such as a copper alloy, for example, and is electrically connected to the reference potential in the test substrate 140.
  • the first electrode layer 501 may be electrically connected to the ground wiring in the test substrate 140.
  • the second electrode layer 503 is formed of the same conductive member as the first electrode layer 501 and is electrically connected to the transmission line connecting the test circuit 130 and the power supply terminal 121. In this example, the second electrode layer 503 may be electrically connected to the power supply unit 542 of the test circuit 130.
  • the dielectric layer 502 is formed of, for example, an insulating resin, ceramic, mica, or the like, and insulates the first electrode layer 501 and the second electrode layer 503 from each other.
  • the insulator layer 510 is provided so as to cover the surface of the capacitor 500 on the side facing the semiconductor chip 310-1, that is, the surface of the second electrode layer 503.
  • the insulator layer 510 may be formed by a semiconductor process. More specifically, the insulator layer 510 may be formed by laminating an insulating material on the surface of the second electrode layer 503 exposed in the direction perpendicular to the lower surface 113 of the test substrate 140.
  • the insulator layer 510 is provided so that the signal supply terminal 120 and the power supply terminal 121 are exposed to the semiconductor chip 310-1 side in the unit cell 111-1. That is, the insulator layer 510 is formed on the lower surface 113 of the unit cell 111-1 so as not to protrude from the signal supply terminal 120 and the power supply terminal 121 toward the semiconductor chip 310-1.
  • the second electrode layer 503 of the capacitor 500 comes into contact with the circuit on the semiconductor chip 310. Short circuit can be prevented.
  • one electrode is connected to the transmission line for applying the power supply voltage (V DD ) from the test circuit 130 to the CMOS circuit 330, and the other electrode is the reference.
  • a capacitor 500 is connected to the potential.
  • the capacitor 500 is arranged on the surface of the unit cell 111-1 opposite to the test circuit 130, so that the area of the electrode layer in the capacitor 500 is increased to, for example, the same level as the test circuit 130. be able to. Therefore, since the capacitor 500 having a large capacity can be provided in the unit cell 111-1, the broadband high-frequency noise can be filtered.
  • the capacitor 500 is provided at a position closer to the CMOS circuit 330 than the control device 10 and the test circuit 130, fluctuations in current consumption in the CMOS circuit 330 can be compensated.

Abstract

L'invention porte sur une unité de tranche pour test (100) qui est électriquement connectée à une pluralité de puces de semi-conducteur (310) formées sur une tranche de semi-conducteur (300). L'unité de tranche pour test comprend un substrat de test (110) agencé en regard d'une tranche de semi-conducteur, une pluralité de bornes d'alimentation électrique, au moins chacune d'elles étant prévue pour les puces de semi-conducteur individuelles dans le substrat de test et électriquement connectée à la borne d'entrée de source d'alimentation de chaque puce de semi-conducteur correspondante, et une pluralité de sections de détection de courant, au moins chacune d'elles étant prévue pour les puces de semi-conducteur individuelles dans le substrat de test afin de détecter le courant de repos fourni aux puces de semi-conducteur par les bornes d'alimentation électrique individuelles. Un système de test ayant une dimension réduite d'une unité de commande (10) peut ainsi être réalisé.
PCT/JP2008/060079 2008-05-30 2008-05-30 Unité de tranche pour test et système de test WO2009144828A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/JP2008/060079 WO2009144828A1 (fr) 2008-05-30 2008-05-30 Unité de tranche pour test et système de test
PCT/JP2009/002370 WO2009144948A1 (fr) 2008-05-30 2009-05-28 Unité de test et système de test
JP2010514379A JPWO2009144948A1 (ja) 2008-05-30 2009-05-28 試験用ユニットおよび試験システム
TW098118029A TWI393200B (zh) 2008-05-30 2009-06-01 測試用單元以及測試系統

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PCT/JP2008/060079 WO2009144828A1 (fr) 2008-05-30 2008-05-30 Unité de tranche pour test et système de test

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WO2009144828A1 true WO2009144828A1 (fr) 2009-12-03

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JP2007240376A (ja) * 2006-03-09 2007-09-20 Matsushita Electric Ind Co Ltd 半導体集積回路の静止電源電流検査方法および装置

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EP2286843A2 (fr) 2000-06-02 2011-02-23 Bracco Suisse SA Composés pour le ciblage de cellules endothéliales
EP2341356A1 (fr) * 2009-12-18 2011-07-06 Tektronix, Inc. Procédé et dispositif de mesure de signaux entre puces
US8384411B2 (en) 2009-12-18 2013-02-26 Tektronix, Inc. Method and device for measuring inter-chip signals

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TW200952107A (en) 2009-12-16
TWI393200B (zh) 2013-04-11
JPWO2009144948A1 (ja) 2011-10-06

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