TW200952107A - Testing unit and test system - Google Patents

Abstract

A testing unit conductively connected to a semiconductor chip is provided. The testing unit includes a testing substrate, arranged opposite to the semiconductor chip; a power supply terminal, conductively connected with a power-input terminal of the semiconductor chip on the testing substrate; and a current detection portion, which detects a static current supplied to the semiconductor chip through the power supply terminal on the testing substrate.

Description

-ii.doc 200952107 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a test system for a test unit having a test substrate, and the above-mentioned test uses a self-test unit The current detecting unit supplies the quiescent current to the formed body, and the quiescent current of the Γ Ο Γ Γ : : : : : : : : : : : 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体A device that is half-and-a-half-tested (for example, referring to a patent and a plurality of semiconductor wafers on a semiconductor wafer, collectively into a double-hearted material (10)e (four)), and a new semiconductor is connected [previous technical literature] [Patent Document 1] Japanese Patent Laid-Open Publication No. 2002-222839. In the method, in order to cut all the sharpness of the semiconductor wafer, the connection position of the probe card with respect to the semiconductor wafer is repeated two days. Test 'and thus become the main reason for the test time becoming longer and 'in the previous test device including the above device, the circuit for generating the test case, and for the test object Response of the semiconductor wafer = a circuit or the like for detecting a tiger or the like is provided on the side of the control device which is cut by the probe by a relatively long transmission line such as a one-turn gate. *This is a complementary MOS for semiconductors (c. Delete (10) on ^ 200952107 JUVJipIl.doc

The Metal Oxide Semiconductor (CMOS) circuit is used to measure the power supply current. The detection error caused by the current current = the noise of the line is less. The iron is, for example, for the semiconductor __ The method of installing the + path of the probe on the probe card is more difficult from the angle of the probe card. The cost of the long clothes [invention] The purpose of the core is to 巍-shoot the rainbow, Μ Μ 、 、 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备 具备In the form of 1 , mentioning #- using early 兀 ' _ trial unit and semi-conducting ' includes: test substrate, connected with the semi-conductor s electric 11 , sub-terminal 'on the test substrate = set; power supply connection In addition to the current and supply terminals, the source and the supply terminal are supplied to the semiconductor crystal via the electric power, and the 坌0 h of the present invention is used to detect the enthalpy. Test system, , heart: test unit, unit, above test The unit clamping test wafer is disposed opposite to each other; the power supply + frequency substrate, and the semiconductor wafer body power supply wheel terminal are on the test substrate, and the semi-conductive test substrate is connected to the green via; The inspection unit detects the quiescent current of 4 200952107 id.doc supplied to the semiconductor wafer. In the third aspect of the semi-conductor μ B, a test system is provided, and a plurality of semiconductor wafers of the test system 2:? are tested, and the measurement is performed from the control device, and the test unit is controlled, and configured; ==_The substrate 'is opposite to the semiconductor wafer to the f-conductor wafer, at least rff, on the service substrate for each half of the power supply wheel, and the corresponding semiconductor wafer is cut and sub-electricity Connections; and at least one of the shaft-mounted semiconductor wafers, = = a summary of the static ΐ C supplied to the semiconductor wafer via the respective power supply terminals, and does not enumerate all the sub-combinations of the necessary feature groups of the invention ( Sub-combination) The above-mentioned features and advantages of the present invention can be more clearly recorded. The following is a detailed description of the sub-combination and the related embodiments. [Embodiment] The present invention will be described by way of embodiments of the invention, but The invention of the scope of the patent application. And the 'embodiment.' The combination of '4 inches' is not necessarily necessary for the solution of the invention. It constitutes this:; ==__^^ The mouth-cutting system 400 is a pair of

200952107 JM jpU.d〇C The semiconductor wafer stage of the test system is tested by the 'System 10' and the 晶圆 试 test wafer unit. The clothing (4) ir example, as shown by κ 1, is used in the test (10) 4 (8) as: two V. The conductor wafer is 3°. It may be a wafer-shaped semiconductor substrate formed with a plurality of semiconductor wafers 310 (31 (M, .) including CM 〇 S circuits / 1, 330-2, ...). The plurality of semiconductor crystals form a T. For semiconductor wafers, use a semiconductor processing board for exposure, etc., and test the substrate (10). Test the semi-conductor plate of the crystal 11〇 and the half-m pattern of the corresponding shape of the wafer on the base wafer. The test substrate is disposed opposite to the fifth Japanese Yen 300. When the conductor wafer _ is a disk-shaped semiconductor substrate, the same i, i i110 may have a semiconductor crystal than the semiconductor wafer 3 The circular diameter of the large circle, the 1-2, etc. = semiconductor substrate. The test substrate is not limited thereto, and may be any shape that faces at least a portion of the upper surface of the semiconductor wafer 300. - ΐ ί, 基 * 110 * has a plurality of unit cells (ll) disposed at positions corresponding to each of a plurality of half-meters m"0 on the semiconductor wafer 300 (chuan) ], 1 abortion < ~1 nl_2, ···). Moreover, in a plurality of unit elements ΐλΐη two, A test circuit 130 (130-1, 130-2 '...) for generating a semiconductor crystal g, /, a test signal for the corresponding one is provided. The unit cell of the substrate 110 for the J type and the semiconductor wafer 6 u. The semiconductor wafer 310-1 of doc 200952107 is disposed opposite to each other, and a test circuit is provided therein. The plurality of semiconductor vertical test substrates m are controlled by a semiconductor process such as exposure, and the control device 10 controls the test system 4 (8). For the semi-conductor test program, for example, the control device .10 can be used for each of the 110 readings of the lightning technique 〖m+ 'the 5 type substrate - various control; = r, r = Ο ί), Each of the test circuits 130 to be supplied to each of the semiconductor wafers can generate a test letter corresponding to the test pattern in response to the control signal from the batch: the following::: to the corresponding semiconductor wafer 31〇 Moreover, each road, 〇';;: D (four) cow ¥ body day 31Q in the CM0 kinds of operating state of the stationary power supply current (IDDQ), and the corresponding digital data is sent to the control device 10. At this time, suppress |, set '==:;: connect = the number of data; judgment; In the following paragraph, the test system of the present embodiment will be provided in the latter section. The test system of the present embodiment is provided with a plurality of test circuits 130, thereby providing a wide range of test circuits 130. All the semiconductor wafers on the wafer _ are simultaneously subjected to the j ° type and the 'each' test circuit 130 is formed by the test substrate ι10, so that the test circuit is mounted on the printed circuit board. In contrast, it is easier to form multiple testers on the test substrate n〇200952107

Ljyj&gt;pn.d〇C circuit. 2 is a view showing a unit cell η of the test substrate 11A and a semiconductor wafer 31 of the semiconductor wafer 300 (an example of a cross section of the crucible. In FIG. 2, the test substrate is picked out). The unit cell is represented by the semiconductor wafer 310-1 on the semiconductor wafer 300 facing the unit cell ln_. In addition to the unit cell (1) shown in FIG. 2 The unit cell (1) has the same configuration, and the description thereof is omitted. Moreover, the semiconductor wafer 31 (3 Κ) has the same configuration, and the description of the chip-test circuit 13〇-1 and the device side is omitted. The terminals 114 and 115 are provided on the back surface of the unit cell 111-1 facing the surface of the semiconductor wafer 31 (M (hereinafter, referred to as "the upper surface 112 of the unit cell mi").

No. Supply terminal 120 and power supply terminal? The history of the unit cell UH is placed on the surface facing the semiconductor wafer 310-1 (hereinafter referred to as "the lower surface 113 of the unit cell 111-1"). Here, the signal supply terminal 120 and the power supply terminal 121 may be provided at positions of the signal input terminal 32 and the power supply input terminal 3 provided on the upper surface of the semiconductor wafer 31 (~). The end of the upper surface 112 side of the plurality of through holes (5) (7) (1) of the through holes (1) is electrically connected to the device side terminal 114, and is connected to the device side terminal 114 via the upper surface 112 to the lower surface 113. The pattern wiring 116 on the upper surface 112 is electrically connected to the test circuit. Moreover, the one end of the upper surface 112 side of the through hole 117_2 is electrically connected to the terminal device side terminal H5, and is connected to the test via the pattern wiring m.

B 200952107 , — a r ii.doc Test circuit 130-1 is also electrically connected. Further, the pattern wiring m2:: on the lower surface of the via hole 117-1 is formed on the lower side. Further, the lower surface of the through hole 117-2, the '3 彳 〜 、, the 5 鳊 12 ( ) electrically connected 116 and the end of the power supply terminal ( 2 ) ^ 3 = via the pattern wiring 120 and the power supply terminal ^. Therefore, the signal is supplied to the terminal. On the other hand, the semiconductor chip and the circuit 13Q are electrically connected and the power input terminal 321 is respectively passed through the = input terminal 320.

Circuit 330-1 is electrically connected. S wood wiring 316 and CMOS when the CM0S circuit on the test system 4 〇〇 &amp; 310-1 "is again placed when the plurality of semiconductor wafers are close to the semiconductor wafer 3HM, the cell 12 〇 and the signal input terminal 32 After the (4) signal supply terminal and the power supply input terminal 32lt and the power supply terminal 121, the test circuit 130 is connected via the respective terminals.

Lone 1 sends the specified test ^^^ to the _ circuit to supply the specified power. Here, the power supply voltage 1 for driving the CM〇S circuit by the source input terminal 32i may be, for example, another unit cell 11M supply terminal (2) or a power supply and a semiconductor, respectively. The conductive member terminals 32 of the wafer or the like are electrically connected. And / / input the vertical and the 32 〇 and the power wheel of each terminal can be connected by Lei Cheng A on the 24, unit cell 111-1

Each terminal is electrically connected. And the corresponding connection with the semiconductor wafer 31〇-1, and in place of the above connection, the unit cell 11M 9 200952107 :wp]i.doc can also be connected by the transmission path I of the transmitting optical signal. Furthermore, in place of the above connection, the 3KM of the single-body wafer is coupled to the semiconductor wafer! Electrical connection. It is also possible to pass the capacitance. Fig. 3 is a diagram showing the CMOS circuit 33. As shown in Fig. 3, the outline of the CM〇s ”: path configuration and the eve of the power line 331, 332, 332 335 (335-1 . 335-2 &gt; ·..) In addition, the CMOS circuit 3 has at least one transistor circuit portion = in the form of this example, as long as each transistor circuit portion 335 has | ^ α and, in this example, a plurality of pairs of electricity The crystal circuit unit 335 is configured to be ''therefore, the description of the following spare parts 33^〇35_2, . . .) is omitted, and the other transistor cell 121 and the test circuit and the power supply continuation current measuring unit 550 are omitted. Electrical connection: "": supply portion 542 and power supply transistor circuit = field effect transistor 337. p-type field effect transistor ^ electric body 336 and n-type sub-electrode are electrically connected to power line 331. The drain terminal (the terminal) and the power source line 332 are electrically connected to the source of the transistor 337. In addition, the P-type field effect transistor 336 has no external terminals of the crystal 337. The field effect transistor 336 is electrically connected to the gate + θ (gaie) terminal of the field effect transistor 337 and the η open pole 疋And through the xi.doc 200952107 m into the terminal, and the driver 532 to be described later is electrically connected *. - and the test circuit is on the power line 3, Θ, ... the signal input terminal 130 is on the power line 331 The power supply unit 542 of the control unit is mounted with the power supply 2, and the power supply is applied to the power supply unit 332, and the power supply (Vss) 31 is applied to the electric field and the electric power (Vss) 31. (Vdd) The source line 332 is grounded, so the voltage (v, in the case, due to electricity

When the CMOS circuit 330 is to be =-, , the size of t is approximately equal to 〇v. The driver 532 of the 130 can be used to test the p-type field effect self-test circuit at a predetermined timing, and the m-value is switched to another signal. The different voltages of -(°w) are given to the above-mentioned measurement and subtraction signals, so that the p-type field effect transistors are switched to be turned on ((10)) or off) respectively. The transistor circuit portion of the subsequent stage supplies a signal of a voltage level corresponding to the test signal. 1. Fig. 4A is a block diagram showing an example of the functional configuration of the test circuit 13A. Measurement . The circuit 130 includes a pattern generating unit 522, a waveform forming unit 53A, a driver=2, a 4-inch measuring unit 54A, and a power supply unit 542. Further, the test circuit 130 can have the configuration shown in Fig. 4 for each pin of the input/output pin ^Pin) of the connected semiconductor wafer. These configurations can be formed on the test substrate n by a semiconductor process such as exposure. The potential pattern generation unit 522 generates a logic pattern of the test signal. The water generation unit 522 of this example can store the pattern of the logic 200952107 il^v^pn.doc provided from the control unit 1 in the internal memory before the start of the test. Further, the pattern generating portion 522 can output the logical pattern stored in the internal memory at the same time as the start of the test. Further, the pattern generating portion S22 may generate the logic pattern based on an algorithm provided in advance. The waveform shaping unit 530 shapes the waveform of the test signal based on the logic pattern supplied from the pattern generation unit 522 and the timing signal supplied from the control unit i10. For example, the waveform shaping section 530 outputs a voltage corresponding to each logical value of the logic pattern every predetermined bit period in accordance with the timing of the timing signal, whereby the waveform of the test signal can be shaped. The driver 532 outputs a test signal corresponding to the waveform supplied from the waveform shaping portion 53A at a predetermined timing. The test signal that is rotated from the driver 532 is supplied to the CMOS circuit 33A of the corresponding semiconductor wafer 310 via the signal supply terminal 120 and the signal input terminal. Then, the test signal is supplied to the p-type field effect transistor 336 in the CMOS circuit 330 and the gate terminal of the n-type field effect transistor 337. The characteristic measuring unit 540 measures the shape of the voltage or current output from the driver 532. For example, the characteristic measuring unit 54 can function as a determining unit that determines whether or not the conductor wafer 310 is good or not based on whether or not the waveform of the current or voltage supplied from the driver 532 to the semiconductor wafer 310 satisfies a predetermined specification. The power supply unit 542 supplies power for driving the semiconductor wafer 310. In this example, the power supply unit 542 can supply the power supply voltage (Vdd) corresponding to the power supplied from the control device to the power supply power of the CMOS circuit 33A of the semiconductor wafer 310 to the cm〇s. Circuit ii.doc 200952107 i. ^ Power line 33 of y 330 In addition, the power supply unit 542 can supply drive power to all components including the CMOS circuit 330 of the test circuit 13A.

The power supply current measuring unit 550 flows through the stationary state after switching the p-type field effect transistor 336 and the n-type field effect transistor 337 of the CMOS circuit 330 to a predetermined operation mode (m〇de) according to the above test signal. The power line 331 and the power line 332's current, that is, the quiescent current (IDDQ) are detected. Further, the power source current measuring unit 55 transmits the data corresponding to the current value detected by the 至 to the control device 1A. Test circuit! By having the above configuration, the test system in which the control device 10 is lowered can be realized. For example, a general-purpose personal computer or the like can be used as the control device. Fig. 5 is a view showing an example of the functional configuration of the power source current measuring unit 55A. The power supply current measuring unit 550 includes a current detecting unit 551, a transmission material generating unit 552, and a data transmitting unit 553. Days, / leaves, secrets.. ...% external 丨 邯 邯 42 42 与 与 与 与 与 与 与 与 与 与 与 与 与 与 臬 臬 臬 臬 臬 臬 臬 臬 臬 臬 臬 臬 臬 臬 臬 臬 臬 臬The current detecting unit 551 detects the above-described stationary: from the CMOS circuit 33A. The current detecting unit 551 transmits a signal corresponding to the value of the detected current value (4) of the % stream to the transmission: # = =2. Further, the current detecting unit 551 may transmit the detected static value and the flow value to the information generating unit 552. The transmitted data generating unit 552 detects the digital data corresponding to the current detecting unit 200952107 j irwpii.doc: dead = fine value, and the digital data is 53 53. For example, when the self-current detecting unit 551t has the value of the quiescent current greater than a predetermined level, the transmitting data 552 can generate digital data corresponding to a high logical value, and when the value of the stationary (four) is smaller than a predetermined bit. On time, the transmission data generation unit says that it is equivalent to generating a low logic value_bit data. Instead of this, the transmission data generating unit 552 may convert the value of the stationary current transmitted from the current detecting unit 551 into a multi-valued number returning to its size, and send it to the data transmitting unit 553. &quot; The one-bean shipment unit 553 develops the digital material generated by the transmission data generating unit 552 to the outside of the test wafer unit 1〇〇. For example, the transmission unit 553 can electrically transmit the digital data transmitted from the transmission data generating unit 552 to the control device 10. Further, the data transmitting unit 55 tries to separately set the round unit between the test crystals and the control device 10 separately. 〃, 1 uses the corresponding test circuit 13 fixed portion 550 to detect the static power supply in the two S circuit 330 of each semiconductor wafer training... 3 electrical value after the power supply current portion 55G 'the detection device 10, therefore, And the control is performed to control the influence of the non-channel noise to detect the weak power supply current. The test system of the test system of the present embodiment is a semiconductor crystal that is the same as the object of the present embodiment. Circle 300 into 200952107 j&gt; i ^ ^ jpif.doc The system for testing is provided with the control device 10 and the test wafer unit 101. In the test system 401, the same components as those of the above-described test system 4 are denoted by the same reference numerals, and their description will be omitted. The test wafer unit 101 includes a test substrate 14A and a timing generation unit 50. Similar to the test substrate 110 included in the test wafer unit, the test substrate 140 may be a semiconductor substrate having a shape corresponding to the semiconductor wafer 300 and opposed to the semiconductor wafer 3A. Configuration.

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The V timing generation unit 150 causes the edge timings at which the logical values between the test signals generated by the respective test circuits 130 in the test substrate 14 are changed to be different. For example, the timing generating portion 15G makes the edge % of the waveform shaping portion s3 of the respective test circuits m different for each test circuit 130 in order to make the self-control device | The sequence is delayed as specified. The test system 401 includes the timing generation unit 15 described above, for example, in each of the m circuits 13Q: (10) the circuit 33〇 can obtain the following effect == field effect transistor (four) two = day (10) S circuit for switching (4) The test signal is a large current. In the middle of the 4 source lines 331, 332, the instantaneous flow is relatively ambiguous. In the case of the day, the power supply is provided between the power lines 331, 332, and the vomiting is given to the side 542. The voltage of the corresponding power supply for the power supply of the θ 生 生 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥Therefore, when the timing generating portion 15A is not provided, the flow of the voltage of the 200952107 flows through the CMOS circuits mo of the plurality of semiconductor wafers 310 at the same timing. Therefore, it is necessary to set a power source with a large current capacity. On the other hand, the 'test system 4' can change the edge timing of the logical value between the test signals generated by the respective measurement circuits 30 by the timing generation unit 5〇, and thus the power supply unit is different. The 542 side does not have a power supply with a large current capacity. Fig. 7 is a view showing an example of a cross section of the semiconductor cell 31 of the test substrate 14 and the semiconductor wafer 31 of the semiconductor crystal 8] 300. Hereinafter, the unit cell m-ι of the test substrate 14A is used. The semiconductor wafer 31G.1 of the semiconductor wafer is used as an example to describe the configuration of the test substrate. The unit cell 111 other than the unit cell 111_1 has the same configuration, and the description thereof is omitted. The cell is 111-121. It is also set. For example, the unit cell 111 of the test substrate is more than 30%, and the test substrate HO❸ unit cell nl-1 is more electric. The valley is 500 and the insulator layer 510. The capacitor 5〇〇 is disposed on the test substrate 14A and is formed with the test circuit 130 Ml 7T. Vial 1 Ί ί. The mouth is connected to the 4, r _^ The power supply terminal capacitor 500 may be on the back surface of the surface of the test substrate 140 130, that is, disposed on

The layer 502 and the second electrode layer 5〇3 are sequentially stacked in the direction perpendicular to the if.doc 200952107 layer. The first electrode layer 501 is made of, for example, steel and electrically connected to the reference potential of the test substrate U0. The electrode layer 501 can be electrically connected to the test substrate 140. The i-th electrode layer is formed by 5 pieces, and is electrically connected to the transmission line of the 3Gm. In this example, the first::=121 can be electrically connected to the test circuit 130, and the 502 sand is formed of an insulating resin, a ceramic ((10) (Chen 3) temple, and the first The electrode layer is insulated from the second electrode. The potential layer 303 is disposed so as to cover the surface of the capacitor % 3KM opposite to one side, that is, the zero seedling/dry, etc. Form 2 to face; ^ 2 electrode layer formed in the direction perpendicular to the lower f-plane 113 of the test butterfly to form an insulating material. In this example, the insulator layer 5] The unit cell mi is arranged such that the cymbal supply terminal 12 sings the squeaky material ι2 ΐ exposed to the semiconductor, that is, the 'insulator layer 510 is not more than the signal supply terminal 120 in the unit cell m-ι The power supply terminal is formed when the unit cell is called and the thickness of the solar cell is half. Therefore, when the connection is sexually connected, the electrode 2 and the semiconductor layer 503 and the semiconductor 200952107 can be prevented from being electrically approached and each terminal is electrically excited. .doc 曰曰片=〇The circuit on the 相 is short-circuited (s. 斤迷, test base 4〇 unit _ electric grid device 500, the capacitor, 500 and one of them: already have (1) in the test circuit] 30 to CM 〇 s circuit % = pole connected to the transmission line with 4, plus pen The source voltage (VD) c should be circuit 33 other than - and the / soil _ 妾 基准 基准 基准 。 。 。 。 。 。 。 。 。 由此 由此 由此 由此 由此 由此 由此 由此 由此 由此 由此 由此 由此 由此 由此 由此 由此 由此 由此 由此 由此 由此 由此 由此 由此 由此 基准 基准 基准 基准 基准Performing the slope πμΓ and showing 'the capacitor 5 (10) on the opposite side of the unit one lake' can thereby increase the area of the capacitor 0 @ (3) to, for example, the frequency with the test circuit 130. The above-mentioned high-frequency noise is filtered. In the example, compared with the control device 10 and the test circuit 130, the capacitor 5 is provided at the position of the fine circuit 〇〇S circuit 330, so that the CM〇Sf path can be compensated. The variation of the current consumption in the gamma. The present invention is described in the broad state of the present invention, but the technique (4) of the present invention is not limited to the range described in the above embodiments. The above embodiment can be clearly understood from the description of the scope of the patent application, and the improved form is obtained. It can be included in the technical scope of the present invention. For example, the test wafer _ 曰 # Aik 车 神 神 and the test wafer unit 101 疋 are used as the test unit electrically connected to the 脰曰曰 脰曰曰The test unit can also be formed on a substrate that is not wafer-shaped. For example, the test sheet 200952107 jjjif.doc 雍1 semiconductor wafer of one or more test objects 3i° relative dreams of the mail] / shape of the substrate at this time, The unit used can be used; the test wafer unit described in connection with FIG. 7 is manufactured by dividing the wafer unit into a crystal grain shape. Bracts: Two? The unit can be formed to be approximately the size of the semiconductor wafer of the test object. Moreover, it is also possible that the die is connected to the semiconductor wafer 310 of the object;

: The pellets are packaged (packed) by a film (fllm) or the like. Further, the semiconductor wafer 310 may be a grain-like wafer. Although the present invention has been disclosed in the above embodiments, it is not intended to be used in the present invention. Any one of the technical fields of the technical field of the present invention may be modified and retouched without the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a configuration of a test system and a system 4 according to an embodiment of the present invention. Fig. 2A is a view showing an example of a cross section of the unit cell ill of the test substrate 11A and the semiconductor wafer 310-1 of the semiconductor wafer 300. Fig. 3 is a schematic diagram showing an example of a circuit configuration of a C Μ O S circuit 303. FIG. 4 is a block diagram showing an example of the functional configuration of the test circuit 130. FIG. 5 is a view showing an example of the functional configuration of the power source current measuring unit 550. Fig. 6 is a schematic view showing an example of the configuration of a test system 4〇ι 2009 200952107 31595pif.doc according to an embodiment of the present invention. FIG. 7 is a view showing an example of a cross section of the unit cell 1-1 of the test substrate 140 and the semiconductor wafer wo of the conductor wafer 300. [Explanation of main component symbols] - 1〇: Control device, ιοί: Test wafer unit no, 4〇··Test substrate '111-1, 111-2: Unit cell 112. Upper surface 113: Lower surface 114, 115: device side terminal 116: pattern wiring Π 7 ' 117-1 ' 117-2 : through hole 120 : signal supply terminal 121 : power supply terminal 130 , 130-1 , 13 〇 2 : test circuit 150 : timing generation Portion 300: semiconductor wafer 310, 3KM, 31-seven semiconductor wafer 316. Pattern wiring 320. Signal input terminal 321. Power supply wheel terminal 330' 330-1, 330-2: CMOS circuit 331, 332: power supply line 20 200952107 Most 335, 335-1, 335-2: transistor circuit portion 336: p-type field effect transistor 337: n-type field effect transistor 400, 401: test system 522: pattern generation portion 530: waveform shaping portion 532: driver 540 : Characteristic measurement unit 542 : Power supply unit 550 : Power supply current measurement unit 551 : Current detection unit 552 : Transmission data generation unit 553 : Data transmission unit 500 : Capacitor 501 : First electrode layer 502 : Dielectric layer 503 : 2nd Electrode layer 510: absolutely Layers

Claims (1)

200952107 όί^^ρπ.άοο VII. Shenqing patent scope: 】·A test unit, and Fengfeng unit includes: , '版日日片电连接, this 螂蟀 test substrate, and the above semi-power supply The terminal is disposed on the upper, the +, and the body positive plates; the power supply wheel of the wafer is electrically connected to the terminal, and the semi-conductive H current residual portion is supplied to the test supply terminal. : The child applies for the patent scope of the second item = two via the above-mentioned e-mail, and the inspection is carried out. The transmission data generating unit, the soil, and the early detection unit further includes: a poor material transmitting unit corresponding to the value detected by the current detecting unit on the substrate, and a value indicating the current value, which is disposed on the upper portion Send the data generation department to the second, the board, the outside of the board. The position is developed to the above-mentioned just trial list 3. As mentioned in the second item of the patent application scope, the upper part sends the data to generate the Qiufeng out balance. The D type uses the premise, and the above-mentioned static current of the electric fiber is in the t The above-mentioned number corresponding to the inspection by the Ministry of Electrical and Electronic Supervision ^ ^ 在 匈 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = Shen: The test unit described in the fourth item of the patent κ, the aΨ 4 capacitor is placed on the back side of the surface on which the test circuit is formed with %?if.doc 200952107. In the test unit described in item 5 of the mi patent, the surface of the test substrate is oriented in the direction of the substrate, such as a layer, a dielectric layer, and a second electrode layer. = On the test substrate, the county layer is formed by the square handle of the above-mentioned test material. . . And the road η 8·such as the test unit described in the article, the semi-conductor f is a wafer electrically connected to the semiconductor wafer a unit; the test substrate and the semiconductor wafer are opposite to each other on the upper side of the "coffee board for each upper conductor; === joint and the axis semi-conducting trial purely for each of the above-mentioned identification, each &amp; a test unit for detecting the quiescent current supplied to the semiconductor wafer via each of the above-mentioned strips, and the test unit described in the eighth aspect of the patent range, further comprising: a cymbal I ί measuring substrate Each of the above-mentioned semiconductor apostrophes; each of which sets a test timing generating portion having a quaternary (four) logic pattern, so that the edge timing of each of the above-described test ray changes does not generate a test signal 10 - a test The system tests the semiconductor wafer. The test system 200952107 ji^VDpil.doC system includes: test unit, and control device, electrical connection of the semiconductor wafer at the batch; and ground trial == trial unit, test The board is connected to the power supply; the + 乂 semiconductor wafer is disposed opposite to each other; and the wafer reduction terminal terminal test substrate is connected to the above-mentioned semi-lead current detecting unit, and is supplied to the upper layer: On the substrate, a plurality of semi-conductive test systems formed by measuring the current into the butterfly wafer via the above-mentioned electro-green U.1 test system include: semiconductor wafer electrical connection conductor The plurality of devices formed on the wafer control the test unit, wherein the test unit comprises: a plurality of electrodes; Ί, two: the body wafer is disposed opposite to each other; and each of the semiconductor wafers is at least two The power input terminal of the plurality of semiconductor wafers on the substrate is electrically connected; one: _ quiescent current. To the above-mentioned abundance conductor wafer