Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/0175—Coupling arrangements; Interface arrangements
  • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
  • H03K19/018507—Interface arrangements
  • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
  • H03K19/018528—Interface arrangements of complementary type, e.g. CMOS with at least one differential stage
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/01—Modifications for accelerating switching
  • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
  • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
  • H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
  • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
  • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
  • H03K3/356—Bistable circuits
  • H03K3/356104—Bistable circuits using complementary field-effect transistors
  • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit

Definitions

• the present disclosure is generally related to level shifting circuits and methods.
• wireless computing devices such as portable wireless telephones, personal digital assistants (PDAs), and paging devices that are small, lightweight, and easily carried by users.
• portable wireless telephones such as cellular telephones and internet protocol (IP) telephones
• IP internet protocol
• wireless telephones can communicate voice and data packets over wireless networks.
• many such wireless telephones include other types of devices that are incorporated therein.
• a wireless telephone can also include a digital still camera, a digital video camera, a digital recorder, and an audio file player.
• wireless telephones can process executable instructions, including software applications, such as a web browser application, that can be used to access the Internet. As such, these wireless telephones can include significant computing capabilities.
• level shifter circuit designs often require a choice between improving response time to an input transition and improving a range of operation at low voltages. An increase in response time typically decreases the range of operation, while increasing the range of operation typically degrades response time. Thus, level shifters may limit performance of devices during low-power operation.
• a circuit device in a particular embodiment, includes an input to receive an input voltage signal and an output to provide a level shifted voltage signal.
• the circuit device includes a first weak state holding path coupled to the input and a second weak state holding path coupled to the output.
• the circuit device also includes a voltage pull-up logic circuit coupled to the first weak state holding path and to the second weak state holding path.
• the circuit device further includes a control path coupled to the voltage pull-up logic circuit to selectively control activation of the voltage pull-up logic circuit.
• a system in another embodiment, includes a memory array and a first input coupled to the memory array by a first level shifting circuit.
• the system also includes a second input coupled to the memory array by a second level shifting circuit.
• the first level shifting circuit includes an input to receive the first input and an output to provide a first level shifted voltage signal to the memory array.
• the first level shifting circuit also includes a first weak state holding path coupled to the input.
• the first level shifting circuit further includes a second weak state holding path coupled to the output.
• the first level shifting circuit includes a voltage pull-up logic circuit coupled to the first weak state holding path and to the second weak state holding path.
• the first level shifting circuit also includes a control path coupled to the voltage pull-up logic circuit to selectively control activation of the voltage pull-up logic circuit.
• a device in another embodiment, includes means for receiving an input voltage at an input to a level shifting circuit including voltage pull-up logic. The device also includes means for providing an output signal from the level shifting circuit. The device further includes means for selectively activating the voltage pull-up logic circuit of the level shifting circuit.
• a method in another embodiment, includes receiving an input voltage at an input to a level shifting circuit that includes voltage pull-up logic. The method includes providing an output signal from the level shifting circuit. The method also includes selectively activating the voltage pull-up logic circuit of the level shifting circuit.
• One particular advantage provided by the disclosed embodiments is a large voltage shifting range due to the weak state holding paths and a quick response to input signal transitions due to the voltage pull-up logic circuit. Another particular advantage is that operation of the level shifting circuit is relatively process tolerant.
• FIG. 1 is a block diagram of a first illustrative embodiment of a level shifting circuit device
• FIG. 2 is a circuit diagram of a second illustrative embodiment of a level shifting circuit device
• FIG. 3 is a block diagram of a particular illustrative embodiment of a system including a level shifting circuit device
• FIG. 4 is a flow diagram of a particular illustrative embodiment of a method of level shifting using a circuit device, such as the circuit devices illustrated in FIGs. 1-3;
• FIG. 5 is a block diagram of a representative mobile communication device in which embodiments of the circuits and methods described in FIGs. 1-4 may be used.
• a first illustrative embodiment of a level shifting circuit device is depicted and generally designated 100.
• the level shifting circuit device 100 includes an input 102 to receive an input voltage signal.
• An output 104 provides a level shifted voltage signal.
• a first weak state holding path 106 is coupled to the input 102 and to the output 104.
• the first weak state holding path 106 is cross-coupled to a second weak state holding path 108 that is also coupled to the input 102.
• a voltage pull-up logic circuit 110 is coupled to both the first weak state holding path 106 and the second weak state holding path 108.
• a control path 112 is coupled to provide a control signal to the voltage pull-up logic circuit 110.
• the input voltage signal received at the input 102 is within a first voltage range between a high state (VlL) and a low state (VO).
• the first weak state holding path 106 In response to the input voltage signal, the first weak state holding path 106 generates a level shifted voltage signal at the output 104 that is within a second voltage range between a high state (VlH) and a low state (VO).
• the first weak state holding path 106 and the second weak state holding path 108 are configured to enable level shifting of a large range of input voltages, including level shifting at or below 0.6-1.4 V.
• the first weak state holding path 106 and the second weak state holding path 108 may exhibit relatively slow transition times in response to a transition of the input signal received at the input 102.
• the voltage pull-up logic circuit 110 is operative to improve the switching speed at the output 104 by providing current to the first weak state holding path 106 and to the second weak state holding path 108.
• the additional current provided by the voltage pull-up logic circuit 110 to the weak state holding paths 106 and 108 enables faster response to a transition of the input signal.
• the voltage pull-up logic circuit 110 primarily operates to provide level shifting current to at least one of the first weak state holding path 106 and to the second weak state holding path 108 in response to a detected transition of the input signal received at the input 102.
• the voltage pull-up logic circuit 110 is responsive to the control path 112 to stop providing current to the weak state holding paths 106 and 108 to maintain sensitivity of the weak state holding paths 106 and 108 to low voltage signals at the input 102 during non-transition periods.
• the control path 112 is adapted to selectively control activation of the voltage pull-up logic circuit 110.
• the control path 112 includes a self-timed feedback path 118 from the output 104 to the voltage pull-up logic circuit 110.
• the control path 112 may be operative to detect a voltage level change at the output 104 and provide an activation signal to the voltage pull-up control logic 110 to turn off a current to one or more of the weak state holding paths 106 and 108 when the self-timed feedback path 118 determines a particular delay has elapsed based on a transition at the output 104.
• control path 112 includes a delay logic circuit 114 coupled to the input 102.
• control path 112 is operative to detect a transition in the input 102 and to send an activation signal to the voltage pull-up logic circuit 110.
• the activation signal may cause the voltage pull-up logic circuit 110 to begin sourcing current to assist the weak state holding path 106, 108, or both, to transition between logic states.
• the control path 112 may further be operative to send a second control signal to the voltage pull-up logic circuit 110 in response to the delay logic circuit 114 determining a sufficient delay has elapsed since the transition of the input 102.
• the second control signal may deactivate the voltage pull-up logic circuit 110, resuming normal operation of the weak state holding paths 106 and 108 over the broad range of input voltages.
• the delay logic circuitry 114 is adjustable, and may include an adjustable delay component 116 to control a delay associated with the second control signal.
• a first input signal may be received at the input 102 from a first electronic component.
• the level shifting circuit device 100 may translate or shift the input voltage level and generate an output voltage level at the output 104.
• the input signal may be received from a processor, a bus, a memory, or other electronic components and the output may be provided to a processor, a bus, a memory, or other electronic components.
• the first input signal may reflect the voltage levels VO to VlL associated with a first power supply.
• the output 104 may be coupled to one or more other electronic components that operate at the second voltage levels VO to VlH.
• the first voltage level may be a signal associated with a voltage range from 0 V to 1.0 V
• the second voltage level may be a signal associated with a voltage range from 0 V to 3.3 V.
• the first and second weak state holding paths 106 and 108 begin to transition between states.
• the voltage pull-up logic circuit 110 begins supplying current to the first weak state holding path 106, the second weak state holding path 108, or both, to assist in voltage level transition by supplying charge to one or more transistors.
• the voltage pull-up logic circuit 110 begins to supply current in response to detecting that at least one of the weak state holding paths 106 and 108 have started to transition between states.
• the voltage pull-up logic circuit 110 may instead begin to supply current in response to a control signal from the control path 112.
• the control path 112 After a suitable delay period, such as via self-timed feedback path 118, or a delay logic circuit path 114, the control path 112 provides a control signal to deactivate the voltage pull-up logic circuit 110 to stop sourcing current to the weak state holding paths 106, 108. Following the deactivation of the voltage pull-up logic circuit 110, the cross-coupled weak state holding paths 106 and 108 maintain the new output voltage level at the output 104. By selectively activating the voltage pull-up logic circuit 110, a wide range of input operating voltages and a fast output level transition are both provided by the level shifting circuit device 100.
• the level shifting circuit device 200 includes an input 202 configured to receive an input signal corresponding to a first voltage range between a high voltage VddL and a low voltage Vss.
• the level shifting circuit device 200 also includes an output 204 configured to provide an output signal corresponding to a level shifting of the input 202 to a second voltage range, with a high signal represented by a high voltage VddH and a low signal represented by the low voltage Vss.
• the level shifting circuit device 200 also includes a first weak state holding path 206 and a second weak state holding path 208.
• the first weak state holding path 206 is coupled to the input 202, and the second weak state holding path 208 is coupled to the input 202 via an inverter 207 operating at the first voltage range.
• a voltage pull-up logic circuit 210 is coupled to both of the first weak state holding path 206 and to the second weak state holding path 208.
• a control path 212 is coupled to the voltage pull-up logic circuit 210 and to the output 204.
• the first weak state holding path 206 includes a first weak p-channel transistor 220 that has a first terminal coupled to a power supply voltage VddH, a control terminal coupled to the second weak state holding path 208, and a third terminal.
• the first weak state holding path 206 also includes a second weak p-channel transistor 222 including a fourth terminal that is coupled to the third terminal of the first weak p-channel transistor 220.
• the second weak p-channel transistor 222 has a second control terminal coupled the input 202, and a fifth terminal coupled a first node 223.
• the first node 223 is coupled to the voltage pull-up logic circuit 210.
• the first weak state holding path 206 also has a strong n-channel transistor 224 including a sixth terminal coupled to the first node 223, a third control terminal coupled to the input 202, and a seventh terminal coupled to a second power supply voltage Vss.
• a strong transistor has a faster current response to a signal at a control terminal, such as a gate voltage, than a weak transistor, and may have a channel that is wider and shorter than a weak transistor.
• the weak p-channel transistors 220 and 222 may be p-channel MOSFETs with channels that are approximately 0.12 micrometers (um) wide and 0.1 um long
• the strong n-channel transistor 224 may be an n- channel MOSFET with a channel that is approximately 0.6 um wide and 0.04 um long.
• the second weak state holding path 208 includes a first weak p-channel transistor 230 including a first terminal coupled to a power supply voltage VddH, a control terminal coupled to the first weak state holding path 206, and a third terminal coupled to a second weak p-channel transistor 232.
• the second weak p- channel transistor 232 includes a fourth terminal coupled to the third terminal of the first weak p-channel transistor 230, a second control terminal coupled to an output of the inverter 207, and a fifth terminal coupled to a second node 233.
• a strong n-channel transistor 234 has a sixth terminal coupled to the second node 233, a third control terminal coupled to the output of the inverter 207, and a seventh terminal coupled to the second power supply voltage Vss.
• the second node 233 of the second weak state holding path 208 is coupled to the first control terminal of the first weak p-channel transistor 220 of the first weak state holding path 206.
• the first node 223 of the first weak state holding path 206 is coupled to the first control terminal of the first weak p-channel transistor 230 of the second weak state holding path 208.
• the pull-up logic circuit 210 includes a first strong pull-up path 241 that is coupled to the second weak state holding path 208 and also includes a second strong pull-up path 246 that is coupled to the first weak state holding path 206.
• the first strong pull-up path 241 includes a first strong p-channel transistor 242 coupled to the power supply voltage VddH and having a control terminal coupled to the control path 212.
• the first strong pull-up path 241 has a second strong p-channel transistor 244 coupled to the first strong p-channel transistor 242 and further coupled to the first node 223.
• the second strong p-channel transistor 244 has a control terminal that is coupled to the second node 233.
• the second strong pull-up path 246 has a first strong p-channel transistor 248 that is coupled to the power supply voltage VddH and that has a control terminal coupled to the control path 212.
• the second strong pull-up path 246 also includes a second strong p-channel transistor 250 that is coupled between the first strong p-channel transistor 248 and the second node 233 and that has a control terminal coupled to the first node 223.
• the output 204 is coupled to the first node 223 via an output inverter 266.
• the control path 212 is coupled to the output 204, to the control terminal of the first strong p-channel transistor 248 of the second strong pull-up path 246, and to the control terminal of the first strong p-channel transistor 242 of the first strong pull-up path 241 via an inverter 270.
• the control path 212 includes a self-timed feedback path from the output 204 to the voltage pull-up logic circuit 210.
• the voltage pull-up logic circuit 210 begins operating when one of the nodes 223 or 233 transitions from a low voltage level to a high voltage level, and continues operating until the voltage transition at the first node 223 propagates through the output inverter 266 to the control terminals of the transistors 242 and 248 of the strong pull-up paths 241 and 246.
• the resulting control signal provided by the control path 212 to the transistors 242 and 248 of the strong pull-up paths 241 and 246 deactivates the voltage pull-up logic circuit 210.
• the voltage pull-up logic circuit 210 is off.
• at least one of the transistors 242 and 244 of the first strong current path 241 is off (i.e., non-conducting), and at least one of the transistors 248 and 250 of the second strong current path 246 is off.
• a low signal e.g., Vss
• VddH high voltage
• the output inverter 266 has an input coupled to the first node 223, and outputs a low voltage (e.g., Vss, used in this context to include voltages that would be recognized as a "0" signal).
• the strong n-channel transistor 234 of the second weak state holding path 208 is on and the weak p-channel transistors 230 and 232 are off, biasing the second node 233 at a low voltage.
• the first transistor 242 of the first strong pull-up path 241 is off and the second transistor 244 is on.
• the first transistor 248 of the second strong pull-up path 246 is on and the second transistor 250 is off.
• the strong n-channel transistor 224 of the first weak state holding path 206 turns on, bringing the first node 223 from a high voltage state (e.g., VddH) to a low voltage state (e.g., Vss).
• the weak p-channel transistors 220 and 222 operate at states determined by VddH and VddL.
• the weak p-channel transistor 222 may be on, fighting the n-channel transistor 234 to bias the first node at a high voltage state, the stronger n-channel transistor 224 pulls the first node to the low voltage state.
• the strong n-channel transistor 234 of the second weak state holding path 208 turns off, bringing the second node 233 from a low voltage to a high voltage, but the transition is limited by the current flow through the weak p-channel transistor 232.
• the strong p- channel transistor 250 of the second strong pull-up path 246 is turned on, while the transistor 248 also remains on.
• current flows through the second strong pull-up current path 246 to charge the strong n-channel transistor 234.
• the output inverter 266 transitions from a low state to a high state, which is provided via the control path 212 to the control terminal of the transistor 248, turning off the second strong pull-up path 246.
• the strong n-channel transistor 224 of the first weak state holding path 206 remains on and the weak p-channel transistors 220 and 222 are off, biasing the first node 223 at a low voltage (e.g., VddL).
• the output inverter 266 outputs a high voltage (e.g., VddH).
• the strong n-channel transistor 234 of the second weak state holding path 208 is off, biasing the second node 233 at a high voltage.
• the first transistor 242 of the first strong pull-up path 241 is on and the second transistor 244 is off.
• the first transistor 248 of the second strong pull-up path 246 is off and the second transistor 250 is on.
• the output of the inverter 207 transitions from a low state to a high state, turning on the strong n-channel transistor 234 of the second weak state holding path 208 and bringing the second node 233 from a high voltage state to a low voltage state.
• the weak p-channel transistors 230 and 232 operate at states determined by VddH and VddL. Although the weak p-channel transistor 232 may be on, fighting the n-channel transistor 234 to bias the second node at a high voltage state, the stronger n-channel transistor 234 pulls the second node to the low voltage state.
• the strong p- channel transistor 244 of the first strong pull-up path 241 is turned on, while the transistor 242 remains on.
• the weak p-channel transistor 220 is also turned on.
• the output inverter 266 transitions from a high state to a low state, which is provided via the control path 212 and the inverter 270 to the control terminal of the transistor 242, turning off the first strong pull-up path 241.
• the initial transition of one of the nodes 223, 233 from a high state to a low state is limited by the respective weak p- channel transistors 220-222 or 230-232, but the transition of the other node 223 or 233 from the low state to a high state is assisted by the voltage pull-up control circuit 210.
• the voltage pull-up control circuit 210 is off and the cross-coupled weak state holding paths 206 and 208 remain sensitive to low voltage input ranges at the input 202.
• the voltage pull-up logic circuit 210 When a transition occurs at the input 202, the voltage pull-up logic circuit 210 activates to supply current to the weak state holding paths 206 and 208 to accelerate a transition to the new state. The voltage pull-up logic circuit 210 deactivates in response to the control path 212 indicating a transition at the output 204. The voltage pull-up logic circuit 210 therefore provides a pulse of current to assist the weak state holding paths 206 and 208 transition between states in response to the input 202. By selectively activating the voltage pull-up logic circuit 210, a wide range of input operating voltages and a fast output level transition are both provided by the level shifting circuit device 200.
• FIG. 3 is a block diagram of a particular illustrative embodiment of a system 300 including a level shifting circuit device.
• a structure 302 includes a first input 304 coupled to receive a memory cell selection signal.
• a second input 306 is coupled to receive a data signal.
• the first input 304 is provided to a first level shifting circuit 308, and the second input 306 is provided to a second level shifting circuit 310.
• a memory array 312 is coupled to receive an output of the first level shifting circuit 308 and the second level shifting circuit 310.
• the structure 302 operates at a first voltage level Vstruct, and the memory array 312 operates at a second voltage level Varray.
• the first level shifting circuit 308 includes an input 320 to receive the first input
• the first level shifting circuit 308 includes a first weak state holding path 322 coupled to the input 320 and to the output 321.
• the first weak state holding path 322 is also coupled to a cross-coupling circuit, such as a second weak state holding path 326.
• a voltage pull-up logic circuit 328 is coupled to the first weak state holding path 322 and to the second weak state holding path 326.
• a control path 324 is coupled to the voltage pull-up logic circuit 328 to selectively control activation of the voltage pull-up logic circuit 328.
• the first level shifting circuit 308 may include the level shifting circuit device 100 or 200 illustrated in FIGs. 1-2.
• the second level shifting circuit 310 includes an input 330 to receive the second input 306 and an output 331 to provide a first level shifted voltage signal to the memory array 312.
• the second level shifting circuit 310 includes a first weak state holding path 332 coupled to the input 330 and to the output 331.
• the first weak state holding path 332 is also coupled to a cross-coupling circuit, such as a second weak state holding path 336.
• a voltage pull-up logic circuit 338 is coupled to the first weak state holding path 332 and to the second weak state holding path 336.
• a control path 334 is coupled to the voltage pull-up logic circuit 338 to selectively control activation of the voltage pull-up logic circuit 338.
• the second level shifting circuit 310 may include the level shifting circuit device 100 or 200 illustrated in FIGs. 1-2.
• the first input 304 and the second input 306 may be at a first voltage level, such as Vstruct, but the memory array 312 may be powered by a power source at a second voltage level, such as Varray.
• the first voltage level may be less than the second voltage level.
• the level shifting circuits 306 and 308 may shift voltage levels at the inputs 304 and 306 to voltage levels appropriate for the memory array 312.
• the level shifting circuits 306 and 308 include pull-up logic circuits 328 and 338 that are selectively activated by the control paths 324 and 334, respectively, thus enabling fast transitions in response to changes in input signals and also enabling a wide range of operation.
• the level shifting circuits 306 and 308 may be operable in a voltage range including 0.6-1.4 V.
• FIG. 4 is a flow diagram of a particular illustrative embodiment of a method of level shifting using a circuit device, such as the circuit devices illustrated in FIGs. 1-3.
• an input voltage is received at an input to a level shifting circuit that includes voltage pull-up logic.
• the input signal is applied to a first weak state holding path.
• the first weak state holding path may include multiple weak p-channel transistors and a strong n-channel transistor arranged in series.
• an output signal is provided from the level shifting circuit.
• the input signal has a first voltage and the output signal has a second voltage.
• the voltage pull-up logic circuit of the level shifting circuit is selectively activated.
• the voltage pull-up logic circuit provides charge to decrease a transition time of a weak state holding path.
• a control signal is provided to the voltage pull-up logic circuit.
• the control signal may be a feedback signal responsive to the output signal.
• the control signal causes the voltage pull-up logic circuit to discontinue charging a weak state holding path.
• an output of the voltage pull-up logic circuit includes a current pulse that begins in response to the input signal and that ends in response to the control signal.
• FIG. 5 is a block diagram of a representative mobile communications device 500 in which embodiments of the circuits and methods described in FIGs. 1-4 may be used.
• the communications device 500 includes a processor, such as a digital signal processor (DSP) 510.
• DSP digital signal processor
• a level shifting circuit with voltage pull-up logic 564 is coupled to the DSP 510 to provide a voltage level shift between the DSP 510 and a memory device 532.
• the level shifting circuit with voltage pull-up logic 564 includes the circuit device 100, 200, 308, or 310 illustrated in FIGs. 1-3.
• the level shifting circuit with voltage pull-up logic 564 performs the method illustrated in FIG. 4.
• FIG. 5 also shows a display controller 526 that is coupled to the digital signal processor 510 and to a display 528.
• a coder/decoder (CODEC) 534 can also be coupled to the digital signal processor 510.
• a speaker 536 and a microphone 538 can be coupled to the CODEC 534.
• FIG. 5 also indicates that a wireless controller 540 can be coupled to the digital signal processor 510 and to a wireless antenna 542.
• an input device 530 and a power supply 544 are coupled to the on-chip system 522.
• the display 528, the input device 530, the speaker 536, the microphone 538, the wireless antenna 542, and the power supply 544 are external to the on-chip system 522.
• each can be coupled to a component of the on-chip system 522, such as an interface or a controller.
• the level shifting circuit with voltage pull-up logic 564 may also be used to provide level shifting between other components of the communications device 500 that use different voltage levels.
• the level shifting circuit with voltage pull-up logic 564 may be coupled between the on-chip system 522 and the display 528, the input device 530, the speaker 536, the microphone 538, the wireless antenna 542, the power supply 544, or any combination thereof.
• the level shifting circuit with voltage pull-up logic 564 may be coupled between the DSP 510 and any other component of the on-chip system 522.
• the level shifting circuit with voltage pull-up logic 564 may be integrated with the DSP 510 to provide level shifting for components of the DSP 510, such as at a register file that operates at a lower voltage level within the DSP 510.
• voltage level shifting may be performed by a device that includes means for receiving an input voltage at an input to a level shifting circuit that includes voltage pull-up logic, such as, for example, the inputs 102, 202, 320, and 330, illustrated in FIGs. 1-3.
• the device may also include means for providing an output signal from the level shifting circuit, such as, for example, the outputs 104, 204, 321, and 331 and the corresponding circuit structures coupled to the respective outputs as illustrated in FIGs. 1-3.
• the device may also include means for selectively activating the voltage pull-up logic circuit of the level shifting circuit, such as the control paths 112, 212, 324, and 334, as illustrated in FIGs. 1-3.
• a software module may reside in RAM memory, flash memory, ROM memory, PROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
• An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium.
• the storage medium may be integral to the processor.
• the processor and the storage medium may reside in an ASIC.
• the ASIC may reside in a computing device or a user terminal.
• the processor and the storage medium may reside as discrete components in a computing device or user terminal.

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