WO2009081450A1 - Unité d'affichage plasma - Google Patents

Unité d'affichage plasma Download PDF

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Publication number
WO2009081450A1
WO2009081450A1 PCT/JP2007/001454 JP2007001454W WO2009081450A1 WO 2009081450 A1 WO2009081450 A1 WO 2009081450A1 JP 2007001454 W JP2007001454 W JP 2007001454W WO 2009081450 A1 WO2009081450 A1 WO 2009081450A1
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WO
WIPO (PCT)
Prior art keywords
reset
electrode
period
display
vertical synchronization
Prior art date
Application number
PCT/JP2007/001454
Other languages
English (en)
Japanese (ja)
Inventor
Kazuya Yamaguchi
Yoshikazu Kanazawa
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP2007/001454 priority Critical patent/WO2009081450A1/fr
Publication of WO2009081450A1 publication Critical patent/WO2009081450A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/292—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for reset discharge, priming discharge or erase discharge occurring in a phase other than addressing
    • G09G3/2927—Details of initialising
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0238—Improving the black level

Definitions

  • the present invention relates to a plasma display device, and more particularly to a plasma display device with reduced black display luminance.
  • Plasma display devices are widely used as large-screen thin TVs.
  • the panel drive control of the plasma display device is composed of an address period in which a display image is written in the cell, a sustain period in which the cell written in the address period is brightened, and a reset period in which the state of the wall charge of the cell is reset.
  • the One frame image is displayed in gray scale by a plurality of subfields including a reset period, an address period, and a sustain period. By changing the number of times of light emission in the sustain period of each subfield and combining the subfields to be lit, multi-gradation display becomes possible.
  • the plasma display panel has a plurality of pairs of X and Y electrodes extending in the horizontal direction and a plurality of address electrodes extending in the vertical direction.
  • the X and Y electrodes are display electrodes, and a display line is formed by a pair of display electrodes composed of X and Y electrodes.
  • reset discharge is generated between the X and Y electrodes and between the Y electrode and the address electrode in the reset period to adjust the wall charge amount on the display electrode and the address electrode, and write data is written to the address electrode in the address period.
  • a scan pulse is applied to the Y electrode to generate an address discharge to form a wall charge in the cell
  • a sustain pulse is alternately applied between the X and Y electrodes in the sustain period to sustain the written cell. Generate a discharge. As a result, luminance display according to the number of sustain pulses is made possible.
  • the emission luminance of the phosphor accompanying the discharge is directly related to the image display.
  • the reset discharge in the reset period is a discharge for adjusting the wall charge amount and is not related to image display, and is therefore referred to as background light emission. This background light emission occurs even in black display in which all subfields are not lit, so that the luminance of black display is increased and the contrast, which is the luminance ratio of white display and black display, is deteriorated.
  • Patent Documents 1 and 2 A driving method for reducing background light emission is described in Patent Documents 1 and 2.
  • the background light emission is reduced by reducing the reset discharge scale in the reset period, and a high voltage pulse is generated just before the sustain period so that a discharge occurs in the lighting cell even with the wall charge at the time of reset.
  • a charge forming period to be applied is provided.
  • Patent Document 2 in order to suppress the luminance of black display as much as possible, a reset discharge is executed for a display cell in which display data exists, and a reset is performed for a cell in black display in which no display data exists. It is described that no discharge is performed.
  • an object of the present invention is to provide a plasma display device capable of reducing background light emission in black display.
  • a plasma display device includes a display panel having a plurality of display electrodes and a plurality of address electrodes crossing the display electrodes, and the display electrodes and the address electrodes. And a drive unit for driving.
  • the drive unit In the normal display state where the input video data does not correspond to black display, the drive unit has a reset period for generating a first reset discharge and a second reset discharge in the display electrode in a continuous vertical synchronization period.
  • the subfield having an address period for selecting a cell corresponding to display data based on the input video data and a sustain period for generating a sustain discharge in the selected cell is driven at least once in a predetermined number of vertical synchronization periods.
  • the drive unit generates the first reset discharge in at least one subfield in the first vertical synchronization period when the input video data is in a black display state corresponding to black display, and the first reset discharge is generated in the first vertical synchronization period.
  • the second reset release is performed in at least one subfield.
  • the luminance of the background light emission due to the reset discharge can be reduced.
  • the drive unit generates a first reset discharge by applying a positive blunt wave reset pulse to the first display electrode in the reset period, A negative blunt wave reset pulse is applied to the first display electrode to generate the second reset discharge.
  • the drive unit does not apply a pulse for selecting a cell in the address period to the display electrode and the address electrode in the black display state, and the drive unit in the sustain period.
  • a pulse for generating a sustain discharge is not applied to the display electrode.
  • the first and second vertical synchronization periods occur alternately, or the first and second vertical synchronization periods are between them. Are alternately generated with the third vertical synchronization period interposed therebetween.
  • the drive unit generates the first reset discharge in a single subfield in the first vertical synchronization period in the black display state, In the second vertical synchronization period, the second reset discharge is generated in a single subfield.
  • the second reset discharge is caused by applying a negative obtuse wave reset pulse twice and the reset discharge between the display electrode and the address electrode. And a reset discharge between the display electrodes.
  • the present invention it is possible to reduce the luminance of background light emission while generating a reset discharge for charge adjustment in a black display operation.
  • Display panel 30 Display panel 30, 33, 34: Display electrode drive circuit 35: Address electrode drive circuit 36: Control unit 42: Display data processing unit Video: Input video data A-DATA: Display data
  • FIG. 1 is a panel configuration diagram of the plasma display device according to the present embodiment.
  • a front substrate 11 and a rear substrate 16 are arranged with a discharge space interposed therebetween.
  • a plurality of pairs of an X electrode composed of a transparent electrode 12 and a metal bus electrode 13 superimposed thereon, and a Y electrode composed of a transparent electrode 14 and a metal bus electrode 15 superimposed thereon are arranged.
  • These X and Y electrodes are covered with a dielectric layer IFa.
  • the X and Y electrodes constitute display electrodes, and the X and Y electrodes are arranged for each display line.
  • the rear substrate 16 has a plurality of address electrodes 17, partition walls 18 disposed between the address electrodes 17, and phosphor layers 19R, 19G, and 19B provided on the address electrodes 17 and the partition walls 18. .
  • the phosphor layers 19R, 19G, and 19B are excited by ultraviolet rays that are generated when a discharge occurs in the discharge space, and emit red, green, and blue light, respectively.
  • the emitted light passes through the transparent electrodes 12 and 14 of the front substrate 11 and is emitted to the front side.
  • the barrier ribs 18 have a stripe shape along the address electrodes 17. However, the barrier ribs 18 may have a lattice shape surrounding the periphery of the cell.
  • FIG. 2 is a cross-sectional view of the panel of FIG.
  • FIG. 2 is a cross-sectional view taken along the address electrode 17 of FIG. 1 and is given the same reference numbers as FIG. That is, on the front substrate 11, an X electrode composed of the transparent electrode 12 and the metal bus electrode 13, a Y electrode composed of the transparent electrode 14 and the metal bus electrode 15, and a dielectric layer IFa covering them are formed. Further, a protective film 21 made of MgO and single crystal MgO particles 22 are disposed on the dielectric layer IFa.
  • the MgO of the protective film 21 is a polycrystal formed by vapor deposition or sputtering, whereas the MgO particles 22 are single crystal.
  • address electrodes 17, a dielectric layer IFb covering the address electrodes 17, and a phosphor 19 are formed on the rear substrate 16.
  • the partition wall 18 is not shown.
  • FIG. 3 is a configuration diagram of the drive unit of the plasma display device in the present embodiment.
  • the panel 10 is shown in a state where the front substrate 11 and the rear substrate 16 overlap each other.
  • the X electrodes X and Y electrodes Y extending in the horizontal direction are alternately arranged, and the address electrodes ADD extending in the vertical direction are provided.
  • a cell CELL is formed at the intersection of the X and Y electrode pair and the address electrode ADD.
  • the drive unit is controlled by the X electrode drive circuit 30 that drives the X electrode, the Y electrode drive circuit 32 that drives the Y electrode, the address electrode drive circuit 35 that drives the address electrode, and the drive circuits 30, 32, and 35. And a control circuit 36 for supplying signals S30, S32, and S35 to control the driving operation of the driving circuit.
  • the control circuit 36 is constituted by a microcomputer, for example.
  • the X electrode drive circuit 30 and the Y electrode drive circuit 32 constitute a display electrode drive circuit.
  • the X electrode drive circuit 30 applies a common drive pulse to all the X electrodes, applies a reset pulse and an address voltage to the X electrodes, and applies a sustain pulse to the X electrodes.
  • a sustain driving circuit X-SUS a sustain driving circuit X-SUS.
  • the Y electrode drive circuit 32 includes a scan drive circuit Y-SCAN that sequentially applies a scan pulse to the Y electrode, a reset address drive circuit YR / A that applies a reset pulse and an address voltage to the Y electrode, And a sustain drive circuit Y-SUS for applying a sustain pulse to the electrodes.
  • the control circuit 36 receives the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, the synchronization clock CLK, and the RGB video data signals R, G, Bdata, and the drive control signals 30S, 32S, necessary for driving the panel 10.
  • 35S is supplied to each drive circuit 30, 32, 35.
  • the control signal 35S to the address electrode drive circuit 35 includes display data generated for each subfield based on the video data signal in addition to the drive control signal.
  • a gain adjustment circuit GAIN for adjusting the gradation values of the input RGB video data signals Rdata, Gdata, and Bdata is provided in the previous stage of the control circuit 36.
  • the gain adjustment circuit GAIN adjusts the gradation values of the R, G, and B data signals in accordance with the color temperature adjustment signal CT and the hue adjustment signal C-CON to obtain the requested color temperature or hue.
  • the video data signals Rdata, Gdata, and Bdata may be analog signals or digital signals.
  • the control circuit 36 has a sustain pulse table 37. Based on the automatic power control signal APC-CON and the contrast control signal CONT-CON, the control circuit 36 sets the optimum number of sustain pulses for a plurality of subfields in one vertical synchronization period. Select a combination.
  • the automatic power control signal APC-CON is a signal for reducing the number of sustain pulses in the sub-field when the video load factor is high and the drive circuit power is expected to increase, so that the drive circuit power exceeds the reference value. Do not.
  • the contrast control signal CONT-CON further reduces the number of sustain pulses for dark images and increases the number of sustain pulses for bright images in order to increase contrast.
  • FIG. 4 is a diagram showing panel driving of the plasma display device according to the present embodiment.
  • one vertical synchronization period VT defined by one cycle of the vertical synchronization signal Vsync corresponds to one field FL
  • the one vertical synchronization period VT has a plurality of subfields SF1 to SFn.
  • Each subfield SF1 to SFn has a reset period Reset, an address period Tadd, and a sustain period Tsus.
  • the vertical synchronization period VT (field FL) and the frame are the same.
  • two vertical synchronization periods (2 fields FL) correspond to one frame.
  • the vertical synchronization period VT shown in FIG. 4 is continuously repeated in synchronization with the vertical synchronization signal Vsync.
  • FIG. 5 is a driving waveform diagram of panel driving in the normal display state of the present embodiment.
  • FIG. 5 shows a driving waveform of one subfield SF.
  • the example of FIG. 5 is an example in which the sustain pulse Psus has positive and negative sustain voltages + Vs and ⁇ Vs.
  • the Y electrode driving circuit 32 rises from the voltage Ve with a predetermined gradient to the positive ultimate voltage + Vw (> Vs).
  • a positive blunt wave pulse Presp is applied to the Y electrode.
  • a weak reset discharge is continuously generated between the X and Y electrodes, and a positive charge on the X electrode and a negative charge on the Y electrode as wall charges, respectively. It is formed.
  • the X electrode drive circuit 30 applies a positive voltage + Vx (+ Vs) to the X electrode, and the Y electrode drive circuit 32 temporarily lowers the Y electrode from the voltage + Vw, and further with a predetermined slope.
  • a negative blunt wave pulse Presn that decreases in potential and reaches a negative ultimate voltage ⁇ Vy + ⁇ is applied to the Y electrode.
  • a weak discharge is generated between X and Y, and the wall charges on the X and Y electrodes accumulated by the reset discharge by the positive blunt wave pulse Presp are reduced.
  • the wall charge amount is adjusted to be optimal for discharge.
  • a weak discharge is generated between the address electrode ADD and the Y electrode, and the wall charge on the address electrode is adjusted.
  • the X electrode drive circuit 30 maintains the X electrode at the positive voltage + Vx, and the reset address drive circuit YR / A in the Y electrode drive circuit 32 sets all the Y electrodes to be negative. While maintaining the voltage Vsc, the scan driving circuit Y-SCAN sequentially applies the scan pulse Psc of the negative voltage ⁇ Vy to the Y electrode. In synchronization with the application of the scan pulse Psc to the Y electrode, the address electrode drive circuit 35 applies the address pulse Padd having the address voltage Va to the address electrode ADD corresponding to the display data.
  • the sustain drive circuits X-SUS and Y-SUS of the X and Y electrode drive circuits 30 and 32 are generated between the positive sustain voltage + Vs and the negative sustain voltage -Vs.
  • the pulse Psus is applied alternately to the Y electrode and the X electrode.
  • the sustain pulse Psus is applied, the voltage applied between the X and Y electrodes is superimposed with the voltage due to the negative charge and the positive charge accumulated in the address period, and a sustain discharge is generated in the cell written in the address period.
  • the number of sustain pulses is set to a number corresponding to the luminance weight given to each subfield, and a sustain discharge occurs in the lighted cell in which the address discharge has occurred, and the luminance corresponding to each subfield is output. .
  • the luminance in the field or frame period can be made to correspond to the gradation value of the input video signal.
  • FIG. 6 is a driving waveform diagram of panel driving in the normal display state of the present embodiment.
  • FIG. 6 shows a driving waveform of one subfield SF.
  • the example of FIG. 6 is an example in which the sustain pulse Psus has the ground GND and the positive sustain voltage +2 Vs around the voltage + Vs.
  • the sustain drive circuits X-SUS and Y-SUS only need to have positive power supply voltages + Vs and +2 Vs in addition to the ground GND, the circuit configuration is simple compared to the case of FIG. It becomes.
  • the drive waveform of the X electrode has the ground GND, the address voltage 2Vx, and the sustain voltage + 2Vs around the voltage Vs, and the drive waveform of the X electrode of FIG. 5 is increased by the voltage Vs.
  • the waveform is shifted. That is, the sustain pulse Psus is a pulse between the ground GND and + 2Vs.
  • the power supply of the X electrode drive circuit 30 is only the positive power supply voltages + Vs, + 2Vx, + 2Vs.
  • the drive waveform of the Y electrode is the same as that in FIG. 5 in the reset period Reset and the address period Tadd, and the sustain pulse Psus in the sustain period Tsus is a pulse between the ground GND and +2 Vs.
  • the drive waveforms shown in FIGS. 5 and 6 are drive waveforms in the first subfield SF1 among the plurality of subfields SF in the vertical synchronization period VT shown in FIG.
  • the other subfields SF2 to SFn there is no first reset waveform in the first half in the reset period Treset of the drive waveforms in FIGS. 5 and 6, and the second reset waveform in the second half, that is, while applying ⁇ Vx to the X electrode. Only a reset waveform for applying a negative blunt wave pulse Presn to the Y electrode is formed.
  • the sustain discharge using the Y electrode as the anode and the X electrode as the cathode becomes the last discharge, and the state before the reset period of the subfields SF2 to SFn starts.
  • positive charges and negative charges are accumulated as wall charges on the X electrode of the cell that is lit in the sustain period of the immediately preceding subfield.
  • the amount of wall charges of the cell lit in the immediately preceding subfield is adjusted by the reset discharge by the negative blunt wave pulse Presn.
  • the drive waveforms in the address period and the sustain period of the subfields SF2 to SFn are the same as those in FIGS.
  • the first reset discharge by the positive blunt wave pulse and the second reset discharge by the negative blunt wave pulse are performed, and in the remaining subfields Only the second reset discharge by the negative obtuse wave pulse is performed. Furthermore, the subfield having the first and second reset discharges may be performed only once in a plurality of vertical synchronization periods VT. Thereby, the background light emission luminance in the normal display state can be reduced.
  • FIG. 7 is a diagram showing continuous vertical synchronization periods in the present embodiment. As shown in FIG. 7, the vertical synchronization period VT defined in synchronization with the vertical synchronization signal Vsync is continuously generated. However, FIG. 7 shows only two vertical synchronization periods 1VT and 2VT.
  • the vertical synchronization signal Vsyc has a frequency of 60 Hz, and the vertical synchronization period VT is 1/60 sec.
  • the control circuit 36 shown in FIG. 3 controls the drive circuits 30, 32, and 35 in the normal display state when detecting that all the RGB gradation values of the video data signal input from the gain adjustment circuit GAIN are not zero. . Further, when the control circuit 36 detects that all the gradation values of RGB of the video data signal are zero, it controls the drive circuits 30, 32, and 35 in the black display state.
  • the control circuit 36 repeats the subfield based on the drive waveform shown in FIGS. 5 and 6 and the subfield based on the drive waveform excluding the reset waveform due to the positive obtuse wave pulse Presp from FIGS. Then, drive control is performed in the vertical synchronization period VT. As a result, an image corresponding to the video data signal is displayed.
  • the control circuit 36 causes the X and Y electrode drive circuit and the address electrode drive circuit to generate a drive waveform for the reset period (both the first and second reset pulses), and for the address period and the sustain period. The scan pulse, address pulse, and sustain pulse are not generated.
  • the reset period shown in FIGS. Driving is performed to stop driving in the address period and the sustain period.
  • the second black display operation only the first reset discharge by the first reset pulse Presp in the reset period is performed in the first vertical synchronization period 1VT.
  • the second vertical synchronization period 2VT that occurs after the vertical synchronization period 1VT, only the second reset discharge by the second reset pulse Presn in the reset period is performed.
  • the driving in the address period and the sustain period is not performed in each subfield. Therefore, even if the first reset discharge and the second reset discharge are performed in the different vertical synchronization periods 1VT and 2VT, as described in FIG.
  • the panel can be operated in the reset period.
  • the first and second vertical synchronization periods 1VT and 2VT may be generated alternately or alternately with one or a plurality of third vertical synchronization periods interposed therebetween. May occur.
  • both the first and second reset operations shown in FIGS. 5 and 6 are performed intermittently in successive vertical synchronization periods, that is, every other or every second vertical synchronization period. Can also be considered. However, in that case, the luminance of background light emission by one reset including the first and second reset operations is not reduced, and the frequency of background light emission is reduced. Therefore, there is a possibility that background light emission is recognized as flicker by human eyes, which is not preferable as compared with the second black display operation.
  • FIG. 8 is a diagram showing a drive waveform in the first black display operation in the present embodiment.
  • FIG. 8 shows the drive waveform of the first subfield in the vertical synchronization period, and corresponds to the drive waveform centered on the ground GND of FIG.
  • the Y electrode drive circuit 30 applies the first obtuse wave reset pulse Presp that gradually increases from the voltage Ve to Vw while the X electrode drive circuit 30 applies ⁇ Vx to the X electrode. Apply to.
  • the Y electrode drive circuit 32 temporarily reduces the potential of the Y electrode from Vw and then gradually decreases to the voltage ⁇ Vy + ⁇ .
  • a second blunt wave reset pulse Presn is applied to the Y electrode.
  • the Y electrode drive circuit 32 does not apply the scan pulse to the Y electrode, and the address electrode drive circuit 35 does not apply the address pulse to the address electrode. Therefore, address discharge does not occur. Further, in the sustain period Tsus, the X and Y electrode drive circuits 30 and 32 maintain the X and Y electrodes at the ground GND and do not apply a sustain pulse to the X and Y electrodes.
  • FIG. 9 is a diagram showing a drive waveform in the first black display operation in the present embodiment.
  • the drive waveform of the first one subfield in the vertical synchronization period is shown and corresponds to the drive waveform centered on the voltage Vs in FIG. Therefore, also in FIG. 9, the positive blunt wave reset pulse Presp and the negative blunt wave reset pulse Presn are applied to the Y electrode in the reset period Treset, and a pulse that drops from the voltage Vs to the ground GND is applied to the X electrode. .
  • the drive waveform of the X electrode is a voltage centered on Vs.
  • the drive waveforms of the address electrode and the Y electrode are the same as in FIG.
  • FIGS. 10 and 11 are diagrams showing drive waveforms in the second black display operation in the present embodiment.
  • FIGS. 10 and 11 also show driving waveforms of one subfield, and correspond to driving waveforms using + Vs and ⁇ Vs power sources with the ground GND in FIGS. 5 and 8 as the center.
  • a positive blunt wave reset pulse Presp is applied by the drive waveform shown in FIG. 10 in the first vertical synchronization period to generate the first reset discharge, and the first vertical synchronization period.
  • a negative blunt wave reset pulse Presn is applied by the drive waveform shown in FIG. 11 to generate a second reset discharge.
  • FIG. 10 shows a drive waveform in one subfield, for example, the first subfield in the first vertical synchronization period 1VT.
  • the Y electrode drive circuit 32 applies the voltage Ve to the Y electrode
  • the X electrode drive circuit 30 applies a voltage that gradually decreases from the ground GND to ⁇ Vx to the X electrode. This generates a weak reset discharge between the X and Y electrodes.
  • the X electrode driving circuit 30 keeps the X electrode at ⁇ Vx
  • the Y electrode driving circuit 32 applies the obtuse wave pulse Presp that gradually increases from the voltage Ve to Vw. This generates a weak reset discharge between the X and Y electrodes.
  • both the X and Y electrodes are maintained at the ground GND. Further, all the electrodes are maintained at the ground GND even in the address period Tadd and the sustain period Tsus. No scan pulse or sustain pulse is applied. In other words, in the first vertical synchronization period 1VT, only the first reset discharge is generated by the positive reset pulse Presp.
  • FIG. 11 shows driving waveforms in one subfield, for example, the first subfield, in the second vertical synchronization period 2VT after the first vertical synchronization period 1VT.
  • the X electrode drive circuit 30 applies a voltage + Vx to the X electrode
  • the Y electrode drive circuit 32 applies a negative blunt wave reset pulse Presn that gradually decreases from the ground to the voltage ⁇ Vy + ⁇ to the Y electrode. .
  • the amount of charge formed on the X and Y electrodes is reduced and adjusted to an appropriate amount.
  • the X, Y electrodes and address electrodes are kept at ground.
  • the scan pulse and the sustain pulse are not applied in the address period Tadd and the sustain period Tsus. In other words, in the second vertical synchronization period 2VT, only the second reset discharge is generated by the negative reset pulse Presn.
  • FIGS. 12 and 13 are diagrams showing drive waveforms in the second black display operation in the present embodiment.
  • FIGS. 12 and 13 also show driving waveforms of one subfield, and correspond to driving waveforms using +2 Vs, GND power supply with Vs in FIGS. 6 and 9 as the center. The rest is the same as FIG. 10 and FIG.
  • FIG. 12 shows a drive waveform of one subfield within the first vertical synchronization period 1VT.
  • the drive waveform of the X electrode is the ground GND and the voltage Vs.
  • the drive waveforms of the address electrode and the Y electrode are the same as in FIG. As shown in FIG. 12, only the first reset discharge is generated by the positive reset pulse Presp in the first vertical synchronization period 1VT.
  • FIG. 13 shows a drive waveform of one subfield in the second vertical synchronization period 2VT.
  • the drive waveform of the X electrode is the voltage Vs, + 2Vx.
  • the drive waveforms of the address electrode and the Y electrode are the same as in FIG. In the second vertical synchronization period 2VT, only the second reset discharge is generated by the negative reset pulse Presn.
  • the wall charges on the X and Y electrodes are erased by the positive blunt wave reset pulse Presp in the first vertical synchronization period. Generates wall charges of opposite polarity. Then, the amount of wall charges on the X and Y electrodes is adjusted by the negative blunt wave reset pulse Presn in the second vertical synchronization period. Since electrode driving is not performed in the address period and the sustain period, even if the first reset discharge and the second reset discharge are performed in different vertical synchronization periods, the same wall charge reset action as the reset operation in the normal display operation Can be obtained.
  • the two reset discharges are performed in different vertical synchronization periods, the luminance of the background light emission due to each reset discharge can be lowered, and the occurrence of flicker can be suppressed.
  • FIGS. 14 and 15 are diagrams showing modified examples of drive waveforms in the second black display operation in the present embodiment. 14 corresponds to the drive waveform centered on the ground GND in FIGS. 5 and 8, and FIG. 15 corresponds to the drive waveform centered on + Vs in FIGS.
  • the second reset discharge includes a reset discharge generated between the Y electrode and the address electrode by applying a negative blunt wave reset pulse Presn to the Y electrode while maintaining the X electrode at the ground GND, and the X electrode. Is maintained at the voltage + Vx, and a negative discharge wave reset pulse Presn is applied to the Y electrode to generate a reset discharge generated between the Y electrode and the X electrode.
  • the wall charge amount can be more accurately determined. Adjustments can be made.
  • the second reset discharge includes a reset discharge generated between the Y electrode and the address electrode by maintaining the X electrode at the voltage Vs and applying a negative blunt wave reset pulse Presn to the Y electrode,
  • a reset discharge is generated between the Y electrode and the X electrode by maintaining the electrode at the voltage + 2Vx and applying a negative blunt wave reset pulse Presn to the Y electrode.
  • a first vertical synchronization period in which a first reset discharge is generated by a positive obtuse wave pulse and a second reset discharge is generated by a negative obtuse wave pulse.
  • the luminance value of the screen in black display can be further lowered by gradually increasing the period between the vertical synchronization periods, that is, by intermittently generating the first and second vertical synchronization periods.
  • the first reset discharge by the positive obtuse wave reset pulse and the second reset by the negative obtuse wave reset pulse are performed. Since the reset discharge is executed separately, the luminance of the background light emission due to the reset discharge can be reduced, and the contrast which is the luminance ratio between the white display and the black display can be improved.
  • the first black display operation by combining the first black display operation and the second black display operation, it is possible to reduce the change in the luminance value of the screen when the normal display operation is shifted to the black display operation without any sense of incongruity.
  • the present invention can obtain useful results when applied to a plasma display device.

Abstract

L'unité d'affichage plasma selon l'invention possède un panneau d'affichage ayant une pluralité d'électrodes d'affichage et une pluralité d'électrodes d'adresse croisant les électrodes d'affichage, et une unité de commande pour commander les électrodes d'affichage et les électrodes d'adresse. Au cours d'une période de synchronisation verticale continue dans un état d'affichage normal où les données vidéo d'entrée ne correspondent jamais à l'affichage de couleur noire, l'unité de commande répète plusieurs fois une commande du sous-champ ayant une période de réinitialisation pour générer une première décharge de réinitialisation et une seconde décharge de réinitialisation sur les électrodes d'affichage, une période d'adressage pour les cellules d'éclairage correspondant aux données d'affichage générées en fonction des données vidéo d'entrée et une période de soutien pour générer la décharge de soutien sur les cellules d'éclairage. En outre, dans un état d'affichage de couleur noire où les données vidéo d'entrée correspondent à l'affichage de couleur noire, l'unité de commande effectue l'opération de commande de l'affichage de couleur noire pour générer la première décharge de réinitialisation au cours d'une première période de synchronisation verticale et pour générer la seconde décharge de réinitialisation au cours d'une seconde période de synchronisation verticale suivant la première période de synchronisation verticale.
PCT/JP2007/001454 2007-12-21 2007-12-21 Unité d'affichage plasma WO2009081450A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/001454 WO2009081450A1 (fr) 2007-12-21 2007-12-21 Unité d'affichage plasma

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/001454 WO2009081450A1 (fr) 2007-12-21 2007-12-21 Unité d'affichage plasma

Publications (1)

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WO2009081450A1 true WO2009081450A1 (fr) 2009-07-02

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PCT/JP2007/001454 WO2009081450A1 (fr) 2007-12-21 2007-12-21 Unité d'affichage plasma

Country Status (1)

Country Link
WO (1) WO2009081450A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10301528A (ja) * 1997-04-24 1998-11-13 Mitsubishi Electric Corp プラズマディスプレイの駆動方法
JP2003066900A (ja) * 2001-08-24 2003-03-05 Sony Corp プラズマ表示装置及びその駆動方法
JP2004004513A (ja) * 2002-04-25 2004-01-08 Fujitsu Hitachi Plasma Display Ltd プラズマディスプレイパネルの駆動方法およびプラズマディスプレイ装置
JP2005122120A (ja) * 2003-10-16 2005-05-12 Samsung Sdi Co Ltd プラズマディスプレイパネルの駆動方法及び駆動装置
JP2006091295A (ja) * 2004-09-22 2006-04-06 Matsushita Electric Ind Co Ltd プラズマディスプレイパネルの駆動方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10301528A (ja) * 1997-04-24 1998-11-13 Mitsubishi Electric Corp プラズマディスプレイの駆動方法
JP2003066900A (ja) * 2001-08-24 2003-03-05 Sony Corp プラズマ表示装置及びその駆動方法
JP2004004513A (ja) * 2002-04-25 2004-01-08 Fujitsu Hitachi Plasma Display Ltd プラズマディスプレイパネルの駆動方法およびプラズマディスプレイ装置
JP2005122120A (ja) * 2003-10-16 2005-05-12 Samsung Sdi Co Ltd プラズマディスプレイパネルの駆動方法及び駆動装置
JP2006091295A (ja) * 2004-09-22 2006-04-06 Matsushita Electric Ind Co Ltd プラズマディスプレイパネルの駆動方法

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