WO2009069696A1 - Circuit d'attaque de source, procédé de fabrication de circuit d'attaque de source, et module à cristaux liquides - Google Patents

Circuit d'attaque de source, procédé de fabrication de circuit d'attaque de source, et module à cristaux liquides Download PDF

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Publication number
WO2009069696A1
WO2009069696A1 PCT/JP2008/071539 JP2008071539W WO2009069696A1 WO 2009069696 A1 WO2009069696 A1 WO 2009069696A1 JP 2008071539 W JP2008071539 W JP 2008071539W WO 2009069696 A1 WO2009069696 A1 WO 2009069696A1
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WO
WIPO (PCT)
Prior art keywords
source driver
semiconductor chip
terminals
wiring region
liquid crystal
Prior art date
Application number
PCT/JP2008/071539
Other languages
English (en)
Japanese (ja)
Inventor
Tatsuya Katoh
Original Assignee
Sharp Kabushiki Kaisha
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Kabushiki Kaisha filed Critical Sharp Kabushiki Kaisha
Priority to US12/734,844 priority Critical patent/US8373262B2/en
Priority to KR1020107013699A priority patent/KR101158380B1/ko
Priority to CN2008801183252A priority patent/CN101878524B/zh
Publication of WO2009069696A1 publication Critical patent/WO2009069696A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0209—External configuration of printed circuit board adapted for heat dissipation, e.g. lay-out of conductors, coatings
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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    • H01L2224/812—Applying energy for connecting
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10681—Tape Carrier Package [TCP]; Flexible sheet connector
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/361—Assembling flexible printed circuits with other printed circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Liquid Crystal (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention porte sur un circuit d'attaque de source de type sous-film, dans lequel une puce de semi-conducteur ayant une pluralité de bornes devant être connectées à l'extérieur est montée sur la surface d'une base de film. Le circuit d'attaque de source comprend une région de câblage de borne d'entrée ayant des lignes de câblage formées pour être connectées aux bornes d'entrée de la puce de semi-conducteur, et une région de câblage de borne de sortie ayant des lignes de câblage formées pour être connectées aux bornes de sortie de la puce de semi-conducteur. Sur les deux extrémités de la base de film, des parties d'entraînement sont formées pour avoir des trous continus et une feuille de cuivre sur les surfaces. La région de câblage de borne d'entrée et la région de câblage de borne de sortie sont formées dans des sens mutuellement opposés vers les côtés n'ayant pas de partie d'entraînement. Un motif de conduction de chaleur est formé pour connecter les bornes de la puce de semi-conducteur autres que la borne d'entrée et la borne de sortie à la feuille de cuivre de la partie d'entraînement. Il est ainsi possible de proposer non seulement le circuit d'attaque de source capable d'augmenter le dégagement de chaleur mais également un procédé de fabrication de circuit d'attaque de source, et un module à cristaux liquides.
PCT/JP2008/071539 2007-11-30 2008-11-27 Circuit d'attaque de source, procédé de fabrication de circuit d'attaque de source, et module à cristaux liquides WO2009069696A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US12/734,844 US8373262B2 (en) 2007-11-30 2008-11-27 Source driver, method for manufacturing same, and liquid crystal module
KR1020107013699A KR101158380B1 (ko) 2007-11-30 2008-11-27 소스 드라이버, 소스 드라이버의 제조 방법, 및 액정 모듈
CN2008801183252A CN101878524B (zh) 2007-11-30 2008-11-27 源极驱动器、源极驱动器的制造方法和液晶模块

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-311627 2007-11-30
JP2007311627A JP4344766B2 (ja) 2007-11-30 2007-11-30 ソースドライバ、ソースドライバの製造方法、および液晶モジュール

Publications (1)

Publication Number Publication Date
WO2009069696A1 true WO2009069696A1 (fr) 2009-06-04

Family

ID=40678588

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/071539 WO2009069696A1 (fr) 2007-11-30 2008-11-27 Circuit d'attaque de source, procédé de fabrication de circuit d'attaque de source, et module à cristaux liquides

Country Status (6)

Country Link
US (1) US8373262B2 (fr)
JP (1) JP4344766B2 (fr)
KR (1) KR101158380B1 (fr)
CN (1) CN101878524B (fr)
TW (1) TWI416640B (fr)
WO (1) WO2009069696A1 (fr)

Cited By (1)

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JPWO2013051236A1 (ja) * 2011-10-05 2015-03-30 パナソニック株式会社 表示装置

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JP5325684B2 (ja) * 2009-07-15 2013-10-23 ルネサスエレクトロニクス株式会社 半導体装置
JP2012073388A (ja) * 2010-09-28 2012-04-12 Hitachi Displays Ltd 液晶表示装置
WO2014136735A1 (fr) * 2013-03-04 2014-09-12 ピーエスフォー ルクスコ エスエイアールエル Dispositif semi-conducteur
JP5657767B2 (ja) * 2013-10-30 2015-01-21 ルネサスエレクトロニクス株式会社 半導体装置
JP6711582B2 (ja) * 2015-10-14 2020-06-17 ホシデン株式会社 プラグコネクタ及びアダプタ
KR102392683B1 (ko) * 2015-11-30 2022-05-02 엘지디스플레이 주식회사 터치스크린 내장형 표시장치
JP2018085522A (ja) * 2017-12-21 2018-05-31 ルネサスエレクトロニクス株式会社 半導体装置
CN110323198B (zh) * 2019-07-26 2024-04-26 广东气派科技有限公司 非接触式上下芯片封装结构及其封装方法

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JPH07245324A (ja) * 1994-03-07 1995-09-19 Hitachi Ltd 半導体装置
JP2004111996A (ja) * 1996-03-26 2004-04-08 Canon Inc 接続構造体及び表示装置
JP2003108017A (ja) * 2001-09-27 2003-04-11 Pioneer Electronic Corp フラットパネル型表示装置
JP2005109254A (ja) * 2003-09-30 2005-04-21 Optrex Corp 集積回路搭載基板およびこれを備えた表示装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2013051236A1 (ja) * 2011-10-05 2015-03-30 パナソニック株式会社 表示装置

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CN101878524A (zh) 2010-11-03
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JP2009135340A (ja) 2009-06-18
CN101878524B (zh) 2012-10-03
KR20100087040A (ko) 2010-08-02
TW200947570A (en) 2009-11-16
TWI416640B (zh) 2013-11-21
KR101158380B1 (ko) 2012-06-22

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