WO2009057211A1 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
- Publication number
- WO2009057211A1 WO2009057211A1 PCT/JP2007/071235 JP2007071235W WO2009057211A1 WO 2009057211 A1 WO2009057211 A1 WO 2009057211A1 JP 2007071235 W JP2007071235 W JP 2007071235W WO 2009057211 A1 WO2009057211 A1 WO 2009057211A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- conductive film
- memory layer
- forming
- mask
- semiconductor device
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 238000005530 etching Methods 0.000 abstract 2
- 238000009413 insulation Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
第1の導電膜28aと第1の記憶層36と第2の導電膜38とを形成する工程と、第1の方向に延在する線状のパターンを有する第1のマスクを形成する工程と、第1のマスクを用いて、第2の導電膜、第1の記憶層及び第1の導電膜をエッチングする工程と、第1の導電膜、第1の記憶層及び第2の導電膜を埋め込むように、第1の絶縁層42を形成する工程と、第3の導電膜32と第2の記憶層48と第4の導電膜56とを形成する工程と、第1の方向と交差する第2の方向に延在する線状のパターンを有する第2のマスクを形成する工程と、第2のマスクを用いて、第4の導電膜、第2の記憶層、第3の導電膜、第2の導電膜及び第1の記憶層をエッチングする工程とを有し、第1の導電膜と第3の導電膜とが交差する箇所に、第1の導電膜の一部である第1の下部電極と、第1の記憶層と、第2の導電膜より成る第1の上部電極とを有する第1の記憶素子30を形成する。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2007/071235 WO2009057211A1 (ja) | 2007-10-31 | 2007-10-31 | 半導体装置及びその製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2007/071235 WO2009057211A1 (ja) | 2007-10-31 | 2007-10-31 | 半導体装置及びその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2009057211A1 true WO2009057211A1 (ja) | 2009-05-07 |
Family
ID=40590621
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2007/071235 WO2009057211A1 (ja) | 2007-10-31 | 2007-10-31 | 半導体装置及びその製造方法 |
Country Status (1)
Country | Link |
---|---|
WO (1) | WO2009057211A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009283486A (ja) * | 2008-05-19 | 2009-12-03 | Toshiba Corp | 不揮発性記憶装置及びその製造方法 |
JP2011520265A (ja) * | 2008-05-01 | 2011-07-14 | インターモレキュラー,インク. | 不揮発性抵抗スイッチングメモリ |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003197877A (ja) * | 2001-09-26 | 2003-07-11 | Sharp Corp | 共有ビット線クロスポイントメモリアレイ |
JP2003243623A (ja) * | 2002-02-19 | 2003-08-29 | Seiko Epson Corp | 強誘電体キャパシタを有するメモリセルアレイおよびその製造方法ならびに強誘電体メモリ装置 |
JP2005317787A (ja) * | 2004-04-28 | 2005-11-10 | Matsushita Electric Ind Co Ltd | スイッチング素子およびそれを用いたアレイ型機能素子 |
JP2007027537A (ja) * | 2005-07-20 | 2007-02-01 | Sharp Corp | 可変抵抗素子を備えた半導体記憶装置 |
JP2007165873A (ja) * | 2005-12-12 | 2007-06-28 | Hitachi Global Storage Technologies Netherlands Bv | 単極抵抗ランダムアクセスメモリ(rram)デバイス、および垂直スタックアーキテクチャ |
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2007
- 2007-10-31 WO PCT/JP2007/071235 patent/WO2009057211A1/ja active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003197877A (ja) * | 2001-09-26 | 2003-07-11 | Sharp Corp | 共有ビット線クロスポイントメモリアレイ |
JP2003243623A (ja) * | 2002-02-19 | 2003-08-29 | Seiko Epson Corp | 強誘電体キャパシタを有するメモリセルアレイおよびその製造方法ならびに強誘電体メモリ装置 |
JP2005317787A (ja) * | 2004-04-28 | 2005-11-10 | Matsushita Electric Ind Co Ltd | スイッチング素子およびそれを用いたアレイ型機能素子 |
JP2007027537A (ja) * | 2005-07-20 | 2007-02-01 | Sharp Corp | 可変抵抗素子を備えた半導体記憶装置 |
JP2007165873A (ja) * | 2005-12-12 | 2007-06-28 | Hitachi Global Storage Technologies Netherlands Bv | 単極抵抗ランダムアクセスメモリ(rram)デバイス、および垂直スタックアーキテクチャ |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011520265A (ja) * | 2008-05-01 | 2011-07-14 | インターモレキュラー,インク. | 不揮発性抵抗スイッチングメモリ |
JP2009283486A (ja) * | 2008-05-19 | 2009-12-03 | Toshiba Corp | 不揮発性記憶装置及びその製造方法 |
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