WO2009016862A1 - 複合基板および複合基板を用いた機能デバイス、並びに複合基板および機能デバイスの製造方法 - Google Patents

複合基板および複合基板を用いた機能デバイス、並びに複合基板および機能デバイスの製造方法 Download PDF

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Publication number
WO2009016862A1
WO2009016862A1 PCT/JP2008/056214 JP2008056214W WO2009016862A1 WO 2009016862 A1 WO2009016862 A1 WO 2009016862A1 JP 2008056214 W JP2008056214 W JP 2008056214W WO 2009016862 A1 WO2009016862 A1 WO 2009016862A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
composite substrate
producing
same
functional device
Prior art date
Application number
PCT/JP2008/056214
Other languages
English (en)
French (fr)
Inventor
Toshihiko Maeda
Original Assignee
Kyocera Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corporation filed Critical Kyocera Corporation
Priority to JP2009525299A priority Critical patent/JP5274462B2/ja
Publication of WO2009016862A1 publication Critical patent/WO2009016862A1/ja

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00349—Creating layers of material on a substrate
    • B81C1/00357—Creating layers of material on a substrate involving bonding one or several substrates on a non-temporary support, e.g. another substrate
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B37/00—Joining burned ceramic articles with other burned ceramic articles or other articles by heating
    • C04B37/04—Joining burned ceramic articles with other burned ceramic articles or other articles by heating with articles made from glass
    • C04B37/042—Joining burned ceramic articles with other burned ceramic articles or other articles by heating with articles made from glass in a direct manner
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/07—Interconnects
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0174—Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
    • B81C2201/019—Bonding or gluing multiple substrate layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure

Abstract

【課題】接合される２つの基板の間の接合部における強度が強い複合基板を提供する。 【解決手段】複合基板（１）は、機能素子が設けられる第１基板（２）と、第１基板（２）に融着により接合されたガラスセラミック焼結体からなる第２基板（３）とを有する。第１基板（２）と第２基板（３）との界面には、結晶化したガラスが存在する。
PCT/JP2008/056214 2007-07-30 2008-03-28 複合基板および複合基板を用いた機能デバイス、並びに複合基板および機能デバイスの製造方法 WO2009016862A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009525299A JP5274462B2 (ja) 2007-07-30 2008-03-28 複合基板および複合基板を用いた機能デバイス、並びに複合基板および機能デバイスの製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-197323 2007-07-30
JP2007197323 2007-07-30

Publications (1)

Publication Number Publication Date
WO2009016862A1 true WO2009016862A1 (ja) 2009-02-05

Family

ID=40304103

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/056214 WO2009016862A1 (ja) 2007-07-30 2008-03-28 複合基板および複合基板を用いた機能デバイス、並びに複合基板および機能デバイスの製造方法

Country Status (2)

Country Link
JP (1) JP5274462B2 (ja)
WO (1) WO2009016862A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011119615A (ja) * 2009-12-07 2011-06-16 Shinko Electric Ind Co Ltd 配線基板及びその製造方法並びに半導体パッケージ
JP2013147965A (ja) * 2012-01-18 2013-08-01 Murata Mfg Co Ltd 圧電ポンプ

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0957903A (ja) * 1995-08-21 1997-03-04 Toshiba Corp 多層セラミックス基板およびその製造方法
JP2001294489A (ja) * 2000-04-07 2001-10-23 Tokuyama Corp 結晶化ガラスと窒化アルミニウム焼結体との接合体
JP2002234781A (ja) * 2001-02-06 2002-08-23 Murata Mfg Co Ltd 銅メタライズ組成物ならびにそれを用いたセラミック配線基板およびその製造方法
JP2003158375A (ja) * 2001-11-22 2003-05-30 Sumitomo Metal Electronics Devices Inc セラミック多層基板の製造方法及び半導体装置
JP2005129771A (ja) * 2003-10-24 2005-05-19 Kyocera Corp 多層配線基板およびマイクロ化学チップ
JP2005341162A (ja) * 2004-05-26 2005-12-08 Kyocera Corp デバイス装置およびその製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4693381B2 (ja) * 2004-02-24 2011-06-01 京セラ株式会社 配線基板およびその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0957903A (ja) * 1995-08-21 1997-03-04 Toshiba Corp 多層セラミックス基板およびその製造方法
JP2001294489A (ja) * 2000-04-07 2001-10-23 Tokuyama Corp 結晶化ガラスと窒化アルミニウム焼結体との接合体
JP2002234781A (ja) * 2001-02-06 2002-08-23 Murata Mfg Co Ltd 銅メタライズ組成物ならびにそれを用いたセラミック配線基板およびその製造方法
JP2003158375A (ja) * 2001-11-22 2003-05-30 Sumitomo Metal Electronics Devices Inc セラミック多層基板の製造方法及び半導体装置
JP2005129771A (ja) * 2003-10-24 2005-05-19 Kyocera Corp 多層配線基板およびマイクロ化学チップ
JP2005341162A (ja) * 2004-05-26 2005-12-08 Kyocera Corp デバイス装置およびその製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011119615A (ja) * 2009-12-07 2011-06-16 Shinko Electric Ind Co Ltd 配線基板及びその製造方法並びに半導体パッケージ
US8674514B2 (en) 2009-12-07 2014-03-18 Shinko Electric Industries Co., Ltd. Wiring board, manufacturing method of the wiring board, and semiconductor package
JP2013147965A (ja) * 2012-01-18 2013-08-01 Murata Mfg Co Ltd 圧電ポンプ

Also Published As

Publication number Publication date
JPWO2009016862A1 (ja) 2010-10-14
JP5274462B2 (ja) 2013-08-28

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