WO2009006761A1 - Carte de base multicouche et son procédé de fabrication - Google Patents

Carte de base multicouche et son procédé de fabrication Download PDF

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Publication number
WO2009006761A1
WO2009006761A1 PCT/CN2007/002142 CN2007002142W WO2009006761A1 WO 2009006761 A1 WO2009006761 A1 WO 2009006761A1 CN 2007002142 W CN2007002142 W CN 2007002142W WO 2009006761 A1 WO2009006761 A1 WO 2009006761A1
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WIPO (PCT)
Prior art keywords
layer
multilayer substrate
dielectric layer
pad
pad layer
Prior art date
Application number
PCT/CN2007/002142
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English (en)
French (fr)
Inventor
Chih-Kuang Yang
Original Assignee
Princo Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Princo Corp. filed Critical Princo Corp.
Priority to EP12159661.3A priority Critical patent/EP2480058B1/en
Priority to EP07764046A priority patent/EP2190273B1/en
Priority to JP2010515332A priority patent/JP2010532923A/ja
Priority to PCT/CN2007/002142 priority patent/WO2009006761A1/zh
Priority to KR1020107002691A priority patent/KR101314544B1/ko
Publication of WO2009006761A1 publication Critical patent/WO2009006761A1/zh

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13006—Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks

Definitions

  • the invention relates to a multilayer substrate and a method of fabricating the same, and more particularly to a flat multilayer substrate and a method of fabricating the same.
  • BACKGROUND OF THE INVENTION The miniaturization of any type of electronic products today is an inevitable trend. With the semiconductor wafer manufacturing, the integration of today's integrated circuits has been continuously improved, and a multi-layer substrate having a high degree of integration is used. It is an inevitable trend to package wafers or components and to synthesize high-density systems.
  • FIG. 1 is a simplified schematic diagram of a prior art multilayer substrate.
  • the surface of the multilayer substrate that is, the surface to be subsequently encapsulated with a wafer or component, the multilayer substrate includes a pad layer 102, a surface dielectric layer 104, and a solder resist layer 106.
  • Below the pad layer 102 is a metal wiring layer 108 electrically connected thereto.
  • a plurality of layers of a plurality of wiring layers and a plurality of dielectric layers (not shown) of a multilayer substrate are produced by a pressing method, a build-up method, or the like.
  • the thickness of the surface dielectric layer 104 is much larger than the thickness of the pad layer 102 and the metal circuit layer 108.
  • the thickness of the pad layer 102 and the metal circuit layer 108 of the conventional multilayer substrate is only about several ⁇ to several
  • the thickness of the surface dielectric layer 104 may be as thick as several tens of ⁇ m to about 200 ⁇ m. Therefore, due to the presence of the metal wiring layer 108 under the pad layer 102, the surface dielectric layer 104 is formed by using a dielectric layer material of a fixed thickness regardless of whether the multilayer substrate is formed by a pressing method or a build-up method.
  • the pad layer 102 is formed on the surface of the multilayer substrate, the surface unevenness as shown in FIG. 1 is inevitably caused, but the thickness of the surface dielectric layer 104 is about several tens of ⁇ m to 200 ⁇ ⁇ !
  • the thickness of the wiring layer 108 is about several ⁇ to several tens ⁇ .
  • the thickness of the dielectric layer is much thicker than that of the metal layer.
  • the adjustment of the process parameters can be used to make the dielectric layer slightly deformable.
  • the compensation surface is not flat to an acceptable range.
  • the thickness of the pad layer 102, the metal wiring layer 108, and the surface dielectric layer 104 is also reduced based on volume reduction and electrical considerations.
  • the thickness reduction of the pad layer 102 and the metal wiring layer 108 is limited, but the thickness of the surface dielectric layer 104 is greatly reduced.
  • the industry has tried to produce a thickness of up to ' ⁇ m.
  • Left and right surface dielectric layers 104 For example, the thickness of the surface dielectric layer 104 is about ⁇ , and the thickness of the lower metal wiring layer 108 is about several ⁇ to 10 ⁇ .
  • the dimensions of the 108 thickness are close and comparable, and the aforementioned means for deforming the dielectric layer 104 will not be sufficient to compensate for the unevenness of the surface, and inevitably, the problem that the surface of the multilayer substrate is not flat will be highlighted.
  • FIG. 2 is a simplified schematic diagram of a wafer package packaged by a Flip-Chip process according to the prior art.
  • the multilayer substrate manufactured according to the prior art has a dielectric layer 103 and corresponding metal wiring layers 107-1, 107-2, a surface dielectric layer 104 and corresponding metal wiring layers 108-1, 108-2, 108-3.
  • the multilayer substrate has pad layers 102-1, 102-2, 102-3 on the metal wiring layers 108-1, 108-2, 108-3.
  • Flip Chip technology is a flip-chip package with a surface of the wafer 110 facing down through the metal bumps 120-1, 120-2, 120.
  • the multilayer substrate pad layers 102-1, 102-2, 102-3 and the wafer surface contacts 112-1, 112-2, 112-3 (electrodes) must be one-to-one matching, and must Engage accurately.
  • the flip chip packaging technology firstly fixes the multilayer substrate to a package fixture in advance, and aligns the bumps 120-1, 120-2, 120-3 (bump) on the wafer with the pads of the multilayer substrate. After the positions of the layers 102-1, 102-2, and 102-3 are formed, the flip chip is packaged by hot pressing. However, the bumps 120-1, 120-2, 120-3 on the wafer surface contacts 112-1, 112-2, 112-3 1 must be aligned to the pad layers 102-1, 102-2, 102. -3 and join it
  • the surface of the multilayer substrate may have metal wiring layers 107-1, 107-2 under the metal wiring layers 108-1, 108-3, but the metal wiring layer 108-2 However, there is no corresponding metal layer underneath, so the height of the pad layer 102-2 is lower than that of the other pad layers 102-1, 102-3.
  • the bump 120-2 may not be soldered.
  • the pad layer 102-2 is in contact with the wafer surface 1 12-2.
  • the height tolerance value for reference is about ⁇ 10 ⁇ ⁇ .
  • the density of the pad layer per unit area also increases, and the bump height is further reduced, and the height tolerance error is of course smaller. Therefore, the flatness of the surface of the multilayer substrate (i.e., the coplanarity of the pad layer and the dielectric layer) or the flatness of any of the pad layers themselves is even higher.
  • the thickness of the metal circuit layer manufactured by the industry is several tens of ⁇ , or even as small as several ⁇ . Therefore, if the surface of the multilayer substrate is not effectively planarized, the yield and reliability of the flip chip package will be seriously affected. degree.
  • a primary object of the present invention is to provide a multilayer substrate and a method of fabricating the same that can improve the flatness of a pad layer and a dielectric layer of a packaged multilayer substrate, and improve package yield and reliability. Further increase the density of the overall package. '
  • a multilayer substrate of the present invention comprises a surface dielectric layer and at least one pad layer.
  • the surface dielectric layer is located on a surface layer of the multilayer substrate, the pad layer is embedded in the surface dielectric layer, and the surface dielectric layer and the pad layer form a multilayer substrate.
  • the side surface of the underlayer is in close contact with the surface dielectric layer, and a surface of the pad layer and the surface of the surface dielectric layer have a coplanar surface so as to be fixed on the multi-layer substrate on the package jig.
  • the pad layer and the surface dielectric layer have good flatness. When it is used to package with a surface of the device, the yield and reliability of the package can be improved.
  • a method of manufacturing a multilayer substrate of the present invention comprises the steps of: forming at least one pad layer on a flat carrier surface;
  • the package Forming the flat multi-layer substrate for encapsulation with a component surface, that is, packaging a pad layer of the multi-layer substrate and a surface of a package component, wherein the component can be a wafer, the package
  • the type is a flip chip package.
  • a flat carrier surface by using a flat carrier surface, a pad layer and a surface dielectric layer are formed, and the pad is embedded in the surface dielectric layer to have a coplanar surface, so that the surface of the multilayer substrate of the present invention has high flatness.
  • the bump pitch is inevitably reduced, and the bump height needs to be reduced.
  • the multilayer substrate of the present invention can use bumps having smaller bump heights in the subsequent rhombic package or other high-density multi-contact packages, and can also be used as the surface of the multilayer substrate of the present invention.
  • the flatness ensures the parallel distance between the multilayer substrate and the surface of the wafer or component during packaging, which improves the reliability of the package and further increases the density of the overall package.
  • Fig. 2 is a simplified schematic view showing a case where a wafer is packaged by a flip chip process according to the prior art.
  • Figure 3 is a simplified schematic view of the surface of a multilayer substrate of the present invention.
  • 4A through 4C are flow charts of a method of fabricating a multilayer substrate having a flat surface of the present invention.
  • FIG. 5 is a simplified schematic view showing a Flip Chip process using the multilayer substrate having a flat surface of the present invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Please refer to FIG. 3, which is a simplified schematic view of the surface of a multilayer substrate of the present invention.
  • the multilayer substrate of the present invention comprises at least one pad layer 302 and a surface dielectric layer 3.04. Also, the multilayer substrate may further include a solder resist layer 306. Below the pad layer 302 is a metal wiring layer 308 of a multilayer substrate.
  • the pad layer 302 of the present invention is embedded in the surface dielectric layer 304, and the side of the pad layer 302 is in close contact with the surface dielectric layer 304 to enhance the adhesion between the two.
  • the surface of the pad layer 302 has a coplanar surface with the surface of the surface dielectric layer 304, so that the surface of the multilayer substrate of the present invention has high flatness, that is, the surface of the pad layer 302 and the surface of the surface dielectric layer 304. There is no difference between them.
  • FIG. 4A shows a manufacturing method of the present invention.
  • a solder resist layer 401 is formed on the surface of a flat carrier 400
  • a plurality of pad layers including the pad layer 402 are formed.
  • a silicon wafer having a good surface flatness can be used as the carrier 400, and the solder resist layer 401 can be formed by coating, and a solder pad can be formed on the surface of the solder resist layer 401 by etching, electroforming or lithography.
  • FIG. 4B shows that after the pad layer 402 and the like are formed, a surface dielectric layer 404 is formed, the pad layer 402 is covered, and the pad layer 402 or the like is embedded in the surface dielectric layer 404. Further, according to the design of the multi-layer substrate, after the surface dielectric layer 404 is formed, the surface dielectric layer 404 can be opened at a predetermined position of the metal circuit layer, and the metal circuit layer as shown in FIG. 3 can be further formed. 308, and more dielectric layers, metal wiring layers, and the like (only part of the multilayer substrate is formed in FIG. 4B) to complete the in-line structure of the multilayer substrate.
  • solder resist layer 401 is separated from the surface of the carrier 400, and the anti-corridor layer 401 is opened at the position of the pad layer 402 or the like after being turned upside down.
  • the solder resist layer 401 may also be on the surface dielectric layer 404. Together with the embedded; 1: the early pad layer 402 and the like are peeled off from the surface of the carrier plate 400, and then turned upside down, and then on the pad layer 402 and the surface dielectric layer The surface of 404 is formed.
  • the solder resist layer 401, the pad layer 402, and the like and the surface dielectric layer 404 constitute the multilayer substrate of the present invention.
  • the method for separating the multilayer substrate from the surface of the carrier 400 may be, for example, a sacrificial layer method or a plate surface adhesion strength weakening method or the like.
  • the multilayer substrate in order to improve the reliability of a subsequent flip chip package or other high-density multi-contact package, and to increase the density of the overall package, the multilayer substrate must have a relatively flat surface.
  • a multilayer substrate is produced by using a press method and a build-up method, and the surface structure of the multilayer substrate is inevitably affected by the underlying metal wiring layer to cause surface undulation.
  • the present invention utilizes a carrier 400 having a good surface flatness and embedding a pad layer 402 in the surface dielectric layer 404 to fabricate a surface structure of a multi-layer substrate having a flat surface layer, even if the IC package is continuously increased.
  • the thickness of the dielectric layer 404 of the multilayer substrate needs to be reduced based on the volume reduction and electrical considerations, and the multilayer substrate manufactured according to the present invention still has a surface structure with good surface flatness. Therefore, when subsequent flip-chip packages or other high-density multi-contact packages are performed, the yield and reliability of the package can be improved.
  • FIG. 5 a simple schematic diagram of a Flip Chip process using a multilayer substrate having a flat surface of the present invention is illustrated.
  • the flip chip package is to place the surface of the multilayer substrate (the side having the solder resist layer 401) having the pad layer 402 and the surface dielectric layer 404 upward on a package jig (not shown).
  • the surface of the wafer 410 is faced downward, and the bumps 420 and the like are aligned to the positions of the pad layer 402 and the like as shown in the figure, and then bonding is performed by hot pressing, that is, the flip chip package can be completed.
  • An advantage of the present invention is that since a multilayer substrate is fabricated using a carrier 400 having a good surface flatness, it has a flat surface having a higher flatness than the multilayer substrate produced in the prior art shown in FIG.
  • crystal packages or other types of high-density multi-contact packages such as ball grid packages (BGA), planar gate grid arrays (LGA), and wafer level packages (CSP)
  • BGA ball grid packages
  • LGA planar gate grid arrays
  • CSP wafer level packages
  • the multilayer substrate of the present invention By applying the multilayer substrate of the present invention, it is possible to use the bump '420 with a smaller bump height, and also because of the flatness of the multilayer substrate of the present invention, the surface of the multilayer substrate and the component or crystal can be ensured during packaging.
  • the parallel distance between the surfaces of the element 410 is uniform, and when the packaging process is ensured, the bumps 420 and the like are successfully connected to all the solders.
  • the pad layer 402 and the component or wafer surface electrode (contact) 412 can improve the reliability of the package and further increase the density of the overall package.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

多层基板及其制造方法 技术领域 本发明是关于一种多层基板及其制造方法， 尤指一种平坦的多层基板及其 制造方法。 背景技术 现今任何类型电子产品的小型化， 是无可避免的趋势， 随着半导体晶圓制 此， 当今集成电路的积集度已不断地提高时， 使用积集度高的多层基板用以对 晶元或组件进行封装， 整合成高密度系统已为必然的趋势。
请参考图 1，是现有技术的多层基板的简单示意图。 所谓多层基板的表面， 即后续将与一晶元或组件进行封装的表面， 多层基板包含焊垫层 102、 表面介 电层 104以及防焊层 106。 焊垫层 102下方为与其电性连结的金属线路层 108。 根据现有技术多半以压合法、增层法等制作多层基板的数层导线层与数层介电 层 (未显示)。 而表面介电层 104的厚度较焊垫层 102、 金属线路层 108的厚度 要大了许多， 例如现今一般多层基板的焊垫层 102、 金属线路层 108厚度仅约 数个 μ πι至数十 μ πι左右， 而表面介电层 104的厚度可能厚达数十 μ ιη至 200 μ ΐΉ左右。 因此， 由于焊垫层 102下方的金属线路层 108的存在， 无论是以压 合法或者增层法制作多层基板， 均是以一固定厚度的介电层材料， 制作表面介 电层 104， 因此在多层基板表面形成焊垫层 102时， 必会造成如图 1所示表面 的不平坦， 但如前述表面介电层 104的厚度为数十 μ ιη至 200 μ π!左右， '下方 金属线路层 108厚度约数 μ πι至数十 μ πι左右。 介电层厚度远比金属层厚， 在 压合法或者增层法的制程中， 可利用制程参数的调整使介电层些许地变形可以 补偿表面不平坦至可接受的范围。
然而， 由于集成电路的积集度不断地提高， 基于体积缩小与电性的考虑， 焊垫层 102、 金属线路层 108以及表面介电层 104的厚度也随之减小。 为维持 讯号传导的电性考虑， 焊垫层 102、 金属线路层 108厚度的减小幅度有限， 但 表面介电层 104的厚度却大幅地减小，现今业界更尝试制作厚度可达 'ΙΟμ m左 右的表面介电层 104。 如前述表面介电层 104的厚度为 ΙΟμΐΏ左右， 下方金属 线路层 108厚度约数个 μπι至 10 μΐΏ左右。表面介电层 104厚度与金属线路层
108厚度的尺度接近且相当， 则前述使介电层 104变形的手段将不足以补偿表 面的不平坦， 不可避免地， 更将凸显多层基板表面不平坦的问题。
请参考图 2是根据现有技术， 以覆晶封装 (Flip-Chip)制程对晶元进行封装 为例的简单示意图。根据现有技术所制造的多层基板具有介电层 103及对应金 属线路层 107-1、 107-2,表面介电层 104及对应金属线路层 108-1、 108-2、 108-3。
并且多层基板在金属线路层 108- 1、 108-2、 108-3.上具有焊垫层 102-1、 102-2、 102-3。
. 如图 2所示， 现今封装技术是以覆晶封装 (Flip Chip)技术为主流， 覆晶封 装为一种将晶元 110表面朝下， 通过金属凸块 120-1、 120-2、 120-3使晶元表 面接点 112-1、 112-2、 112-3与多层基板的焊垫层 102- 1、 102-2、 102-3接合连 结的技术。 再者， 多层基板焊垫层 102- 1、 102-2、 102-3与晶元表面接点 112-1、 112-2、 112-3 (电极)间， 必须是一对一匹配， 且必须精准地接合。 此覆晶封装 技术是先将该多层基板事先固定于一封装治具上， 对准晶元上的凸块 120-1、 120-2、 120-3 (bump)与多层基板的焊垫层 102-1、 102-2、 102-3的位置后， 再 以热压方式进行覆晶封装。 然而， 必须使晶元表面接点 112-1、 112-2、 112-3 1 上的凸块 120-1、 120-2、 120-3均对准焊垫层 102-1、 102-2、 102-3且与其接合
(Bonding)后，覆晶封装才算成功。但多层基板的表面，可能因电路设计的缘故， 金属线路层 108-1、 108-3下方有金属线路层 107-1、 107-2,但金属线路层 108-2 却无下方对应的金属层， 因而焊垫层 102-2高度比其它焊垫层 102- 1、 102-3高 度低， 当进行前述覆晶封装时， 会导致凸块 120-2未能连结焊垫层 102-2与晶 元表面接点 1 12-2。
然而不仅对覆晶封装而言， 对于其它高密度多接点的封装， 例如： 球栅封 装 (BGA)、 平面闸格数组 (LGA)以及晶圓级封装 (CSP)来说， 只要有一个金属凸 块未能连结焊垫层与晶元或组件表面接点， 封装即告失败。 因此， 对于多层基 板表面、 晶元 1 10表面或组件表面的平坦性要求比以往更高。
一般覆晶封装如使用凸块高度 (bump Height)为 100 μ m的凸块， 可供参考 的高度容许误差值大约在 ± 10 μ ιτ 左右。 而由于集成电路的积集度提高， 单位 面积的焊垫层密度也会提高， 凸块高度 (bump Height)则更进一步缩小， 高度容 许误差值当然就更小。 因此， 更进一步地对多层基板表面的平坦性 (即焊垫层 与介电层的共平面性)， 或对任一焊垫层本身的平坦性要求就更高。 一般业界 所制造的金属线路层厚度多为数十 μ ΐΏ， 甚至小至数个 μ πι， 因此若未能有效 地使多层基板表面平坦化， 将会严重影响覆晶封装的良率与可靠度。
因此， 若能制作一表面平坦的多层基板， 对前述覆晶封装或其它高密度多 接点的封装而言， 能提高封装的可靠度。 并且能更进一步缩小凸块高度 (bump height), 有利于更进一步提高整体封装的密度。 发明内容 本发明的主要目的在于提供一种多层基板及其制造方法， 能改善用于封装 的多层基板的焊垫层与介电层的平坦度， 提高封装的良率与可靠度， 以更进一 步提高整体封装的密度。 '
为达成本发明的前述目的， 本发明的多层基板， 包含一表面介电层以及至 少一焊垫层。表面介电层位于多层基板的一表层，焊垫层则内嵌于表面介电层， 表面介电层与焊垫层形成多层基板。 本发明的多层基板， 烊垫层的侧面与表面介电层密合， 并且， 焊垫层的一 表面与表面介电层的表面具有一共面， 使固定于封装治具上的多层基板的焊垫 层与表面介电层的平坦度良好。 当其用以与一且件表面进行封装时， 能提高封 装的良率与可靠度。
为达成本发明的前述目的， 本发明制造多层基板的方法包含下列步骤： 在一平坦的载板表面形成至少一焊垫层；
形成一表面介电层， 覆盖焊垫层， 使焊垫层内嵌于表面介电层； 以及 将表面介电层以及焊垫层自载板表面分离， 表面介电层与焊垫层形成一平 坦的多层基板。
形成此平坦的多层基板， 是用以与一组件表面进行封装， 即对多层基板的 一焊垫层与一封装组件表面的一接点进行封装， 其中该组件可为一晶元， 该封 装型态则为一覆晶封装。 本发明因利用一平坦的载板表面， 形成焊垫层以及表 面介电层， 使焊垫展内嵌于表面介电层， 具有一共面， 而使本发明的多层基板 表面平坦性高。 随着集成电路的积集度提高， 凸块间距 (bump pitch)必然缩小， 凸块高度 (bump height)亦需随之减小。 因此本发明的多层基板在后续犀晶封装 或其它高密度多接点的封装时， 能使用凸块高度 (bump height)更小的凸块， 同' 时也能由于本发明多层基板的表面平坦性， 可确保封装时多层基板与晶元或组 件表面间的平行距离一致， 而能提高封装的可靠度， 更进一步提高整体封装的 密度。 附图说明 * 图 1是现有技术多层基板的简单示意图。
图 2是根据现有技术， 以覆晶封装 (Flip Chip)制程对晶元进行封装为例的 简单示意图。
图 3是本发明多层基板表面的简单示意图。 图 4A至图 4C是制造本发明表面平坦的多层基板的方法流程图。
图 5是利用本发明表面平坦的多层基板， 进行覆晶封装 (Flip Chip)制程的 简单示意图。 ' 具体实施方式 请参考图 3 , 是本发明多层基板表面的简单示意图。 本发明的多层基板至 少包含一层焊垫层 302以及一层表面介电层 3.04。 并且， 多层基板可更进一步 包含一层防焊层 306。 焊垫层 302下方则为多层基板的金属线路层 308。 本发 明的焊垫层 302是内嵌于表面介电层 304, 并且焊垫层 302侧面与表面介电层 304密合， 能加强两者间的附着强度。 再者， 焊垫层 302的表面与表面介电层 304的表面具有一共面， 使本发明的多层基板表面平坦性高， 也就是， 焊垫层 302的表面与表面介电层 304的表面间无段差。
接着， 请参考图 4A至图 4C , 是本发明制造表面平坦的多层基板的方法流 程图。 首先， 图 4A表示本发明的制造方法在一平坦的载板 400表面先形成一 防焊层 401后， 再形成包含焊垫层 402的若干焊垫层。 例如： 可以一表面平坦 度好的硅晶圓片作为此载板 400， 以涂布方式形成防焊层 401 , 以蚀刻、 电铸 或微影法等方式在防焊层 401表面上形成焊垫层 402。 图 4B表示在形成焊垫 层 402等之后， 再形成一表面介电层 404， 覆盖焊垫层 402等， 使焊垫层 402 等内嵌于表面介电层 404。 再更进一步依多层基板设计所需， 可在形成表面介 电层 404后， 可对表面介电层 404在金属线路层预定位置进行开孔， 更进一步 形成如图 3所示的金属线路层 308， 以及更多的介电层、 金属线路层等 (在图 4B中仅表示制作多层基板的部份)， 以完成多层基板的内联结构。 图 4C表示 将防焊层 401 自载板 400表面分离， 上下翻转后， 再于焊垫层 402等位置对防 悍层 401进行开孔， 或者， 防焊层 401也可在表面介电层 404连同内嵌的； 1：早垫 层 402等自载板 400表面剥离， 上下翻转后， 再于焊垫层 402以及表面介电层 404的表面形成。 这样， 防焊层 401、 焊垫层 402等以及表面介电层 404即构 成本发明的多层基板。 本发明将多层基板自载板 400表面分离的方法可为， 例 如： 牺牲层法或载板表面附着强度弱化法等。
有别于现有技术以压合方式的多层基板制作方法， 为使后续覆晶封装或其 它高密度多接点的封装的可靠度提高， 提高整体封装的密度， 多层基板必须具 有相当的平坦度， 然而， 现有技术使用压合法、 增层法制作多层基板， 多层基 板表面结构均无可避免地受下层金属线路层的影响而产生表层起伏。但本发明 利用一表面平坦度好的载板 400， 内嵌焊垫层 402于表面介电层 404内， 制造 出具有平坦表层的多层基板表面结构， 即使 IC封装的积集度不断地提高， 基 于体积缩小与电性的考虑， 多层基板的介电层 404的厚度需随之减小， 依据本 发明所制造的多层基板仍然具有表面平坦度佳的表面结构。 因此， 当进行后续 覆晶封装或其它高密度多接点的封装时， 更能提高封装的良率与可靠度。
. 请参考图 5， 是绘示利用本发明表面平坦的多层基板， 进行覆晶封装 (Flip Chip)制程为例的简单示意图。覆晶封装是将具有焊垫层 402与表面介电层 404 的多层基板表面（具有防焊层 401的一面）朝上放置固定于一封装治具上（未显 示)。 接着， 将晶元 410表面朝下， 如图所示将凸块 420等对准焊垫层 402等 的位置后， 以热压方式进行接合 (Bonding), 即能完成覆晶封装。
本发明的优点即在于，由于利用一表面平坦度佳的载板 400制作多层基板， 因此与图 2所示的现有技术制作的多层基板相比， 具有平坦度高的表面， 对于 覆晶封装或其它类型高密度多接点的封装， 例如： 球栅封装 (BGA)、 平面闸格 数组 (LGA)以及晶圆级封装 (CSP)而言， 随着集成电路的积集度提高， 因凸块 420的间距 (bump pitch)必然缩小，凸块 420的高度 (bump height)亦需随之减 'J、。 应用本发明的多层基板， 方能使用凸块高度 (bump height)更小的凸块' 420, 同 时也由于本发明多层基板的平坦性， 可确保封装时多层基板表面与组件或晶元 410表面间的平行距离一致， 确保封装制程时， 凸块 420等成功连结所有的焊 垫层 402与组件或晶元表面电极 (接点 )412, 而能提高封装的可靠度， 更进一步 提高整体封装的密度。

Claims

^ 利 要 求
1. 一种多层基 ¾ ， 其特征在于： 其包含一表面介电层以及至少一焊垫层； 表面介电层位于该多层基板的一表层， 焊垫层具有至少一表面及至少一个与 该表面相邻接的倒面， 且该焊垫层是内嵌于该表面介电层， 该表面介电层以 及该焊垫层共同形成该多层基板。
2. 如权利要求 1所述的多层基板， 其特征在于： 该悍垫层的侧面是与该 表面介电层密合。
3. 如权利要求 1所述的多层基板， 其特征在于： 该焊垫层的表面是与该 表面介电层的表面具有一共面。
4. 如权利要求 3所述的多层基板， 其特征在于； 该共面使该多层基板具 有一平坦的表层， 用以与一组件表面进行封装。
5. 如权利要求 4所述的多层基板， 其特征在于： 该组件为晶元。
6. 如权利要求 4所述的多层基板， 其特征在于： 该封装为覆晶封装。
7. 如权利要求 1所述的多层基板， 其特征在于： 该焊垫层的表面是与该 表面介电层的表面间无段差。
8. 如权利要求 1所述的多层基板， 其特征在于： 其更进一步包含一防焊 层， 位于具有该焊垫层以及该表面介电层的该表层上， 该防焊层具有对应该 焊垫层的开孔。
9. 一种制造多层基板的方法， 其特征在于： 该制造方法包含下列步骤： 在一平坦的载板表面形成至少一层焊垫层； 形成一表面介电层， 覆盖该焊垫层， 使该焊垫层内嵌于该表面介电层， 用 以形成该多层基板； 以及 将该多层基板自该载板表面分离。
10. 如权利要求 9所述的方法， 其特征在于： 形成该表面介电层， 覆盖该 焊垫层的步骤更进一步使该焊垫层的侧面与该表面介电层密合。
1 1. 如权利要求 9所述的方法， 其特征在于： 形成该表面介电层， 覆盖该 焊垫层的步骤是使接触该载板表面的该焊垫层的表面与该表面介电层的表面 具有一共面。
12. 如权利要求 9所述的方法， 其特征在于： 在形成该焊垫层的步骤前， 更包含在该载板表面形成一防焊层的步骤， 使该多层基板更进一步包含该防 焊层。
13. 如权利要求 12所述的方法， 其特征在于： 将该多层基板自该载板表 面分离的步骤是将该防焊层自该载板表面分离。
14. 如权利要求 13所述的方法， 其特征在于： 在将该防焊层自该载板表 面分离的步骤后， 更包含在该焊垫层的位置对该防焊层进行开孔的步骤。
15. 如权利要求 9所述的方法， 其特征在于： 在将该多层基板自该载板表 面分离的步骤后， 更包含在该多层基板的表面形成一防焊层的步骤。
16. 如权利要求 9所述的方法， 其特征在于： 在将该多层基板自该载板表 面分离的步骤后， 更包含对该多层基板的该焊垫层与一组件表面的一接点进 行封装的步骤。
17. ·如权利要求 16所述的方法， 其特征在于： 该封装为覆晶封装。
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EP2190273A4 (en) 2011-02-16
EP2480058B1 (en) 2014-07-23
JP2010532923A (ja) 2010-10-14
EP2190273B1 (en) 2012-09-26
KR20100044205A (ko) 2010-04-29
EP2480058A1 (en) 2012-07-25
EP2190273A1 (en) 2010-05-26

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