WO2009001695A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

Info

Publication number
WO2009001695A1
WO2009001695A1 PCT/JP2008/060886 JP2008060886W WO2009001695A1 WO 2009001695 A1 WO2009001695 A1 WO 2009001695A1 JP 2008060886 W JP2008060886 W JP 2008060886W WO 2009001695 A1 WO2009001695 A1 WO 2009001695A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor device
lower electrode
capacity cells
inputted
surrounds
Prior art date
Application number
PCT/JP2008/060886
Other languages
English (en)
French (fr)
Inventor
Fumihiro Inoue
Hitoshi Shima
Original Assignee
Mitsumi Electric Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsumi Electric Co., Ltd. filed Critical Mitsumi Electric Co., Ltd.
Priority to CN200880015540.XA priority Critical patent/CN101681880B/zh
Priority to EP08765596A priority patent/EP2161743A1/en
Priority to US12/598,253 priority patent/US8217493B2/en
Priority to JP2009520465A priority patent/JP4807455B2/ja
Publication of WO2009001695A1 publication Critical patent/WO2009001695A1/ja

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223Capacitor integral with wiring layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5225Shielding layers formed together with wiring layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805Capacitors only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

 信号が入力される下部電極と、該下部電極に対向して配置された上部電極とを有する複数の容量セルが隣接して備えられた半導体装置であって、前記下部電極に接続された配線層が、前記上部電極の各々を囲むシールド配線部を含むことを特徴とする。
PCT/JP2008/060886 2007-06-27 2008-06-13 半導体装置 WO2009001695A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN200880015540.XA CN101681880B (zh) 2007-06-27 2008-06-13 半导体装置
EP08765596A EP2161743A1 (en) 2007-06-27 2008-06-13 Semiconductor device
US12/598,253 US8217493B2 (en) 2007-06-27 2008-06-13 Semiconductor device having capacitor cells
JP2009520465A JP4807455B2 (ja) 2007-06-27 2008-06-13 半導体装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-169242 2007-06-27
JP2007169242 2007-06-27

Publications (1)

Publication Number Publication Date
WO2009001695A1 true WO2009001695A1 (ja) 2008-12-31

Family

ID=40185514

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/060886 WO2009001695A1 (ja) 2007-06-27 2008-06-13 半導体装置

Country Status (5)

Country Link
US (1) US8217493B2 (ja)
EP (1) EP2161743A1 (ja)
JP (1) JP4807455B2 (ja)
CN (1) CN101681880B (ja)
WO (1) WO2009001695A1 (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010137459A1 (ja) * 2009-05-25 2010-12-02 ミツミ電機株式会社 デジタル-アナログ変換器及びこれを用いたアナログ-デジタル変換器
JP2011134774A (ja) * 2009-12-22 2011-07-07 Oki Semiconductor Co Ltd 微小容量素子及びこれを用いた半導体装置
JP2014022414A (ja) * 2012-07-12 2014-02-03 Mitsumi Electric Co Ltd 半導体集積回路
JP2018206883A (ja) * 2017-06-01 2018-12-27 新日本無線株式会社 半導体高周波集積回路

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8766403B2 (en) * 2012-02-06 2014-07-01 Taiwan Semiconductor Manufacturing Co., Ltd. Capacitor arrays for minimizing gradient effects and methods of forming the same
US9471174B2 (en) * 2013-07-01 2016-10-18 Electronics And Telecommunications Research Institute Control apparatus and method of addressing two-dimensional signal
CN106098800B (zh) * 2016-06-23 2019-01-29 中国电子科技集团公司第二十四研究所 电容阵列
US10840232B2 (en) 2018-06-27 2020-11-17 Silicon Laboratories Inc. Shielding in a unit capacitor array
CN112652619B (zh) * 2020-12-22 2022-08-09 长江存储科技有限责任公司 垫片及其制造方法、封装结构及其制造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0590489A (ja) * 1991-09-30 1993-04-09 Fujitsu Ltd 半導体集積回路
JP2003017575A (ja) 2001-07-04 2003-01-17 Matsushita Electric Ind Co Ltd 半導体集積回路装置ならびにd/a変換装置およびa/d変換装置
JP2004221317A (ja) * 2003-01-15 2004-08-05 Renesas Technology Corp 半導体装置
JP2006115455A (ja) * 2004-09-14 2006-04-27 Denso Corp 伝送装置
JP2006303220A (ja) * 2005-04-21 2006-11-02 Nec Electronics Corp 半導体装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6066537A (en) * 1998-02-02 2000-05-23 Tritech Microelectronics, Ltd. Method for fabricating a shielded multilevel integrated circuit capacitor
JP2001284526A (ja) 2000-03-28 2001-10-12 Nec Yamagata Ltd 半導体集積回路用mim容量装置
US7248061B2 (en) 2004-09-14 2007-07-24 Denso Corporation Transmission device for transmitting a signal through a transmission line between circuits blocks having different power supply systems

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0590489A (ja) * 1991-09-30 1993-04-09 Fujitsu Ltd 半導体集積回路
JP2003017575A (ja) 2001-07-04 2003-01-17 Matsushita Electric Ind Co Ltd 半導体集積回路装置ならびにd/a変換装置およびa/d変換装置
JP2004221317A (ja) * 2003-01-15 2004-08-05 Renesas Technology Corp 半導体装置
JP2006115455A (ja) * 2004-09-14 2006-04-27 Denso Corp 伝送装置
JP2006303220A (ja) * 2005-04-21 2006-11-02 Nec Electronics Corp 半導体装置

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010137459A1 (ja) * 2009-05-25 2010-12-02 ミツミ電機株式会社 デジタル-アナログ変換器及びこれを用いたアナログ-デジタル変換器
JP2011134774A (ja) * 2009-12-22 2011-07-07 Oki Semiconductor Co Ltd 微小容量素子及びこれを用いた半導体装置
US8692355B2 (en) 2009-12-22 2014-04-08 Oki Semiconductor Co., Ltd. Minute capacitance element and semiconductor device using the same
JP2014022414A (ja) * 2012-07-12 2014-02-03 Mitsumi Electric Co Ltd 半導体集積回路
JP2018206883A (ja) * 2017-06-01 2018-12-27 新日本無線株式会社 半導体高周波集積回路

Also Published As

Publication number Publication date
JP4807455B2 (ja) 2011-11-02
US8217493B2 (en) 2012-07-10
CN101681880A (zh) 2010-03-24
CN101681880B (zh) 2011-06-15
EP2161743A1 (en) 2010-03-10
JPWO2009001695A1 (ja) 2010-08-26
US20100117193A1 (en) 2010-05-13

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