WO2008155805A1 - キャッシュメモリ装置、演算処理装置及びその制御方法 - Google Patents

キャッシュメモリ装置、演算処理装置及びその制御方法 Download PDF

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Publication number
WO2008155805A1
WO2008155805A1 PCT/JP2007/000663 JP2007000663W WO2008155805A1 WO 2008155805 A1 WO2008155805 A1 WO 2008155805A1 JP 2007000663 W JP2007000663 W JP 2007000663W WO 2008155805 A1 WO2008155805 A1 WO 2008155805A1
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WO
WIPO (PCT)
Prior art keywords
way
alternating
register
data
address
Prior art date
Application number
PCT/JP2007/000663
Other languages
English (en)
French (fr)
Inventor
Hiroyuki Imai
Naohiro Kiyota
Tsuyoshi Motokurumada
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2007/000663 priority Critical patent/WO2008155805A1/ja
Priority to EP07790189.0A priority patent/EP2159705B1/en
Priority to KR1020097025901A priority patent/KR101077513B1/ko
Priority to JP2009520146A priority patent/JP4595029B2/ja
Priority to CN200780053356XA priority patent/CN101689141B/zh
Publication of WO2008155805A1 publication Critical patent/WO2008155805A1/ja
Priority to US12/636,619 priority patent/US8700947B2/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computer Security & Cryptography (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

　　複数のキャッシュラインを有するウェイを複数備えるデータ保持部と、データ保持部が有するキャッシュラインの１ライン分又はキャッシュラインの一部のデータを保持する交替データレジスタと、データ保持部において故障が発生した故障キャッシュライン及び故障キャッシュライン内の故障発生部を指し示すインデックスアドレスを保持する交替アドレスレジスタと、故障発生部を含むウェイの情報を保持する交替ウェイレジスタと、データ保持部にアクセスを行う場合に、アクセスに用いられるインデックスアドレスと交替アドレスレジスタが保持するインデックスアドレスを比較するアドレスマッチ回路と、データ保持部にアクセスを行う場合に、アクセスに用いられるウェイ情報と交替ウェイレジスタの保持するウェイ情報を比較するウェイマッチ回路と、を備えるようにキャッシュメモリ装置を構成した。
PCT/JP2007/000663 2007-06-20 2007-06-20 キャッシュメモリ装置、演算処理装置及びその制御方法 WO2008155805A1 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
PCT/JP2007/000663 WO2008155805A1 (ja) 2007-06-20 2007-06-20 キャッシュメモリ装置、演算処理装置及びその制御方法
EP07790189.0A EP2159705B1 (en) 2007-06-20 2007-06-20 Cache memory device, arithmetic processing unit, and its control method
KR1020097025901A KR101077513B1 (ko) 2007-06-20 2007-06-20 캐시 메모리 장치, 연산 처리 장치 및 그 제어 방법
JP2009520146A JP4595029B2 (ja) 2007-06-20 2007-06-20 キャッシュメモリ装置、演算処理装置及びその制御方法
CN200780053356XA CN101689141B (zh) 2007-06-20 2007-06-20 高速缓存装置、运算处理装置及其控制方法
US12/636,619 US8700947B2 (en) 2007-06-20 2009-12-11 Cache memory apparatus, execution processing apparatus and control method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/000663 WO2008155805A1 (ja) 2007-06-20 2007-06-20 キャッシュメモリ装置、演算処理装置及びその制御方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/636,619 Continuation US8700947B2 (en) 2007-06-20 2009-12-11 Cache memory apparatus, execution processing apparatus and control method thereof

Publications (1)

Publication Number Publication Date
WO2008155805A1 true WO2008155805A1 (ja) 2008-12-24

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PCT/JP2007/000663 WO2008155805A1 (ja) 2007-06-20 2007-06-20 キャッシュメモリ装置、演算処理装置及びその制御方法

Country Status (6)

Country Link
US (1) US8700947B2 (ja)
EP (1) EP2159705B1 (ja)
JP (1) JP4595029B2 (ja)
KR (1) KR101077513B1 (ja)
CN (1) CN101689141B (ja)
WO (1) WO2008155805A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017504096A (ja) * 2013-11-25 2017-02-02 クアルコム，インコーポレイテッド ビット復元システム
JP2020003959A (ja) * 2018-06-26 2020-01-09 富士通株式会社 情報処理装置、演算処理装置及び情報処理装置の制御方法

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011065503A (ja) * 2009-09-18 2011-03-31 Renesas Electronics Corp キャッシュメモリシステム及びキャッシュメモリのｗａｙ予測の制御方法
JP5650441B2 (ja) * 2010-06-07 2015-01-07 キヤノン株式会社 演算装置、キャッシュ装置、その制御方法及びコンピュータプログラム
WO2012137339A1 (ja) * 2011-04-07 2012-10-11 富士通株式会社 情報処理装置、並列計算機システムおよび演算処理装置の制御方法
JP2013061887A (ja) 2011-09-14 2013-04-04 Fujitsu Ltd 故障位置判定回路、記憶装置、および情報処理装置
US8839025B2 (en) 2011-09-30 2014-09-16 Oracle International Corporation Systems and methods for retiring and unretiring cache lines
JP5565425B2 (ja) * 2012-02-29 2014-08-06 富士通株式会社 演算装置、情報処理装置および演算方法
US9075727B2 (en) * 2012-06-14 2015-07-07 International Business Machines Corporation Reducing penalties for cache accessing operations
US9135126B2 (en) * 2013-02-07 2015-09-15 International Business Machines Corporation Multi-core re-initialization failure control system
US9043668B2 (en) 2013-02-08 2015-05-26 Seagate Technology Llc Using ECC data for write deduplication processing
JP2016081169A (ja) * 2014-10-14 2016-05-16 富士通株式会社 情報処理装置、データ処理システム、データ処理管理プログラム、及び、データ処理管理方法
US9703661B2 (en) 2015-02-05 2017-07-11 International Business Machines Corporation Eliminate corrupted portions of cache during runtime
US10185619B2 (en) * 2016-03-31 2019-01-22 Intel Corporation Handling of error prone cache line slots of memory side cache of multi-level system memory
JP6770230B2 (ja) * 2016-09-30 2020-10-14 富士通株式会社 演算処理装置、情報処理装置及び演算処理装置の制御方法
US10437729B2 (en) 2017-04-19 2019-10-08 International Business Machines Corporation Non-disruptive clearing of varying address ranges from cache
JP6947974B2 (ja) 2017-09-13 2021-10-13 富士通株式会社 演算処理装置及び演算処理装置の制御方法
KR20200081045A (ko) * 2018-12-27 2020-07-07 삼성전자주식회사 3차원 적층 메모리 장치 및 그 동작 방법
US11042483B2 (en) 2019-04-26 2021-06-22 International Business Machines Corporation Efficient eviction of whole set associated cache or selected range of addresses
CN112289353B (zh) * 2019-07-25 2024-03-12 上海磁宇信息科技有限公司 一种优化的具有ecc功能的mram系统及其操作方法
US11966328B2 (en) 2020-12-18 2024-04-23 Advanced Micro Devices, Inc. Near-memory determination of registers

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5215236A (en) 1975-07-25 1977-02-04 Nec Corp Error block unit
JPS60123949A (ja) * 1983-12-09 1985-07-02 Hitachi Ltd 記憶装置制御方式
JP2001147859A (ja) * 1999-09-08 2001-05-29 Fujitsu Ltd キャッシュメモリ装置およびキャッシュメモリ制御プログラムを記録したコンピュータ読み取り可能な記録媒体
US6289438B1 (en) 1998-07-29 2001-09-11 Kabushiki Kaisha Toshiba Microprocessor cache redundancy scheme using store buffer
US20030191885A1 (en) 2002-04-09 2003-10-09 Chandra Thimmanagari On-chip cache redundancy technique
JP3483296B2 (ja) 1994-04-28 2004-01-06 富士通株式会社 情報処理装置
US20040025095A1 (en) 2002-07-31 2004-02-05 Mahadevamurty Nemani Apparatus and methods for providing enhanced redundancy for an on-die cache
US6918071B2 (en) 2001-04-20 2005-07-12 Sun Microsystems, Inc. Yield improvement through probe-based cache size reduction
JP2006099902A (ja) 2004-09-30 2006-04-13 Konica Minolta Opto Inc 光記録／再生用光学装置
JP2006099821A (ja) 2004-09-28 2006-04-13 Mitsubishi Materials Corp 光記録媒体用反射膜および半透明反射膜並びにこれら反射膜を形成するためのＡｇ合金スパッタリングターゲット
US20060080572A1 (en) 2004-09-30 2006-04-13 Fong John Y Set associative repair cache systems and methods
JP2006343851A (ja) * 2005-06-07 2006-12-21 Toshiba Corp キャッシュメモリおよびマイクロプロセッサ

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01292454A (ja) * 1988-05-19 1989-11-24 Mitsubishi Electric Corp キャッシュ制御方式
JPH0719228B2 (ja) * 1988-09-30 1995-03-06 株式会社日立製作所 バッファメモリ装置
JPH04239936A (ja) * 1991-01-24 1992-08-27 Nec Corp キャッシュ制御装置
JP2997370B2 (ja) * 1992-10-14 2000-01-11 三菱電機株式会社 キャッシュメモリ
EP0721621B1 (en) * 1993-09-30 2002-01-30 Apple Computer, Inc. System for decentralized backing store control of virtual memory in a computer
US6006311A (en) * 1997-04-14 1999-12-21 Internatinal Business Machines Corporation Dynamic updating of repair mask used for cache defect avoidance
US6223248B1 (en) * 1997-04-29 2001-04-24 Texas Instruments Incorporated Circuits systems and methods for re-mapping memory row redundancy during two cycle cache access
US6029237A (en) * 1997-10-08 2000-02-22 Dell Usa, L.P. Method for simulating the presence of a diskette drive in a NetPC computer that contains only a hard disk drive
JPH11282764A (ja) * 1998-03-30 1999-10-15 Oki Electric Ind Co Ltd メモリエラー箇所切り離し回路
US6708294B1 (en) * 1999-09-08 2004-03-16 Fujitsu Limited Cache memory apparatus and computer readable recording medium on which a program for controlling a cache memory is recorded
US6339813B1 (en) * 2000-01-07 2002-01-15 International Business Machines Corporation Memory system for permitting simultaneous processor access to a cache line and sub-cache line sectors fill and writeback to a system memory
US6904552B2 (en) * 2001-03-15 2005-06-07 Micron Technolgy, Inc. Circuit and method for test and repair
JP2003203010A (ja) * 2002-01-07 2003-07-18 Nec Computertechno Ltd Ｌ２キャッシュメモリ
US7240277B2 (en) * 2003-09-26 2007-07-03 Texas Instruments Incorporated Memory error detection reporting
JP4239936B2 (ja) 2004-09-16 2009-03-18 富士電機リテイルシステムズ株式会社 硬貨処理装置および金銭処理装置
JP4791525B2 (ja) 2006-02-14 2011-10-12 富士通株式会社 読み出し処理装置および読み出し方法
EP1990727A4 (en) 2006-02-27 2009-08-05 Fujitsu Ltd CACHE CONTROL DEVICE AND CACHE CONTROL PROGRAM
JP5010271B2 (ja) 2006-12-27 2012-08-29 富士通株式会社 エラー訂正コード生成方法、およびメモリ制御装置
JP5215236B2 (ja) 2009-05-21 2013-06-19 株式会社デンソー 車線境界線種別推定装置及び車線境界線種別推定方法

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5215236A (en) 1975-07-25 1977-02-04 Nec Corp Error block unit
JPS60123949A (ja) * 1983-12-09 1985-07-02 Hitachi Ltd 記憶装置制御方式
JP3483296B2 (ja) 1994-04-28 2004-01-06 富士通株式会社 情報処理装置
US6289438B1 (en) 1998-07-29 2001-09-11 Kabushiki Kaisha Toshiba Microprocessor cache redundancy scheme using store buffer
JP2001147859A (ja) * 1999-09-08 2001-05-29 Fujitsu Ltd キャッシュメモリ装置およびキャッシュメモリ制御プログラムを記録したコンピュータ読み取り可能な記録媒体
US6918071B2 (en) 2001-04-20 2005-07-12 Sun Microsystems, Inc. Yield improvement through probe-based cache size reduction
US20030191885A1 (en) 2002-04-09 2003-10-09 Chandra Thimmanagari On-chip cache redundancy technique
US20040025095A1 (en) 2002-07-31 2004-02-05 Mahadevamurty Nemani Apparatus and methods for providing enhanced redundancy for an on-die cache
JP2006099821A (ja) 2004-09-28 2006-04-13 Mitsubishi Materials Corp 光記録媒体用反射膜および半透明反射膜並びにこれら反射膜を形成するためのＡｇ合金スパッタリングターゲット
JP2006099902A (ja) 2004-09-30 2006-04-13 Konica Minolta Opto Inc 光記録／再生用光学装置
US20060080572A1 (en) 2004-09-30 2006-04-13 Fong John Y Set associative repair cache systems and methods
JP2006343851A (ja) * 2005-06-07 2006-12-21 Toshiba Corp キャッシュメモリおよびマイクロプロセッサ

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
J. Y. FONG ET AL.: "19th IEEE International Symposium on DFT in VLSI Systems", article "Nonvolatile Repair Caches Repair Embedded SRAM and New Nonvolatile Memories"
See also references of EP2159705A4

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017504096A (ja) * 2013-11-25 2017-02-02 クアルコム，インコーポレイテッド ビット復元システム
JP2020003959A (ja) * 2018-06-26 2020-01-09 富士通株式会社 情報処理装置、演算処理装置及び情報処理装置の制御方法
JP7139719B2 (ja) 2018-06-26 2022-09-21 富士通株式会社 情報処理装置、演算処理装置及び情報処理装置の制御方法

Also Published As

Publication number Publication date
JP4595029B2 (ja) 2010-12-08
JPWO2008155805A1 (ja) 2010-08-26
CN101689141A (zh) 2010-03-31
EP2159705B1 (en) 2016-03-02
EP2159705A4 (en) 2012-07-25
US20100088550A1 (en) 2010-04-08
EP2159705A1 (en) 2010-03-03
KR20100006588A (ko) 2010-01-19
KR101077513B1 (ko) 2011-10-28
US8700947B2 (en) 2014-04-15
CN101689141B (zh) 2012-10-17

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