ATE509317T1 - Verfahren und vorrichtung zur bereitstellung von unabhängigem logischem adressenraum und zugangsverwaltung - Google Patents

Verfahren und vorrichtung zur bereitstellung von unabhängigem logischem adressenraum und zugangsverwaltung

Info

Publication number
ATE509317T1
ATE509317T1 AT07713493T AT07713493T ATE509317T1 AT E509317 T1 ATE509317 T1 AT E509317T1 AT 07713493 T AT07713493 T AT 07713493T AT 07713493 T AT07713493 T AT 07713493T AT E509317 T1 ATE509317 T1 AT E509317T1
Authority
AT
Austria
Prior art keywords
access
logical address
requesting entity
address space
access management
Prior art date
Application number
AT07713493T
Other languages
English (en)
Inventor
Katsushi Otsuka
Original Assignee
Sony Computer Entertainment Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Computer Entertainment Inc filed Critical Sony Computer Entertainment Inc
Application granted granted Critical
Publication of ATE509317T1 publication Critical patent/ATE509317T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights
    • G06F12/1483—Protection against unauthorised use of memory or access to memory by checking the subject access rights using an access-table, e.g. matrix or list
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/145—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Mathematical Physics (AREA)
  • Storage Device Security (AREA)
  • Bus Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AT07713493T 2006-02-22 2007-02-21 Verfahren und vorrichtung zur bereitstellung von unabhängigem logischem adressenraum und zugangsverwaltung ATE509317T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US77582906P 2006-02-22 2006-02-22
US11/550,096 US7610464B2 (en) 2006-02-22 2006-10-17 Methods and apparatus for providing independent logical address space and access management
PCT/JP2007/000111 WO2007097123A1 (en) 2006-02-22 2007-02-21 Methods and apparatus for providing independent logical address space and access management

Publications (1)

Publication Number Publication Date
ATE509317T1 true ATE509317T1 (de) 2011-05-15

Family

ID=37962683

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07713493T ATE509317T1 (de) 2006-02-22 2007-02-21 Verfahren und vorrichtung zur bereitstellung von unabhängigem logischem adressenraum und zugangsverwaltung

Country Status (5)

Country Link
US (2) US7610464B2 (de)
EP (1) EP1987434B1 (de)
JP (3) JP4756562B2 (de)
AT (1) ATE509317T1 (de)
WO (1) WO2007097123A1 (de)

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US8560782B2 (en) * 2009-09-21 2013-10-15 Freescale Semiconductor, Inc. Method and apparatus for determining access permissions in a partitioned data processing system
US20110153969A1 (en) * 2009-12-18 2011-06-23 William Petrick Device and method to control communications between and access to computer networks, systems or devices
CN102110072B (zh) * 2009-12-29 2013-06-05 中兴通讯股份有限公司 一种多处理器完全互访的方法及系统
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CN102597972B (zh) * 2010-05-24 2016-06-08 松下电器（美国）知识产权公司 虚拟计算机系统、区域管理方法
TWI446351B (zh) * 2010-05-27 2014-07-21 Wistron Corp 資料寫入方法與電腦系統
US8285920B2 (en) * 2010-07-09 2012-10-09 Nokia Corporation Memory device with dynamic controllable physical logical mapping table loading
US8635385B2 (en) * 2010-07-16 2014-01-21 Advanced Micro Devices, Inc. Mechanism to handle peripheral page faults
US8176218B2 (en) 2010-08-11 2012-05-08 Lsi Corporation Apparatus and methods for real-time routing of received commands in a split-path architecture storage controller
US8261003B2 (en) 2010-08-11 2012-09-04 Lsi Corporation Apparatus and methods for managing expanded capacity of virtual volumes in a storage system
US8255634B2 (en) * 2010-08-11 2012-08-28 Lsi Corporation Apparatus and methods for look-ahead virtual volume meta-data processing in a storage controller
GB2484717B (en) * 2010-10-21 2018-06-13 Advanced Risc Mach Ltd Security provision for a subject image displayed in a non-secure domain
US9229884B2 (en) * 2012-04-30 2016-01-05 Freescale Semiconductor, Inc. Virtualized instruction extensions for system partitioning
US9152587B2 (en) 2012-05-31 2015-10-06 Freescale Semiconductor, Inc. Virtualized interrupt delay mechanism
US9442870B2 (en) 2012-08-09 2016-09-13 Freescale Semiconductor, Inc. Interrupt priority management using partition-based priority blocking processor registers
US9436626B2 (en) 2012-08-09 2016-09-06 Freescale Semiconductor, Inc. Processor interrupt interface with interrupt partitioning and virtualization enhancements
US8931108B2 (en) * 2013-02-18 2015-01-06 Qualcomm Incorporated Hardware enforced content protection for graphics processing units
US10049216B2 (en) * 2014-02-06 2018-08-14 Intel Corporation Media protection policy enforcement for multiple-operating-system environments
KR102214511B1 (ko) * 2014-02-17 2021-02-09 삼성전자 주식회사 두 단계로 페이지를 필터링하는 데이터 저장 장치, 이를 포함하는 시스템, 및 상기 데이터 저장 장치의 동작 방법
WO2015174285A1 (ja) * 2014-05-16 2015-11-19 ソニー株式会社 情報処理装置、情報処理方法、および電子機器
US9372635B2 (en) * 2014-06-03 2016-06-21 Ati Technologies Ulc Methods and apparatus for dividing secondary storage
US9569119B2 (en) * 2014-09-04 2017-02-14 National Instruments Corporation Self-addressing memory
US9767320B2 (en) 2015-08-07 2017-09-19 Qualcomm Incorporated Hardware enforced content protection for graphics processing units
US10102391B2 (en) 2015-08-07 2018-10-16 Qualcomm Incorporated Hardware enforced content protection for graphics processing units
JP6504984B2 (ja) * 2015-09-28 2019-04-24 ルネサスエレクトロニクス株式会社 データ処理装置
JP2017215802A (ja) * 2016-05-31 2017-12-07 株式会社リコー 制御装置及び制御方法
US10970226B2 (en) * 2017-10-06 2021-04-06 Silicon Motion, Inc. Method for performing access management in a memory device, associated memory device and controller thereof, and associated electronic device
JP6992616B2 (ja) * 2018-03-13 2022-01-13 日本電気株式会社 データ転送装置、データ転送方法、プログラム
JP7003752B2 (ja) * 2018-03-13 2022-01-21 日本電気株式会社 データ転送装置、データ転送方法、プログラム

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US7822941B2 (en) * 2006-06-05 2010-10-26 Oracle America, Inc. Function-based virtual-to-physical address translation

Also Published As

Publication number Publication date
US20070208885A1 (en) 2007-09-06
JP4756562B2 (ja) 2011-08-24
US20100211752A1 (en) 2010-08-19
EP1987434A1 (de) 2008-11-05
JP5073080B2 (ja) 2012-11-14
JP2009523269A (ja) 2009-06-18
EP1987434B1 (de) 2011-05-11
JP2011181089A (ja) 2011-09-15
JP4975175B2 (ja) 2012-07-11
JP2011204247A (ja) 2011-10-13
US8533426B2 (en) 2013-09-10
US7610464B2 (en) 2009-10-27
WO2007097123A1 (en) 2007-08-30

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