WO2008149751A1 - 半導体装置の製造方法、半導体製造装置及び記憶媒体 - Google Patents
半導体装置の製造方法、半導体製造装置及び記憶媒体 Download PDFInfo
- Publication number
- WO2008149751A1 WO2008149751A1 PCT/JP2008/059828 JP2008059828W WO2008149751A1 WO 2008149751 A1 WO2008149751 A1 WO 2008149751A1 JP 2008059828 W JP2008059828 W JP 2008059828W WO 2008149751 A1 WO2008149751 A1 WO 2008149751A1
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- Prior art keywords
- copper
- seed layer
- substrate
- concave part
- self
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/425—Barrier, adhesion or liner layers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/047—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/052—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by treatments not introducing additional elements therein
- H10W20/0523—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by treatments not introducing additional elements therein by irradiating with ultraviolet or particle radiation
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/052—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by treatments not introducing additional elements therein
- H10W20/0526—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by treatments not introducing additional elements therein by thermal treatment thereof
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/055—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by formation methods other than physical vapour deposition [PVD], chemical vapour deposition [CVD] or liquid deposition
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/055—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by formation methods other than physical vapour deposition [PVD], chemical vapour deposition [CVD] or liquid deposition
- H10W20/0552—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by formation methods other than physical vapour deposition [PVD], chemical vapour deposition [CVD] or liquid deposition by diffusing metallic dopants to react with dielectrics
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
- H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
酸化物となり銅の拡散防止機能を発揮する自己形成バリア用の金属又はこの金属と銅との合金からなるシード層を、基板表面の層間絶縁膜上及びその凹部の内壁面に沿って形成する工程と、シード層を水素の活性種を用いて還元する工程と、シード層の還元後、凹部に銅を埋め込む工程と、銅の埋め込み後、シード層を構成する自己形成バリア用の金属を酸化してバリア層を形成すると共に余剰の自己形成バリア用の金属を銅の表面に析出させるために酸素雰囲気において基板を加熱処理する工程とを含み、シード層還元後、凹部に銅を埋め込むまでの間の基板が置かれる雰囲気を真空雰囲気又は不活性ガス雰囲気とする。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007-143991 | 2007-05-30 | ||
| JP2007143991A JP2008300568A (ja) | 2007-05-30 | 2007-05-30 | 半導体装置の製造方法、半導体製造装置及び記憶媒体 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2008149751A1 true WO2008149751A1 (ja) | 2008-12-11 |
Family
ID=40093570
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2008/059828 Ceased WO2008149751A1 (ja) | 2007-05-30 | 2008-05-28 | 半導体装置の製造方法、半導体製造装置及び記憶媒体 |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2008300568A (ja) |
| WO (1) | WO2008149751A1 (ja) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103730410A (zh) * | 2012-10-10 | 2014-04-16 | 格罗方德半导体公司 | 于通孔底部具有自行成阻障层的半导体装置 |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5522979B2 (ja) * | 2009-06-16 | 2014-06-18 | 国立大学法人東北大学 | 成膜方法及び処理システム |
| JP5307072B2 (ja) | 2009-06-17 | 2013-10-02 | 東京エレクトロン株式会社 | 金属酸化物膜の形成方法及び成膜装置 |
| KR101659469B1 (ko) | 2011-06-16 | 2016-09-23 | 도쿄엘렉트론가부시키가이샤 | 반도체 장치의 제조 방법, 반도체 장치, 반도체 장치의 제조 장치 및 기억 매체 |
| WO2014013941A1 (ja) | 2012-07-18 | 2014-01-23 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
| JP6268008B2 (ja) | 2014-03-17 | 2018-01-24 | 東京エレクトロン株式会社 | Cu配線の製造方法 |
| JP6584326B2 (ja) | 2015-03-16 | 2019-10-02 | 東京エレクトロン株式会社 | Cu配線の製造方法 |
| US10096548B2 (en) | 2015-03-16 | 2018-10-09 | Tokyo Electron Limited | Method of manufacturing Cu wiring |
| JP2017050304A (ja) | 2015-08-31 | 2017-03-09 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
| JP2019192892A (ja) | 2018-04-18 | 2019-10-31 | 東京エレクトロン株式会社 | 処理システムおよび処理方法 |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05102318A (ja) * | 1991-04-05 | 1993-04-23 | Internatl Business Mach Corp <Ibm> | 銅合金導電プラグ形成方法及び装置 |
| JP2000208627A (ja) * | 1999-01-19 | 2000-07-28 | Hitachi Ltd | 半導体装置の製造方法 |
| JP2001035850A (ja) * | 1999-07-19 | 2001-02-09 | Ebara Corp | 半導体装置及びその製造方法 |
| JP2005277390A (ja) * | 2004-02-27 | 2005-10-06 | Handotai Rikougaku Kenkyu Center:Kk | 半導体装置及びその製造方法 |
| JP2006278587A (ja) * | 2005-03-29 | 2006-10-12 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法および製造装置 |
-
2007
- 2007-05-30 JP JP2007143991A patent/JP2008300568A/ja active Pending
-
2008
- 2008-05-28 WO PCT/JP2008/059828 patent/WO2008149751A1/ja not_active Ceased
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05102318A (ja) * | 1991-04-05 | 1993-04-23 | Internatl Business Mach Corp <Ibm> | 銅合金導電プラグ形成方法及び装置 |
| JP2000208627A (ja) * | 1999-01-19 | 2000-07-28 | Hitachi Ltd | 半導体装置の製造方法 |
| JP2001035850A (ja) * | 1999-07-19 | 2001-02-09 | Ebara Corp | 半導体装置及びその製造方法 |
| JP2005277390A (ja) * | 2004-02-27 | 2005-10-06 | Handotai Rikougaku Kenkyu Center:Kk | 半導体装置及びその製造方法 |
| JP2006278587A (ja) * | 2005-03-29 | 2006-10-12 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法および製造装置 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103730410A (zh) * | 2012-10-10 | 2014-04-16 | 格罗方德半导体公司 | 于通孔底部具有自行成阻障层的半导体装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2008300568A (ja) | 2008-12-11 |
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