WO2008146603A1 - 半導体装置およびその製造方法、ならびにディスプレイ装置およびその製造方法 - Google Patents

半導体装置およびその製造方法、ならびにディスプレイ装置およびその製造方法 Download PDF

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Publication number
WO2008146603A1
WO2008146603A1 PCT/JP2008/058841 JP2008058841W WO2008146603A1 WO 2008146603 A1 WO2008146603 A1 WO 2008146603A1 JP 2008058841 W JP2008058841 W JP 2008058841W WO 2008146603 A1 WO2008146603 A1 WO 2008146603A1
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WIPO (PCT)
Prior art keywords
semiconductor
terminal portion
semiconductor device
insulating substrate
manufacturing
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PCT/JP2008/058841
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English (en)
French (fr)
Inventor
Katsuhiro Ryutani
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Shindo Company, Ltd.
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Filing date
Publication date
Application filed by Shindo Company, Ltd. filed Critical Shindo Company, Ltd.
Priority to US12/600,585 priority Critical patent/US20100148207A1/en
Priority to EP08752712A priority patent/EP2151862A1/en
Priority to CN2008800178721A priority patent/CN101689535B/zh
Publication of WO2008146603A1 publication Critical patent/WO2008146603A1/ja

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    • H01L23/4985—Flexible insulating substrates
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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Abstract

　半導体の放熱効率のよい半導体装置を提供する。および、そのような半導体装置を用いたディスプレイ装置および半導体装置の製造方法を提供する。 　半導体接続用端子部を設けるとともにその半導体接続用端子部を挟んで第１の外部接続用端子部と第２の外部接続用端子部とを設ける導電パターンを、可撓性を有する絶縁基材の表面に形成するフレキシブルプリント配線板に、前記導電パターンの半導体接続用端子部に接続して半導体を搭載する。そのような半導体装置において、半導体のまわりを一部残してその半導体を取り囲むように、絶縁基材にスリットを形成して半導体保持部位を設けてなる。そして、その半導体保持部位を除いて絶縁基材を、表面を内側として折り返し、第１の外部接続用端子部および第２の外部接続用端子部を各々他の部品に接続するとき、搭載された半導体を絶縁基材の裏面から外側に突出させるように、スリットが形成されている。
PCT/JP2008/058841 2007-05-30 2008-05-14 半導体装置およびその製造方法、ならびにディスプレイ装置およびその製造方法 WO2008146603A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US12/600,585 US20100148207A1 (en) 2007-05-30 2008-05-14 Semiconductor device, and manufacturing method thereof, and display device and its manufacturing method
EP08752712A EP2151862A1 (en) 2007-05-30 2008-05-14 Semiconductor device and its manufacturing method, and display and its manufacturing method
CN2008800178721A CN101689535B (zh) 2007-05-30 2008-05-14 半导体装置及其制造方法，以及显示装置及其制造方法

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007142919 2007-05-30
JP2007-142919 2007-05-30
JP2007243306A JP4109707B1 (ja) 2007-05-30 2007-09-20 半導体装置およびその製造方法、ならびにディスプレイ装置およびその製造方法
JP2007-243306 2007-09-20

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WO2008146603A1 true WO2008146603A1 (ja) 2008-12-04

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Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5413971B2 (ja) * 2007-07-19 2014-02-12 日本電気株式会社 電子部品実装装置及びその製造方法
CN102422338B (zh) 2009-05-02 2015-04-01 株式会社半导体能源研究所 显示设备
JP5466966B2 (ja) * 2010-02-16 2014-04-09 新藤電子工業株式会社 配線板、半導体装置、半導体モジュール及びディスプレイ装置
JP2011199090A (ja) * 2010-03-23 2011-10-06 Shindo Denshi Kogyo Kk フレキシブルプリント配線板の製造方法、半導体装置の製造方法、ディスプレイ装置の製造方法、フレキシブルプリント配線板、半導体装置及びディスプレイ装置
KR102055194B1 (ko) 2013-05-06 2019-12-12 삼성전자주식회사 표시 장치
KR20150080878A (ko) * 2014-01-02 2015-07-10 삼성전자주식회사 디스플레이 모듈 및 이를 갖춘 디스플레이 장치
US9335231B2 (en) * 2014-03-25 2016-05-10 Mks Instruments, Inc. Micro-Pirani vacuum gauges
US9195358B1 (en) * 2014-04-16 2015-11-24 Eastman Kodak Company Z-fold multi-element substrate structure
TWI477216B (zh) * 2014-06-09 2015-03-11 Chipbond Technology Corp 可撓式基板
US9379355B1 (en) 2014-12-15 2016-06-28 Lg Display Co., Ltd. Flexible display device having support layer with rounded edge
KR20160110861A (ko) * 2015-03-13 2016-09-22 삼성디스플레이 주식회사 연성 회로 기판 및 이를 포함하는 표시 장치
US10177347B2 (en) * 2015-07-01 2019-01-08 Sharp Kabushiki Kaisha Method for manufacturing display device
CN204884440U (zh) * 2015-08-27 2015-12-16 京东方科技集团股份有限公司 柔性显示面板和柔性显示装置
KR102465929B1 (ko) * 2016-02-19 2022-11-10 삼성디스플레이 주식회사 터치 스크린 패널 및 이를 포함하는 이동 단말기
JP6817862B2 (ja) * 2017-03-24 2021-01-20 株式会社ジャパンディスプレイ 表示装置
CN107172802B (zh) * 2017-06-21 2023-10-13 上海传英信息技术有限公司 简易显示屏
CN111091764B (zh) * 2018-10-18 2022-04-15 启耀光电股份有限公司 电子装置与其制造方法
DE102019205617A1 (de) * 2019-04-17 2020-10-22 Brose Fahrzeugteile Se & Co. Kommanditgesellschaft, Bamberg Verfahren zur Herstellung eines Trägermoduls und Trägermodul
JP7241622B2 (ja) * 2019-06-24 2023-03-17 株式会社ジャパンディスプレイ 電気機器、表示装置及びそれらの製造方法
CN113570975A (zh) * 2020-04-29 2021-10-29 深圳市柔宇科技有限公司 面板组件及电子设备
CN112349206B (zh) * 2020-11-09 2022-07-12 厦门天马微电子有限公司 一种可折叠显示装置
CN115318565B (zh) * 2022-10-14 2022-12-09 高能瑞泰(山东)电子科技有限公司 一种倒装芯片封装设备
KR20240121588A (ko) * 2023-02-02 2024-08-09 엘지이노텍 주식회사 연성 회로기판, cof 모듈 및 이를 포함하는 전자 디바이스

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003309150A (ja) 2002-04-17 2003-10-31 Sharp Corp 半導体装置
JP2004235353A (ja) 2003-01-29 2004-08-19 Matsushita Electric Ind Co Ltd 半導体装置およびそれを用いたディスプレイ装置
JP2006108356A (ja) 2004-10-05 2006-04-20 Sharp Corp 半導体装置および電子機器
JP2006135247A (ja) 2004-11-09 2006-05-25 Sharp Corp 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003309150A (ja) 2002-04-17 2003-10-31 Sharp Corp 半導体装置
JP2004235353A (ja) 2003-01-29 2004-08-19 Matsushita Electric Ind Co Ltd 半導体装置およびそれを用いたディスプレイ装置
JP2006108356A (ja) 2004-10-05 2006-04-20 Sharp Corp 半導体装置および電子機器
JP2006135247A (ja) 2004-11-09 2006-05-25 Sharp Corp 半導体装置

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TW200913177A (en) 2009-03-16
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EP2151862A1 (en) 2010-02-10
JP2009010309A (ja) 2009-01-15
CN101689535A (zh) 2010-03-31
KR20100024381A (ko) 2010-03-05
CN101689535B (zh) 2011-11-16

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