WO2008133052A1 - 半導体集積回路の2パターンテストにおける誤テスト回避型テスト入力生成方法 - Google Patents
半導体集積回路の2パターンテストにおける誤テスト回避型テスト入力生成方法 Download PDFInfo
- Publication number
- WO2008133052A1 WO2008133052A1 PCT/JP2008/057191 JP2008057191W WO2008133052A1 WO 2008133052 A1 WO2008133052 A1 WO 2008133052A1 JP 2008057191 W JP2008057191 W JP 2008057191W WO 2008133052 A1 WO2008133052 A1 WO 2008133052A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- test
- integrated circuit
- semiconductor integrated
- critical
- pattern
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318307—Generation of test inputs, e.g. test vectors, patterns or sequences computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/31813—Test pattern generators
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318371—Methodologies therefor, e.g. algorithms, procedures
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009511784A JP5141988B2 (ja) | 2007-04-23 | 2008-04-11 | 半導体集積回路の2パターンテストにおける誤テスト回避型テスト入力生成方法 |
US12/597,106 US8001437B2 (en) | 2007-04-23 | 2008-04-11 | Test pattern generation method for avoiding false testing in two-pattern testing for semiconductor integrated circuit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007-113238 | 2007-04-23 | ||
JP2007113238 | 2007-04-23 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2008133052A1 true WO2008133052A1 (ja) | 2008-11-06 |
Family
ID=39925511
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2008/057191 WO2008133052A1 (ja) | 2007-04-23 | 2008-04-11 | 半導体集積回路の2パターンテストにおける誤テスト回避型テスト入力生成方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8001437B2 (ja) |
JP (1) | JP5141988B2 (ja) |
TW (1) | TW200907386A (ja) |
WO (1) | WO2008133052A1 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5843358B2 (ja) * | 2010-01-15 | 2016-01-13 | 国立大学法人 奈良先端科学技術大学院大学 | 半導体集積回路のテストパターン生成方法、プログラム、およびコンピュータ読み取り可能な記録媒体 |
US8413102B2 (en) * | 2011-08-03 | 2013-04-02 | Apple Inc. | Vectorless IVD analysis prior to tapeout to prevent scan test failure due to voltage drop |
US8776006B1 (en) | 2013-02-27 | 2014-07-08 | International Business Machines Corporation | Delay defect testing of power drop effects in integrated circuits |
US9122891B2 (en) * | 2013-08-12 | 2015-09-01 | Microsoft Technology Licensing, Llc | Functional timing sensors |
WO2015087114A1 (en) * | 2013-12-13 | 2015-06-18 | Freescale Semiconductor, Inc. | Method and apparatus for validating a test pattern |
US9465071B2 (en) | 2014-03-04 | 2016-10-11 | Mediatek Inc. | Method and apparatus for generating featured scan pattern |
US10018675B1 (en) * | 2014-03-14 | 2018-07-10 | Altera Corporation | Testing an integrated circuit in user mode using partial reconfiguration |
US10331826B2 (en) | 2017-04-20 | 2019-06-25 | Texas Instruments Incorporated | False path timing exception handler circuit |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2641954B2 (ja) * | 1990-02-07 | 1997-08-20 | 富士通株式会社 | テストパターンの発生装置 |
JPH10134093A (ja) * | 1996-10-28 | 1998-05-22 | Matsushita Electric Ind Co Ltd | 集積回路の性能推定装置及びその性能推定方法 |
JP2002279012A (ja) * | 2000-11-22 | 2002-09-27 | Matsushita Electric Ind Co Ltd | 遅延分布計算方法、回路評価方法およびフォールスパス抽出方法 |
JP2005308471A (ja) * | 2004-04-20 | 2005-11-04 | Matsushita Electric Ind Co Ltd | パスディレイテスト方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6148425A (en) * | 1998-02-12 | 2000-11-14 | Lucent Technologies Inc. | Bist architecture for detecting path-delay faults in a sequential circuit |
JP2001208803A (ja) * | 2000-01-24 | 2001-08-03 | Advantest Corp | 半導体集積回路の故障シミュレーション方法および故障シミュレータ |
US6684375B2 (en) * | 2000-11-22 | 2004-01-27 | Matsushita Electric Industrial Co., Ltd. | Delay distribution calculation method, circuit evaluation method and false path extraction method |
JP2005327308A (ja) | 2000-11-22 | 2005-11-24 | Matsushita Electric Ind Co Ltd | 回路性能評価方法 |
JP2005285144A (ja) | 2000-11-22 | 2005-10-13 | Matsushita Electric Ind Co Ltd | フォールスパス抽出方法 |
JP2006155644A (ja) | 2000-11-22 | 2006-06-15 | Matsushita Electric Ind Co Ltd | 遅延分布計算方法 |
US7131081B2 (en) * | 2003-02-14 | 2006-10-31 | Nec Laboratories America, Inc. | Scalable scan-path test point insertion technique |
US7313743B2 (en) * | 2003-09-04 | 2007-12-25 | Nec Laboratories America, Inc | Hybrid scan-based delay testing technique for compact and high fault coverage test set |
-
2008
- 2008-04-11 JP JP2009511784A patent/JP5141988B2/ja not_active Expired - Fee Related
- 2008-04-11 WO PCT/JP2008/057191 patent/WO2008133052A1/ja active Application Filing
- 2008-04-11 US US12/597,106 patent/US8001437B2/en not_active Expired - Fee Related
- 2008-04-16 TW TW097113765A patent/TW200907386A/zh not_active IP Right Cessation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2641954B2 (ja) * | 1990-02-07 | 1997-08-20 | 富士通株式会社 | テストパターンの発生装置 |
JPH10134093A (ja) * | 1996-10-28 | 1998-05-22 | Matsushita Electric Ind Co Ltd | 集積回路の性能推定装置及びその性能推定方法 |
JP2002279012A (ja) * | 2000-11-22 | 2002-09-27 | Matsushita Electric Ind Co Ltd | 遅延分布計算方法、回路評価方法およびフォールスパス抽出方法 |
JP2005308471A (ja) * | 2004-04-20 | 2005-11-04 | Matsushita Electric Ind Co Ltd | パスディレイテスト方法 |
Non-Patent Citations (4)
Title |
---|
SANKARALINGAM R., POUYA B., TOUBA N.A.: "Reducing power dissipation during test using scan chain disable", 19TH IEEE PROCEEDINGS ON VLSI TEST SYMPOSIUM, 29 April 2001 (2001-04-29), pages 319 - 324, XP010542404 * |
SATO Y. ET AL.: "Invisible delay quality - SDQM model lights up what could not be seen", TEST CONFERENCE, 2005. PROCEEDINGS. ITC 2005. IEEE INTERNATIONAL, 8 November 2005 (2005-11-08), pages 47.1 1 - 47.1 9, XP010888339 * |
XIAOQING MEN ET AL.: "On low-capture-power test generation for scan testing", VLSI TEST SYMPOSIUM, 2005. PROCEEDINGS. 23RD IEEE, 1 May 2005 (2005-05-01), pages 265 - 270, XP010809193 * |
XIAOQING WEN ET AL.: "Critical-Path-Awae X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing", DESIGN AUTOMATION CONFERENCE, 2007. DAC'07. 44TH ACM/IEEE, 4 June 2007 (2007-06-04), pages 527 - 532, XP031183400 * |
Also Published As
Publication number | Publication date |
---|---|
JP5141988B2 (ja) | 2013-02-13 |
US20100095179A1 (en) | 2010-04-15 |
TW200907386A (en) | 2009-02-16 |
US8001437B2 (en) | 2011-08-16 |
TWI368043B (ja) | 2012-07-11 |
JPWO2008133052A1 (ja) | 2010-07-22 |
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