WO2008117441A1 - イコライザ特性最適化方法、伝送システム、通信装置及びプログラム - Google Patents

イコライザ特性最適化方法、伝送システム、通信装置及びプログラム Download PDF

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Publication number
WO2008117441A1
WO2008117441A1 PCT/JP2007/056398 JP2007056398W WO2008117441A1 WO 2008117441 A1 WO2008117441 A1 WO 2008117441A1 JP 2007056398 W JP2007056398 W JP 2007056398W WO 2008117441 A1 WO2008117441 A1 WO 2008117441A1
Authority
WO
WIPO (PCT)
Prior art keywords
acquiring
latch
logical value
equalizer
clock timing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/056398
Other languages
English (en)
French (fr)
Inventor
Manabu Yamazaki
Masaki Tosaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to KR1020097020005A priority Critical patent/KR101021205B1/ko
Priority to JP2009506154A priority patent/JP4796645B2/ja
Priority to CN2007800523712A priority patent/CN101652932B/zh
Priority to PCT/JP2007/056398 priority patent/WO2008117441A1/ja
Publication of WO2008117441A1 publication Critical patent/WO2008117441A1/ja
Priority to US12/585,619 priority patent/US8194727B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—DC level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/061—DC level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of DC offset
    • H04L25/063—Setting decision thresholds using feedback techniques only
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/04—Control of transmission; Equalising
    • H04B3/06—Control of transmission; Equalising by the transmitted signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L2025/0335—Arrangements for removing intersymbol interference characterised by the type of transmission
    • H04L2025/03356—Baseband transmission

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dc Digital Transmission (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

　受信信号の波形からリカバリクロックタイミングを得るリカバリクロック取得段階と、リカバリクロックタイミングを中心とした所定のサンプリングクロックタイミングを得るサンプリングクロック取得段階と、リカバリクロックタイミングで受信信号をラッチする第１のラッチ段階と、サンプリングクロックタイミングで受信信号をラッチする第２のラッチ段階と、第１のラッチ段階で得られた論理値と前記第２のラッチ段階で得られた論理値とを比較する論理値比較段階と、イコライザの特性の設定を変更し、変化後の状態で前記リカバリクロック取得段階、サンプリングクロック取得段階、第１のラッチ段階、第２のラッチ段階および論理値比較段階を行う動作を繰り返すデータ収集段階と、データ収集段階で収集された論理値比較結果のデータに基づいて前記イコライザの最適な特性の設定を求める最適設定抽出段階とよりなる構成である。
PCT/JP2007/056398 2007-03-27 2007-03-27 イコライザ特性最適化方法、伝送システム、通信装置及びプログラム Ceased WO2008117441A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1020097020005A KR101021205B1 (ko) 2007-03-27 2007-03-27 이퀄라이저 특성 최적화 방법, 전송 시스템, 통신 장치, 및 프로그램을 기록한 컴퓨터 판독 가능한 기록 매체
JP2009506154A JP4796645B2 (ja) 2007-03-27 2007-03-27 イコライザ特性最適化方法、伝送システム、通信装置及びプログラム
CN2007800523712A CN101652932B (zh) 2007-03-27 2007-03-27 均衡器特性最优化方法、传送系统、通信装置及程序
PCT/JP2007/056398 WO2008117441A1 (ja) 2007-03-27 2007-03-27 イコライザ特性最適化方法、伝送システム、通信装置及びプログラム
US12/585,619 US8194727B2 (en) 2007-03-27 2009-09-18 Equalizer characteristics optimizing method and transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/056398 WO2008117441A1 (ja) 2007-03-27 2007-03-27 イコライザ特性最適化方法、伝送システム、通信装置及びプログラム

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/585,619 Continuation US8194727B2 (en) 2007-03-27 2009-09-18 Equalizer characteristics optimizing method and transmission system

Publications (1)

Publication Number Publication Date
WO2008117441A1 true WO2008117441A1 (ja) 2008-10-02

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/056398 Ceased WO2008117441A1 (ja) 2007-03-27 2007-03-27 イコライザ特性最適化方法、伝送システム、通信装置及びプログラム

Country Status (5)

Country Link
US (1) US8194727B2 (ja)
JP (1) JP4796645B2 (ja)
KR (1) KR101021205B1 (ja)
CN (1) CN101652932B (ja)
WO (1) WO2008117441A1 (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012191509A (ja) * 2011-03-11 2012-10-04 Toshiba Corp ストレージ装置、電子機器及び周波数帯域補償レベル調整方法
US9385894B2 (en) 2014-10-02 2016-07-05 Fujitsu Limited Receiving circuit and data decision method
WO2021256010A1 (ja) * 2020-06-17 2021-12-23 日立Astemo株式会社 電子制御装置、判定方法
JP2023530110A (ja) * 2020-06-11 2023-07-13 テクトロニクス・インコーポレイテッド 波形データの循環ループ画像表示

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KR101931223B1 (ko) * 2011-12-29 2018-12-21 에스케이하이닉스 주식회사 데이터 이퀄라이징 회로 및 데이터 이퀄라이징 방법
US9036751B1 (en) 2012-01-17 2015-05-19 Clariphy Communications, Inc. Skew compensation based on equalizer coefficients
JP7033786B2 (ja) * 2018-07-13 2022-03-11 ザインエレクトロニクス株式会社 イコライザ調整装置、イコライザ調整方法、受信機および送受信システム
KR102711854B1 (ko) * 2020-08-18 2024-09-30 삼성전자주식회사 적응적 등화를 수행하는 수신 회로 및 이를 포함하는 시스템
US11444813B1 (en) * 2021-07-23 2022-09-13 Macom Technology Solutions Holdings, Inc. Method and apparatus for CTLE equalizer adaptation based on samples from error slicers
CN116055265B (zh) * 2022-08-12 2024-11-15 海光信息技术股份有限公司 一种连续时间线性均衡器的补偿方法、接收机及电子设备

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Publication number Priority date Publication date Assignee Title
JP2005303607A (ja) * 2004-04-09 2005-10-27 Fujitsu Ltd 等化回路を有する受信回路
JP2007053648A (ja) * 2005-08-19 2007-03-01 Fujitsu Ltd 通信機能を有する装置、送信器自動調整方法、システム及びプログラム

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JPS62130037A (ja) 1985-12-02 1987-06-12 Hitachi Ltd クロツク位相選択方法及びその装置
JPS62159545A (ja) 1986-01-08 1987-07-15 Hitachi Ltd 信号伝送方式
JP3622287B2 (ja) 1995-09-01 2005-02-23 ソニー株式会社 ディジタル信号再生回路および再生方法
EP0831479B1 (en) * 1996-09-24 2001-12-05 Hewlett-Packard Company, A Delaware Corporation Data processing apparatus and methods
US7277516B2 (en) * 2003-10-14 2007-10-02 Realtek Semiconductor Corp Adaptive equalization system for a signal receiver
US7233164B2 (en) * 2003-12-17 2007-06-19 Rambus Inc. Offset cancellation in a multi-level signaling system
US7193802B2 (en) * 2004-03-25 2007-03-20 Hitachi Global Storage Technologies Netherlands, B.V. Apparatus for providing dynamic equalizer optimization
GB0504425D0 (en) * 2005-03-03 2005-04-06 Texas Instruments Ltd Equalisation circuit
KR100795724B1 (ko) 2005-08-24 2008-01-17 삼성전자주식회사 아이 사이즈 측정 회로, 데이터 통신 시스템의 수신기 및아이 사이즈 측정 방법
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Publication number Priority date Publication date Assignee Title
JP2005303607A (ja) * 2004-04-09 2005-10-27 Fujitsu Ltd 等化回路を有する受信回路
JP2007053648A (ja) * 2005-08-19 2007-03-01 Fujitsu Ltd 通信機能を有する装置、送信器自動調整方法、システム及びプログラム

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012191509A (ja) * 2011-03-11 2012-10-04 Toshiba Corp ストレージ装置、電子機器及び周波数帯域補償レベル調整方法
US9385894B2 (en) 2014-10-02 2016-07-05 Fujitsu Limited Receiving circuit and data decision method
JP2023530110A (ja) * 2020-06-11 2023-07-13 テクトロニクス・インコーポレイテッド 波形データの循環ループ画像表示
JP7781079B2 (ja) 2020-06-11 2025-12-05 テクトロニクス・インコーポレイテッド 循環ループ画像表示システム、循環ループ画像生成方法及び試験測定装置
WO2021256010A1 (ja) * 2020-06-17 2021-12-23 日立Astemo株式会社 電子制御装置、判定方法
JP2021197696A (ja) * 2020-06-17 2021-12-27 日立Astemo株式会社 電子制御装置、判定方法
JP7449785B2 (ja) 2020-06-17 2024-03-14 日立Astemo株式会社 電子制御装置、判定方法
US12119964B2 (en) 2020-06-17 2024-10-15 Hitachi Astemo, Ltd. Electronic control device and determination method

Also Published As

Publication number Publication date
CN101652932B (zh) 2013-03-27
JP4796645B2 (ja) 2011-10-19
KR101021205B1 (ko) 2011-03-11
CN101652932A (zh) 2010-02-17
US8194727B2 (en) 2012-06-05
JPWO2008117441A1 (ja) 2010-07-08
KR20100005050A (ko) 2010-01-13
US20100008413A1 (en) 2010-01-14

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