WO2008102595A1 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
WO2008102595A1
WO2008102595A1 PCT/JP2008/050827 JP2008050827W WO2008102595A1 WO 2008102595 A1 WO2008102595 A1 WO 2008102595A1 JP 2008050827 W JP2008050827 W JP 2008050827W WO 2008102595 A1 WO2008102595 A1 WO 2008102595A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor layer
semiconductor device
manufacturing
same
insulating substrate
Prior art date
Application number
PCT/JP2008/050827
Other languages
English (en)
French (fr)
Inventor
Hiroyuki Moriwaki
Original Assignee
Sharp Kabushiki Kaisha
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Kabushiki Kaisha filed Critical Sharp Kabushiki Kaisha
Priority to US12/517,686 priority Critical patent/US8067771B2/en
Priority to CN200880001187XA priority patent/CN101569016B/zh
Publication of WO2008102595A1 publication Critical patent/WO2008102595A1/ja

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

　第１半導体層を有するｐ型ＴＦＴと、第２半導体層を有するｎ型ＴＦＴとを備え、第１半導体層の外縁部分の少なくとも一部には、絶縁性基板側へテーパ状に広がる傾斜部が形成され、第１半導体層の内側に形成される角度であって絶縁性基板の表面に対する傾斜部表面の傾斜角度は、第２半導体層の内側に形成される角度であって絶縁性基板の表面に対する第２半導体層の外縁部分側面の角度よりも小さい。
PCT/JP2008/050827 2007-02-21 2008-01-22 半導体装置及びその製造方法 WO2008102595A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/517,686 US8067771B2 (en) 2007-02-21 2008-01-22 Semiconductor device and method for manufacturing the same
CN200880001187XA CN101569016B (zh) 2007-02-21 2008-01-22 半导体装置及其制造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-040744 2007-02-21
JP2007040744 2007-02-21

Publications (1)

Publication Number Publication Date
WO2008102595A1 true WO2008102595A1 (ja) 2008-08-28

Family

ID=39709874

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/050827 WO2008102595A1 (ja) 2007-02-21 2008-01-22 半導体装置及びその製造方法

Country Status (3)

Country Link
US (1) US8067771B2 (ja)
CN (1) CN101569016B (ja)
WO (1) WO2008102595A1 (ja)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000196096A (ja) * 1998-12-28 2000-07-14 Fujitsu Ltd 半導体装置、画像表示装置、半導体装置の製造方法、及び画像表示装置の製造方法
JP2003174036A (ja) * 2001-12-07 2003-06-20 Seiko Epson Corp 薄膜トランジスタの製造方法及び薄膜トランジスタ
JP2007027198A (ja) * 2005-07-12 2007-02-01 Sanyo Epson Imaging Devices Corp 薄膜トランジスタの製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6420758B1 (en) * 1998-11-17 2002-07-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having an impurity region overlapping a gate electrode
JP4575621B2 (ja) 2001-05-21 2010-11-04 シャープ株式会社 薄膜トランジスタ
JP2003298059A (ja) * 2002-03-29 2003-10-17 Advanced Lcd Technologies Development Center Co Ltd 薄膜トランジスタ
CN1249819C (zh) * 2003-01-09 2006-04-05 中国科学院等离子体物理研究所 纳米多孔薄膜

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000196096A (ja) * 1998-12-28 2000-07-14 Fujitsu Ltd 半導体装置、画像表示装置、半導体装置の製造方法、及び画像表示装置の製造方法
JP2003174036A (ja) * 2001-12-07 2003-06-20 Seiko Epson Corp 薄膜トランジスタの製造方法及び薄膜トランジスタ
JP2007027198A (ja) * 2005-07-12 2007-02-01 Sanyo Epson Imaging Devices Corp 薄膜トランジスタの製造方法

Also Published As

Publication number Publication date
CN101569016A (zh) 2009-10-28
US8067771B2 (en) 2011-11-29
CN101569016B (zh) 2011-03-23
US20090267069A1 (en) 2009-10-29

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