WO2008102433A1 - Ｌｓｉ試験装置、ｌｓｉ試験方法、ｌｓｉ試験プログラムおよび記録媒体 - Google Patents

Ｌｓｉ試験装置、ｌｓｉ試験方法、ｌｓｉ試験プログラムおよび記録媒体 Download PDF

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Publication number
WO2008102433A1
WO2008102433A1 PCT/JP2007/053059 JP2007053059W WO2008102433A1 WO 2008102433 A1 WO2008102433 A1 WO 2008102433A1 JP 2007053059 W JP2007053059 W JP 2007053059W WO 2008102433 A1 WO2008102433 A1 WO 2008102433A1
Authority
WO
WIPO (PCT)
Prior art keywords
lsi test
test
lsi
recording medium
voltage drop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/053059
Other languages
English (en)
French (fr)
Inventor
Satoru Yoshikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Fujitsu Semiconductor Ltd filed Critical Fujitsu Ltd
Priority to PCT/JP2007/053059 priority Critical patent/WO2008102433A1/ja
Priority to CN2007800508661A priority patent/CN101669036B/zh
Priority to KR1020097016072A priority patent/KR101117397B1/ko
Priority to US12/525,427 priority patent/US8134383B2/en
Priority to JP2009500030A priority patent/JP5316405B2/ja
Publication of WO2008102433A1 publication Critical patent/WO2008102433A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302—Contactless testing
    • G01R31/303—Contactless testing of integrated circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3004—Current or voltage test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318552—Clock circuits details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

　テスト合成前ネットリストにテスト回路を挿入し、それにより得られたテスト合成後ネットリストに基づいて一部のゲーテッドクロックバッファのみを同時に活性化させるテストパターンを生成する。そのテストパターンを用いてテスト合成後ネットリストからなる回路のシミュレーションを行い、それにより得られた動作率情報に基づいて電圧降下量を解析する。その解析により得られた電圧降下量がシステム動作時の電圧降下量以下になるように、ゲーテッドクロックバッファの活性化率を変更して、ＬＳＩの高速試験を行う。
PCT/JP2007/053059 2007-02-20 2007-02-20 Ｌｓｉ試験装置、ｌｓｉ試験方法、ｌｓｉ試験プログラムおよび記録媒体 Ceased WO2008102433A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
PCT/JP2007/053059 WO2008102433A1 (ja) 2007-02-20 2007-02-20 Ｌｓｉ試験装置、ｌｓｉ試験方法、ｌｓｉ試験プログラムおよび記録媒体
CN2007800508661A CN101669036B (zh) 2007-02-20 2007-02-20 Lsi试验装置、lsi试验方法
KR1020097016072A KR101117397B1 (ko) 2007-02-20 2007-02-20 Ｌｓｉ 시험 장치, ｌｓｉ 시험 방법, 및 ｌｓｉ 시험 프로그램을 기록한 기록 매체
US12/525,427 US8134383B2 (en) 2007-02-20 2007-02-20 LSI test apparatus, LSI test method, and computer product
JP2009500030A JP5316405B2 (ja) 2007-02-20 2007-02-20 Ｌｓｉ試験装置、ｌｓｉ試験方法、ｌｓｉ試験プログラムおよび記録媒体

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/053059 WO2008102433A1 (ja) 2007-02-20 2007-02-20 Ｌｓｉ試験装置、ｌｓｉ試験方法、ｌｓｉ試験プログラムおよび記録媒体

Publications (1)

Publication Number Publication Date
WO2008102433A1 true WO2008102433A1 (ja) 2008-08-28

Family

ID=39709719

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/053059 Ceased WO2008102433A1 (ja) 2007-02-20 2007-02-20 Ｌｓｉ試験装置、ｌｓｉ試験方法、ｌｓｉ試験プログラムおよび記録媒体

Country Status (5)

Country Link
US (1) US8134383B2 (ja)
JP (1) JP5316405B2 (ja)
KR (1) KR101117397B1 (ja)
CN (1) CN101669036B (ja)
WO (1) WO2008102433A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8754667B2 (en) 2010-03-19 2014-06-17 Fujitsu Semiconductor Limited Semiconductor device test method and semiconductor device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
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JPWO2010021131A1 (ja) * 2008-08-19 2012-01-26 株式会社アドバンテスト 試験装置および試験方法
CN102243605B (zh) * 2010-05-14 2014-04-30 鸿富锦精密工业（深圳）有限公司 检测装置及其检测方法
US20140181603A1 (en) * 2012-12-21 2014-06-26 Iwan R. Grau Method and apparatus for tuning scan capture phase activity factor

Citations (4)

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JP2004286549A (ja) * 2003-03-20 2004-10-14 Matsushita Electric Ind Co Ltd スキャンテスト装置およびその設計方法
JP2005050030A (ja) * 2003-07-31 2005-02-24 Fujitsu Ltd 半導体集積回路装置、クロック制御方法及びデータ転送制御方法
JP2006038831A (ja) * 2004-06-23 2006-02-09 Fujitsu Ltd スキャン試験回路を備えた半導体集積回路
JP2006066825A (ja) * 2004-08-30 2006-03-09 Renesas Technology Corp 半導体集積回路テスト設計支援装置

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DE19643658C1 (de) * 1996-10-22 1998-03-26 Siemens Ag Verfahren zum Steuern des Anmeldens von Schnurlos-Mobilteilen bei Schnurlos-Basisstationen universeller Mobil-Telekommunikationssysteme, insbesondere von DECT-Mobilteilen bei DECT-Basisstationen CAP-spezifischer Telekommunikationssysteme
JPH10320440A (ja) 1997-05-21 1998-12-04 Oki Electric Ind Co Ltd 論理シミュレーションライブラリと電子回路の動作確認方法及びその装置
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JP2005050030A (ja) * 2003-07-31 2005-02-24 Fujitsu Ltd 半導体集積回路装置、クロック制御方法及びデータ転送制御方法
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JP2006066825A (ja) * 2004-08-30 2006-03-09 Renesas Technology Corp 半導体集積回路テスト設計支援装置

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8754667B2 (en) 2010-03-19 2014-06-17 Fujitsu Semiconductor Limited Semiconductor device test method and semiconductor device

Also Published As

Publication number Publication date
JPWO2008102433A1 (ja) 2010-05-27
KR101117397B1 (ko) 2012-03-07
US8134383B2 (en) 2012-03-13
KR20100004930A (ko) 2010-01-13
CN101669036A (zh) 2010-03-10
JP5316405B2 (ja) 2013-10-16
CN101669036B (zh) 2013-05-22
US20100090705A1 (en) 2010-04-15

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