WO2008099499A1 - Ｐ型ｍｏｓトランジスタの製造方法、そのｐ型ｍｏｓトランジスタを含むｃｍｏｓ型の半導体装置の製造方法、及び、その製造方法によって製造されたｃｍｏｓ型の半導体装置 - Google Patents

Ｐ型ｍｏｓトランジスタの製造方法、そのｐ型ｍｏｓトランジスタを含むｃｍｏｓ型の半導体装置の製造方法、及び、その製造方法によって製造されたｃｍｏｓ型の半導体装置 Download PDF

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Publication number
WO2008099499A1
WO2008099499A1 PCT/JP2007/052829 JP2007052829W WO2008099499A1 WO 2008099499 A1 WO2008099499 A1 WO 2008099499A1 JP 2007052829 W JP2007052829 W JP 2007052829W WO 2008099499 A1 WO2008099499 A1 WO 2008099499A1
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WO
WIPO (PCT)
Prior art keywords
manufacturing
mos transistor
type mos
type
cmos
Prior art date
Application number
PCT/JP2007/052829
Other languages
English (en)
French (fr)
Inventor
Teruo Kurahashi
Yasuyoshi Mishima
Yukie Sakita
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2007/052829 priority Critical patent/WO2008099499A1/ja
Priority to JP2008557956A priority patent/JP5146326B2/ja
Publication of WO2008099499A1 publication Critical patent/WO2008099499A1/ja
Priority to US12/541,556 priority patent/US8470653B2/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H01L29/4975—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

　本発明の目的は、Ｐ型ＭＯＳトランジスタのゲート電極を構成する材料の仕事関数を容易に制御可能なＰ型ＭＯＳトランジスタの製造方法、その製造方法によって製造したＰ型ＭＯＳトランジスタ、そのＰ型ＭＯＳトランジスタを含むＣＭＯＳ型の半導体装置を提供することである。 　上記の課題を解決するため、本発明は、Ｎ型領域を備える基板を用意する工程と、高誘電体絶縁膜からなるゲート絶縁膜を基板の表面に形成するゲート絶縁膜形成工程と、Ｎ型領域に不純物が添加されていないアモルファスシリコンからなるゲート電極を形成する工程と、アモルファスシリコンの膜質を制御する熱処理工程と、その後、ゲート電極上にニッケル（Ｎｉ）を堆積する工程と、膜質を制御したアモルファスシリコンとニッケル（Ｎｉ）とからニッケルシリサイドを形成する工程と、からなるＰ型ＭＯＳトランジスタの製造方法を提供する。
PCT/JP2007/052829 2007-02-16 2007-02-16 Ｐ型ｍｏｓトランジスタの製造方法、そのｐ型ｍｏｓトランジスタを含むｃｍｏｓ型の半導体装置の製造方法、及び、その製造方法によって製造されたｃｍｏｓ型の半導体装置 WO2008099499A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/JP2007/052829 WO2008099499A1 (ja) 2007-02-16 2007-02-16 Ｐ型ｍｏｓトランジスタの製造方法、そのｐ型ｍｏｓトランジスタを含むｃｍｏｓ型の半導体装置の製造方法、及び、その製造方法によって製造されたｃｍｏｓ型の半導体装置
JP2008557956A JP5146326B2 (ja) 2007-02-16 2007-02-16 Ｐ型ｍｏｓトランジスタの製造方法、そのｐ型ｍｏｓトランジスタを含むｃｍｏｓ型の半導体装置の製造方法、及び、その製造方法によって製造されたｃｍｏｓ型の半導体装置
US12/541,556 US8470653B2 (en) 2007-02-16 2009-08-14 Method for manufacturing a P-type MOS transistor, method for manufacturing a CMOS-type semiconductor apparatus having the P-type MOS transistor, and CMOS-type semiconductor apparatus manufactured using the manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/052829 WO2008099499A1 (ja) 2007-02-16 2007-02-16 Ｐ型ｍｏｓトランジスタの製造方法、そのｐ型ｍｏｓトランジスタを含むｃｍｏｓ型の半導体装置の製造方法、及び、その製造方法によって製造されたｃｍｏｓ型の半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/541,556 Continuation US8470653B2 (en) 2007-02-16 2009-08-14 Method for manufacturing a P-type MOS transistor, method for manufacturing a CMOS-type semiconductor apparatus having the P-type MOS transistor, and CMOS-type semiconductor apparatus manufactured using the manufacturing method

Publications (1)

Publication Number Publication Date
WO2008099499A1 true WO2008099499A1 (ja) 2008-08-21

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Application Number Title Priority Date Filing Date
PCT/JP2007/052829 WO2008099499A1 (ja) 2007-02-16 2007-02-16 Ｐ型ｍｏｓトランジスタの製造方法、そのｐ型ｍｏｓトランジスタを含むｃｍｏｓ型の半導体装置の製造方法、及び、その製造方法によって製造されたｃｍｏｓ型の半導体装置

Country Status (3)

Country Link
US (1) US8470653B2 (ja)
JP (1) JP5146326B2 (ja)
WO (1) WO2008099499A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016063743A1 (ja) * 2014-10-23 2016-04-28 株式会社Ｓｃｒｅｅｎホールディングス 熱処理方法および熱処理装置
JP2016115830A (ja) * 2014-12-16 2016-06-23 株式会社Ｓｃｒｅｅｎホールディングス 熱処理方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102420185A (zh) * 2010-09-25 2012-04-18 中芯国际集成电路制造(上海)有限公司 Cmos晶体管的制作方法
CN103094120A (zh) * 2011-11-08 2013-05-08 中国科学院微电子研究所 一种半导体结构的制造方法
US9023708B2 (en) * 2013-04-19 2015-05-05 United Microelectronics Corp. Method of forming semiconductor device
US9209086B2 (en) * 2013-07-22 2015-12-08 Globalfoundries Inc. Low temperature salicide for replacement gate nanowires

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JPH0613402A (ja) * 1992-06-29 1994-01-21 Toshiba Corp 半導体装置の製造方法
JPH08274185A (ja) * 1995-03-30 1996-10-18 Sony Corp Ｍｏｓトランジスタの製造方法
JP2005243664A (ja) * 2004-02-24 2005-09-08 Renesas Technology Corp 半導体装置およびその製造方法
JP2005294704A (ja) * 2004-04-02 2005-10-20 Nec Electronics Corp 半導体装置の製造方法
JP2005347605A (ja) * 2004-06-04 2005-12-15 Hitachi Ltd 半導体装置およびその製造方法
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JP4101409B2 (ja) * 1999-08-19 2008-06-18 シャープ株式会社 半導体装置の製造方法
JP2005294799A (ja) 2004-03-12 2005-10-20 Toshiba Corp 半導体装置およびその製造方法
KR100685804B1 (ko) * 2004-12-14 2007-02-22 삼성에스디아이 주식회사 유기전계발광소자 및 그의 제조방법
JP2006344836A (ja) * 2005-06-09 2006-12-21 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
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Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0613402A (ja) * 1992-06-29 1994-01-21 Toshiba Corp 半導体装置の製造方法
JPH08274185A (ja) * 1995-03-30 1996-10-18 Sony Corp Ｍｏｓトランジスタの製造方法
JP2005243664A (ja) * 2004-02-24 2005-09-08 Renesas Technology Corp 半導体装置およびその製造方法
JP2005294704A (ja) * 2004-04-02 2005-10-20 Nec Electronics Corp 半導体装置の製造方法
JP2005347605A (ja) * 2004-06-04 2005-12-15 Hitachi Ltd 半導体装置およびその製造方法
JP2006013270A (ja) * 2004-06-29 2006-01-12 Renesas Technology Corp 半導体装置およびその製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016063743A1 (ja) * 2014-10-23 2016-04-28 株式会社Ｓｃｒｅｅｎホールディングス 熱処理方法および熱処理装置
US10437153B2 (en) 2014-10-23 2019-10-08 SCREEN Holdings Co., Ltd. Heat treatment method and heat treatment apparatus
JP2016115830A (ja) * 2014-12-16 2016-06-23 株式会社Ｓｃｒｅｅｎホールディングス 熱処理方法

Also Published As

Publication number Publication date
JP5146326B2 (ja) 2013-02-20
JPWO2008099499A1 (ja) 2010-05-27
US8470653B2 (en) 2013-06-25
US20100044799A1 (en) 2010-02-25

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