WO2008059633A1 - Élément semi-conducteur, procédé de fabrication de celui-ci et affichage - Google Patents

Élément semi-conducteur, procédé de fabrication de celui-ci et affichage Download PDF

Info

Publication number
WO2008059633A1
WO2008059633A1 PCT/JP2007/062523 JP2007062523W WO2008059633A1 WO 2008059633 A1 WO2008059633 A1 WO 2008059633A1 JP 2007062523 W JP2007062523 W JP 2007062523W WO 2008059633 A1 WO2008059633 A1 WO 2008059633A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor layer
insulating film
film
gate insulating
gate
Prior art date
Application number
PCT/JP2007/062523
Other languages
English (en)
Japanese (ja)
Inventor
Hiroshi Matsukizono
Takuya Matsuo
Naoki Makita
Takashi Terauchi
Original Assignee
Sharp Kabushiki Kaisha
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Kabushiki Kaisha filed Critical Sharp Kabushiki Kaisha
Publication of WO2008059633A1 publication Critical patent/WO2008059633A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates

Definitions

  • the present invention relates to a semiconductor element, a manufacturing method thereof, and a display device, and more particularly to a semiconductor element such as a top gate type thin film transistor.
  • a thin film transistor (hereinafter abbreviated as “TFT”) is a semiconductor element widely used as a switching element of a liquid crystal display device of an active matrix driving system.
  • a top-gate TFT is provided between a semiconductor layer provided on an insulating substrate, a gate electrode provided on a semiconductor layer, and the semiconductor layer and the gate electrode.
  • a gate insulating film is provided between a semiconductor layer provided on an insulating substrate, a gate electrode provided on a semiconductor layer, and the semiconductor layer and the gate electrode.
  • the gate insulating film is generally composed of a silicon oxide film or the like.
  • this gate insulating film is formed thinly to about 1000 A or less, for example, there is a possibility that a pinhole penetrating the gate insulating film is formed as a defect. Further, when the pinhole is formed so as to overlap with the semiconductor layer, the conductive material constituting the gate electrode formed in a later process is filled in the pinhole, so that the gate electrode and the semiconductor are formed. There is a possibility that the layer may be conducted through a pinhole. In such a case, the liquid crystal display device equipped with the TFT cannot operate the TFT normally, and the display quality deteriorates.
  • FIG. 14 is a cross-sectional view of a substrate in which defects due to pinholes have been repaired by a conventional oxidation treatment.
  • a base coat film 111 is provided between the insulating substrate 110 and the semiconductor layer 112.
  • the semiconductor layer 112 exposed from the pinhole Ph of the gate insulating film 113 For example, by performing a thermal oxidation process in an oxygen atmosphere at around 1000 ° C., a silicon oxide layer 112a is formed at the bottom of the pinhole Ph, and the insulating property of the gate insulating film 113 made of a silicon nitride film is maintained. Become.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 62-149139
  • the gate insulating film when the gate insulating film is formed thicker than the semiconductor layer, even if the semiconductor layer overlapping the pinhole is oxidized over the entire film thickness, it can be formed from the semiconductor layer of the defect repairing portion. Since the thickness of the oxide film is thinner than that of the gate insulating film, there is a concern that the reliability of the insulating property of the gate insulating film may be lowered.
  • the defect repair portion since the defect level density at the interface between the oxide film and the semiconductor layer in the defect repair portion is different from the defect level density at the interface between the gate insulating film and the semiconductor layer in the normal portion, for example, the defect repair portion
  • the threshold value for TFTs that include is different from that for TFTs that do not include defect repairs.
  • the TFT characteristics may vary from pixel to pixel due to the difference in the TFT threshold value, and the display quality may deteriorate. is there.
  • the circuit In the liquid crystal display device in which a circuit such as a constructed gate driver and the source driver is built by combining the TFT is the difference in the threshold of the TFT, the circuit does not operate correctly, problems will be caused a fear force s is there.
  • the present invention has been made in view of power, and the object of the present invention is to deteriorate the characteristics of the semiconductor element due to the pinhole of the gate insulating film without reducing the productivity. It is to suppress.
  • the present invention provides a top gate type semiconductor device in which the semiconductor layer is removed larger than the through hole in a portion where the semiconductor layer overlaps the through hole of the gate insulating film.
  • the gate electrode is not in contact with the inner wall in the removed portion of the semiconductor layer.
  • a semiconductor element according to the present invention is provided on a semiconductor layer provided on an insulating substrate, a gate insulating film provided so as to cover the semiconductor layer, and the gate insulating film.
  • a through hole is formed in the gate insulating film in a thickness direction, and the semiconductor layer is removed larger than the through hole in a portion overlapping the through hole.
  • the gate electrode is not in contact with the inner wall of the removed portion of the semiconductor layer.
  • the semiconductor layer is removed larger than the through hole in the portion overlapping the through hole of the gate insulating film, and the gate electrode is not formed on the inner wall in the removed portion of the semiconductor layer. Since it is a contact, the insulation between the gate electrode and the semiconductor layer is maintained.
  • the semiconductor layer is removed larger than the through hole in the portion overlapping the through hole of the gate insulating film, the insulation between the gate electrode and the semiconductor layer is maintained.
  • the reliability of the insulating property of the gate insulating film does not deteriorate due to the film thickness of the semiconductor layer.
  • the defect level density at the interface between the gate insulating film and the semiconductor layer in the portion having the through hole (defect repairing portion) and the normal state of the gate insulating film and the semiconductor layer in the portion Since the difference with the defect level density at the interface is less likely to occur, the difference between the threshold value of the semiconductor element including the defect repaired portion and the threshold value of the semiconductor element not including the defect repaired portion is less likely to occur.
  • removing the portion of the semiconductor layer that overlaps the through hole by etching to maintain the insulating property of the gate insulating film improves the insulating property of the gate insulating film by oxidation treatment. Since it can be processed in a shorter time than the method, it is excellent in productivity. [0018] Therefore, according to the above configuration, deterioration of the characteristics of the semiconductor element due to pinholes in the gate insulating film without reducing productivity is suppressed.
  • the gate insulating film includes a first insulating film on the semiconductor layer side and a second insulating film on the gate electrode side, and the second insulating film has an etching rate with respect to hydrofluoric acid of the first insulating film. It may be configured to be lower.
  • the etching rate for hydrofluoric acid of the second insulating film constituting the gate electrode side of the gate insulating film is lower than that of the first insulating film constituting the semiconductor layer side of the gate insulating film.
  • the formation of new through holes in the first insulating film and the second insulating film is suppressed by etching with hydrofluoric acid.
  • An oxide film may be provided on the inner wall of the removed portion of the semiconductor layer.
  • a method for manufacturing a semiconductor device includes a semiconductor layer forming step of forming a semiconductor layer on an insulating substrate, and a gate insulating film so as to cover the semiconductor layer formed in the semiconductor layer forming step.
  • the semiconductor layer etching step the semiconductor layer is removed (etched) larger than the through hole at the portion where the semiconductor layer overlaps the through hole of the gate insulating film.
  • the conductive film formation step the conductive film forming the gate electrode is not formed on the semiconductor layer. The film is formed by contact.
  • the gate electrode formation step the conductive film is patterned to form a gate electrode.
  • the gate electrode formed through the conductive film formation step and the gate electrode formation step is not in contact with the inner wall in the portion where the semiconductor layer is removed in the semiconductor layer etching step, the gate electrode and the semiconductor layer The insulation between them is maintained.
  • the defect level density at the interface between the gate insulating film and the semiconductor layer in the portion having the through hole (defect repairing portion) and the gate insulating film and the semiconductor layer in the normal portion Since the difference with the defect level density at the interface is less likely to occur, the difference between the threshold value of the semiconductor element including the defect repaired portion and the threshold value of the semiconductor element not including the defect repaired portion is less likely to occur.
  • the portion of the semiconductor layer that overlaps the through hole is removed by etching so that the insulating property of the gate insulating film is maintained. Since it can be processed in a shorter time than the conventional method of improving the production, it is excellent in productivity.
  • a first insulating film and a second insulating film having a lower etching rate with respect to hydrofluoric acid than the first insulating film are sequentially formed so as to cover the semiconductor layer.
  • an oxide film etching step of etching an oxide film formed on the surface of the semiconductor layer with hydrofluoric acid may be provided.
  • the semiconductor layer may be isotropically etched with an alkaline etchant.
  • the semiconductor layer etching step the semiconductor layer is removed to be larger than the through hole at a portion overlapping the through hole of the gate insulating film by isotropic etching with an alkaline etching solution. Therefore, the effects of the present invention are specifically exhibited.
  • the conductive film may be formed by sputtering.
  • the sputtered particle force is deposited by sputtering in the thickness direction of the gate insulating film, so that the conductive film constituting the gate electrode is not in contact with the semiconductor layer.
  • the insulating effect between the gate electrode and the semiconductor layer is maintained, so that the effects of the present invention are specifically exhibited.
  • an oxide film forming step of forming an oxide film on the inner wall of the semiconductor layer etched in the semiconductor layer etching step may be provided.
  • the conductive film cover coverage (covering property) is also determined in the conductive film forming step. Even if () is improved, an oxide film is formed between the inner wall of the semiconductor layer and the gate electrode in the oxide film forming step, so that the insulation between the gate electrode and the semiconductor layer is maintained.
  • the display device is a display device including an active matrix substrate on which a thin film transistor is formed, and the thin film transistor covers a semiconductor layer provided on an insulating substrate and the semiconductor layer. And a gate electrode provided on the gate insulating film.
  • a through-hole is formed in the gate insulating film in a thickness direction, and the semiconductor layer includes the through-hole.
  • a portion overlapping with the hole is removed to be larger than the through hole, and the gate electrode is formed in the removed portion of the semiconductor layer. It is characterized by non-contact with the inner wall.
  • the semiconductor layer is removed larger than the through hole in the portion overlapping the through hole of the gate insulating film, and the gate electrode is not formed on the inner wall in the removed portion of the semiconductor layer. Since it is a contact, the insulation between the gate electrode and the semiconductor layer is maintained.
  • the semiconductor layer is removed larger than the through hole in the portion overlapping the through hole of the gate insulating film, the insulation between the gate electrode and the semiconductor layer is maintained.
  • the reliability of the insulating property of the gate insulating film does not deteriorate due to the film thickness of the semiconductor layer.
  • the defect level density at the interface between the gate insulating film and the semiconductor layer in the portion having the through hole (defect repairing portion) and the normal state of the gate insulating film and the semiconductor layer in the semiconductor layer Since the difference between the defect level density at the interface is less likely to occur, the difference between the threshold value of the thin film transistor including the defect repair portion and the threshold value of the thin film transistor not including the defect repair portion is less likely to occur.
  • removing the portion of the semiconductor layer that overlaps the through hole by etching to maintain the insulating property of the gate insulating film improves the insulating property of the gate insulating film by oxidation treatment. Since it can be processed in a shorter time than the method, it is excellent in productivity.
  • the semiconductor layer is removed larger than the through hole in the portion overlapping the through hole of the gate insulating film, and the gate electrode is removed from the semiconductor layer. Therefore, the deterioration of the characteristics of the semiconductor element due to the pinhole of the gate insulating film can be suppressed without reducing the productivity.
  • FIG. 1 is a cross-sectional view showing a liquid crystal display device 50 according to Embodiment 1.
  • FIG. 1 is a cross-sectional view showing a liquid crystal display device 50 according to Embodiment 1.
  • FIG. 2 is a cross-sectional view showing TFT 5a in active matrix substrate 20 constituting liquid crystal display device 50.
  • FIG. 3 is a cross-sectional view showing a TFT 5b of a defect repaired portion in which a defect caused by a pinhole Ph is repaired.
  • FIG. 4 is a cross-sectional view showing an amorphous silicon film 12a formed in the semiconductor layer forming step.
  • FIG. 5 is a cross-sectional view showing a polysilicon film 12b formed in the semiconductor layer forming step.
  • FIG. 6 is a cross-sectional view showing a semiconductor layer 12P formed in the semiconductor layer forming step.
  • FIG. 7 is a cross-sectional view showing a gate insulating film 13 including a through hole Ph formed in the gate insulating film forming step.
  • FIG. 8 shows the semiconductor layer 12P etched in the semiconductor layer etching step.
  • FIG. 9 is a cross-sectional view showing a conductive film 14a formed in the conductive film formation step.
  • FIG. 10 is a cross-sectional view showing a TFT 5c of a defect repairing part in which a defect due to the pinhole Ph according to the second embodiment is repaired.
  • FIG. 11 shows the semiconductor layer 12P etched in the semiconductor layer etching step.
  • FIG. 12 is a cross-sectional view showing an oxide film 12f formed in the oxide film formation step.
  • FIG. 13 is a cross-sectional view showing a conductive film 14b formed in the conductive film formation step.
  • FIG. 14 is a cross-sectional view showing a substrate in which defects due to pinholes have been repaired by a conventional oxidation treatment.
  • liquid crystal display device including an active matrix substrate on which a TFT (semiconductor element) is formed will be described as a display device.
  • TFT semiconductor element
  • FIG. 1 is a cross-sectional view showing a liquid crystal display device 50 of the present embodiment
  • FIG. 2 is a cross-sectional view showing a TFT 5a in an active matrix substrate 20 constituting the liquid crystal display device 50.
  • the liquid crystal display device 50 includes an active matrix substrate 20, a counter substrate 30 disposed so as to face the active matrix substrate 20, and between the active matrix substrate 20 and the counter substrate 30.
  • a liquid crystal layer 25 provided in the frame, a seal portion 26 provided in a frame shape so as to surround the liquid crystal layer 25 between the active matrix substrate 20 and the counter substrate 30, and liquid crystals of the active matrix substrate 20 and the counter substrate 30.
  • the active matrix substrate 20 includes a plurality of gate lines (not shown) extending in parallel to each other, a plurality of source lines (not shown) extending in parallel to each other in a direction orthogonal to the gate lines, each gate line, A plurality of TFTs 5a provided as switching elements at the intersections of the source lines and a plurality of pixel electrodes 18 respectively provided corresponding to the TFTs 5a are provided (see FIG. 2).
  • the TFT 5a includes a semiconductor layer 12 provided on the base coat film 11 on the insulating substrate 10, a gate insulating film 13 provided so as to cover the semiconductor layer 12, and a gate insulating film. 13 is provided with a gate electrode 14aa provided on the interlayer insulating film 15, an interlayer insulating film 15 provided so as to cover the gate electrode 14aa, and a source electrode 16s and a drain electrode 16d provided on the interlayer insulating film 15.
  • a flat film 17 is provided on the interlayer insulating film 15 so as to cover the source electrode 16s and the drain electrode 16d.
  • a plurality of pixel electrodes 18 are provided in a matrix.
  • the semiconductor layer 12 includes a channel region 12c provided so as to overlap with the gate electrode 14aa, and a source region 12s and a drain region 12d provided at both ends of the channel region 12c, respectively.
  • the gate insulating film 13 includes a first insulating film 13a (for example, a silicon oxide film) provided on the semiconductor layer 12 side, and an etch against hydrofluoric acid than the first insulating film 13a provided on the gate electrode 14aa side.
  • a second insulating film 13b (for example, a silicon nitride film) having a low etching speed.
  • FIG. 3 is a cross-sectional view showing the TFT 5b of the defect repaired portion in which the defect due to the pinhole Ph is repaired.
  • the defect repairing portion is provided with a removal portion 12ea in which the semiconductor layer 12 is removed larger than the pinhole Ph in a portion overlapping with the pinhole Ph.
  • the semiconductor layer 12 is removed so that the inner peripheral end (inner wall W) is disposed outside the pinhole Ph in the portion overlapping the pinhole Ph of the gate insulating film 13.
  • FIG. 3 is a cross-sectional view showing the TFT 5b of the defect repaired portion in which the defect due to the pinhole Ph is repaired.
  • the defect repairing portion is provided with a removal portion 12ea in which the semiconductor layer 12 is removed larger than the pinhole Ph in a portion overlapping with the pinhole Ph.
  • the semiconductor layer 12 is removed so that the inner peripheral end (inner wall W) is disposed outside the pinhole Ph in the portion overlapping the pinhole Ph of the gate insulating film 13.
  • the gate electrode 14ab is also formed along the depth direction of the pinhole Ph of the gate insulating film 13 extending only on the surface of the gate insulating film 13, but the semiconductor layer 12 is removed. It is formed in a non-contact manner on the inner wall W in the part that is formed.
  • the source electrode 16s is connected to the source region 12s of the semiconductor layer 12 through the first contact hole 21a formed in the gate insulating film 13 and the interlayer insulating film 15, as shown in FIG.
  • the drain electrode 16d is connected to the drain region 12d of the semiconductor layer 12 through the second contact hole 21b formed in the gate insulating film 13 and the interlayer insulating film 15, and
  • the pixel electrode 18 is connected through a third contact hole 21c formed in the flat film 17.
  • the gate electrode 14aa (14ab) is a protrusion protruding to the side of the gate line
  • the source electrode 16s is a protrusion protruding to the side of the source line.
  • the counter substrate 30 includes a color filter layer (not shown) provided on the insulating substrate, and a common electrode (not shown) provided on the color filter layer.
  • the color filter layer corresponds to each pixel electrode 18 on the active matrix substrate 20, for example, a plurality of colored layers (not shown) colored in red, green, or blue, respectively. And a black matrix (not shown) provided between the colored layers.
  • the liquid crystal layer 25 includes nematic liquid crystal having electro-optical characteristics.
  • the liquid crystal display device 50 configured as described above, in each pixel, when a gate signal is sent from the gate line to the gate electrode 14aa (14ab) and the TFT 5a (5b) is turned on, the source line A source signal is sent to the source electrode 16s, and a predetermined charge is written into the pixel electrode 18 via the semiconductor layer 12 and the drain electrode 16d. At this time, a potential difference is generated between each pixel electrode 18 of the active matrix substrate 20 and the common electrode of the counter substrate 30a, and a predetermined voltage is applied to the liquid crystal layer 25. In the liquid crystal display device 50, an image is displayed by adjusting the light transmittance of the liquid crystal layer 25 by changing the alignment state of the liquid crystal molecules according to the magnitude of the voltage applied to the liquid crystal layer 25.
  • the manufacturing method of the present embodiment includes a semiconductor layer forming process, a gate insulating film forming process, an oxide film etching process, a semiconductor layer etching process, a conductive film forming process, and a gate electrode forming process, an active matrix substrate manufacturing process, It includes a substrate manufacturing process and a liquid crystal display panel manufacturing process.
  • a silicon oxynitride film for example, a thickness of about 1000 A
  • a silicon oxide film for example, a thickness
  • the base coat film 11 is formed in order (see Fig. 4).
  • the amorphous silicon film 12a (e.g.,
  • amorphous silicon film 12a is melted and solidified by laser annealing or the like to form a polysilicon film (polycrystalline silicon film) 12b as shown in FIG.
  • the polysilicon film 12b is patterned by photolithography to form the semiconductor layer 12P (semiconductor layer forming step).
  • the semiconductor layer 12P may be formed by modifying the amorphous silicon film as described above, but a polycrystalline silicon film may be directly formed.
  • a silicon oxide film (for example, about 300 A thick) is formed on the entire substrate on the base coat film 11 on which the semiconductor layer 12P is formed by plasma CVD, and the first insulating film 13a is formed. A film is formed (see Fig. 7).
  • a silicon nitride film (for example, a thickness of about 400 A) is formed by plasma CVD so as to cover the first insulating film 13a, and a second insulating film 13b is formed (gate).
  • a pinhole Ph reaching the semiconductor layer 12P is formed in the gate insulating film 13 composed of the first insulating film 13a and the second insulating film 13b.
  • the surface of the semiconductor layer 12P exposed from the pinhole Ph of the gate insulating film 13 is
  • a natural oxide film (not shown) is formed.
  • the surface of the semiconductor layer 12P is self-etched by wet etching with hydrofluoric acid.
  • oxide film is removed (oxide film etching process).
  • wet etching is performed through pinhole Ph with an alkaline etching solution containing organic alkali such as tetraethylamine hydride (TMAH).
  • TMAH tetraethylamine hydride
  • the diameter of the pinhole Ph is, for example, 1
  • the diameter of the removal portion 12ea is about 2 / im.
  • a tantalum nitride film for example, about 500 A thickness
  • a tungsten film for example, about 3500 A thickness
  • the conductive film 14a is patterned by photolithography to form gate electrodes 14aa and 14ab and gate lines (gate electrode forming step).
  • the semiconductor layer 12P is doped with phosphorus through the gate insulating film 13, and a channel is formed in a portion overlapping the gate electrodes 14aa and 14ab.
  • a source region 12s and a drain region 12d are respectively formed in the region 12c and the outer portion thereof.
  • a silicon nitride film for example, about 2500 A thick
  • a silicon oxide film for example, thick
  • the interlayer insulating film 15 is formed in this order.
  • the portions corresponding to the source region 12s and the drain region 12d of the laminated film of the gate insulating film 13 and the interlayer insulating film 15 are etched, and as shown in FIG. 2, the first contact hole 21a and the second contact hole 21a Contact hole 21b is formed.
  • a titanium film eg, about 1000A thickness
  • an aluminum film eg, about 3500A thickness
  • a titanium film eg, thickness
  • a source electrode 16s, a source line, and a drain electrode 16d are respectively formed as shown in FIG.
  • an acrylic resin or the like is applied to the entire substrate on the interlayer insulating film 15 on which the source electrode 16s, the source line and the drain electrode 16d are formed to a thickness of about 1.6 ⁇ . 17 is formed.
  • an ITO (Indium Tin Oxide) film (for example, about 1000 A thick) is formed on the entire surface of the planarizing film 17 by sputtering, and then a pattern is formed by photolithography. Thus, the pixel electrode 18 is formed.
  • ITO Indium Tin Oxide
  • the active matrix substrate 20 of the present embodiment can be manufactured.
  • the alignment film 27a is formed by performing an alignment process on the surface by a rubbing method.
  • a chromium thin film (for example, about 1000 A thick) is formed on the entire substrate of an insulating substrate such as a glass substrate, and then a pattern is formed by photolithography to form a grid-like black matrix.
  • a color filter layer is formed by patterning a green or blue colored layer.
  • an ITO film (for example, about 1000 A thick) is formed on the entire substrate on the color filter layer to form a common electrode.
  • the counter substrate 30 of this embodiment can be manufactured. Thereafter, after a polyimide resin thin film is formed by the printing method, the alignment film 27b is formed by performing an orientation process on the surface by a rubbing method.
  • a seal portion 26 made of a thermosetting resin is formed on the active matrix substrate 20 by a printing method, and then spherical spacers are sprayed inside the formed seal portion 26.
  • the liquid is interposed between the active matrix substrate 20 and the counter substrate 30 by a decompression method.
  • the liquid crystal layer 25 is formed to produce a liquid crystal display panel.
  • polarizing plates 28a and 28b are attached to the front and back surfaces of the liquid crystal display panel, respectively.
  • the liquid crystal display device 50 of the present embodiment can be manufactured.
  • the semiconductor layer 12P is formed of the gate insulating film 13 in the semiconductor layer etching step.
  • the conductive film 14a constituting the gate electrodes 14aa and 14ab is formed in a non-contact manner on the semiconductor layer 12P. Then, in the gate electrode formation process,
  • the film 14a is patterned to form gate electrodes 14aa and 14ab.
  • the gate electrode 14ab formed through the conductive film formation step and the gate electrode formation step is not in contact with the inner wall W in the portion where the semiconductor layer 12P is removed in the semiconductor layer etching step, the gate electrode 14ab and The insulation between the semiconductor layers 12P can be maintained.
  • the semiconductor layer 12P is removed to be larger than the through hole Ph, and the insulation between the gate electrode 14ab and the semiconductor layer 12P is performed. This is due to the film thickness of the semiconductor layer 12 as in the past.
  • the defect level density at the interface between the gate insulating film 13 and the semiconductor layer 12P in the portion having the through hole Ph (defect repairing portion) and the gate insulating portion in the normal portion is reduced.
  • the difference between the defect level density at the interface between the edge film 13 and the semiconductor layer 12 is less likely to occur, the difference between the threshold value of the TFT 5b including the defect repairing portion and the threshold value of the TFT 5a not including the defect repairing portion is less likely to occur.
  • the semiconductor layer etching step it is possible to remove the portion of the semiconductor layer 12P that overlaps the through-hole Ph by etching and maintain the insulating property of the gate insulating film 13 as an acid.
  • the manufacturing method thereof, and the liquid crystal display device it is possible to suppress the deterioration of the characteristics of the TFT 5b due to the pinhole Ph of the gate insulating film 13 without reducing the productivity. it can.
  • the etching rate of the second insulating film 13b constituting the gate electrodes 14aa and 14ab side of the gate insulating film 13 with respect to hydrofluoric acid Is the semiconductor layer 12P of the gate insulating film 13
  • the first insulating film 13a constituting one side is lower than the first insulating film 13a, a through-hole is newly formed in the gate insulating film 13 composed of the first insulating film 13a and the second insulating film 13b by etching with hydrofluoric acid in the pretreatment. Formation can be suppressed.
  • the semiconductor layer 12P is isotropically etched with an alkaline etchant in the semiconductor layer etching step, the semiconductor layer 12P is formed on the gate insulating film 13 by The portion overlapping the through hole Ph can be removed larger than the through hole Ph.
  • the sputtered particles are deposited in the thickness direction of the gate insulating film 13 by sputtering in the conductive film forming step, whereby the gate electrodes 14aa and 14a b Conductive film 14a is formed on the semiconductor layer 12P in a non-contact manner.
  • FIG. 10 is a cross-sectional view showing a TFT 5c constituting the liquid crystal display device (active matrix substrate) of the present embodiment.
  • the TF in which defects due to the pinhole Ph are repaired is maintained.
  • the oxide film 12f between the inner wall W of the semiconductor layer 12 and the gate electrode 14ba the insulating property between the gate electrode 14ba and the semiconductor layer 12 is maintained.
  • the gate electrode 14ba in the TFT 5c is in contact with the oxide film 12f provided on the inner wall W of the semiconductor layer 12, but is not in contact with the inner wall W of the semiconductor layer 12. Therefore, the insulation with respect to the semiconductor layer 12 is maintained.
  • An active matrix substrate (liquid crystal display device) including the TFT 5c having the above structure is an oxide film described later between the semiconductor layer etching step and the conductive film forming step in the manufacturing method described in the first embodiment. Since it can be manufactured by adding a forming step, the following description of the manufacturing method will detail the steps before and after the oxide film forming step.
  • a semiconductor in which a natural oxide film is removed after an oxide film etching process is performed on a substrate (see FIG. 7) in which pinholes Ph are formed in the gate insulating film 13 described in the first embodiment.
  • an alkaline etching solution containing organic alkali such as monoethanolamine tetraethylamine hydride (TMAH)
  • TMAH monoethanolamine tetraethylamine hydride
  • the diameter of the pinhole Ph is, for example, about 1 / im, and the diameter of the removal portion 12eb is, for example, about 3 ⁇ m.
  • an oxide film 12f is formed as shown in FIG. 12 (oxide film formation step).
  • a tantalum nitride film eg, thickness of about 500A
  • a tungsten film eg, thickness of about 3500A
  • 14b is formed (conductive film formation step, see FIG. 13). At this time, as shown in FIG. 13, the conductive film 14b is in contact with the oxide film 12f formed on the inner wall W of the semiconductor layer 12P.
  • the conductive film 14b is patterned by photolithography to form the gate electrode 14ba and the like (a gate electrode formation step, see FIG. 10). Subsequently, using the gate electrode 14ba as a mask, the semiconductor layer 12P is passed through the gate insulating film 13.
  • a channel region 12c is formed in a portion overlapping with the gate electrode 14ba, and a source region 12s and a drain region 12d are formed in portions outside thereof, as shown in FIG.
  • the active matrix of the present embodiment is formed by forming the interlayer insulating film 15, the source electrode 16s, the drain electrode 16d, the planarizing film 17, the pixel electrode 18, and the like.
  • a substrate can be produced.
  • the liquid crystal display device of the present embodiment can be manufactured by performing the counter substrate manufacturing process and the liquid crystal display panel manufacturing process as in the first embodiment.
  • the position (retreat amount) of the inner wall W of the semiconductor layer 12P etched in the semiconductor layer etching step is assumed. Even if it varies, in the conductive film formation process,
  • the oxide film 12f is formed between the inner wall W of the semiconductor layer 12P and the gate electrode 14ba in the oxide film forming step.
  • the gate insulating film 13 is nitrided in order to suppress the formation of new pinholes in the gate insulating film 13 prior to the pretreatment for etching the natural oxide film.
  • a two-layer structure of silicon oxide film / silicon oxide film is illustrated. However, even if a new pinhole is formed in the gate insulating film 13 in the present invention, an oxide film is formed after that. Therefore, the insulation between the semiconductor layer 12 and the gate electrode 14ba can be maintained.
  • the present invention may be configured in such a manner that the conductive film 14b does not contact the oxide film 12f.
  • the present invention can effectively maintain the insulation between the gate electrode and the semiconductor layer, and thus is useful for liquid crystal display devices including TFTs and semiconductor devices in general.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Nonlinear Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un transistor à effet de champ (TFT) de type à grille supérieure (5b) comportant une couche semi-conductrice (12) disposée sur un substrat isolant (10), un film isolant de grille (13) disposé pour couvrir la couche semi-conductrice (12), et une électrode de grille (14ab) disposée sur le film isolant de grille (13). Un trou traversant (Ph) est formé dans le film isolant de grille (13) dans la direction de l'épaisseur, la couche semi-conductrice (12) est enlevée plus large que le trou traversant (Ph) à une partie chevauchant le trou traversant (Ph), et l'électrode de grille (14ab) n'est pas en contact avec la paroi interne (W) à une partie où la couche semi-conductrice (13) est enlevée.
PCT/JP2007/062523 2006-11-15 2007-06-21 Élément semi-conducteur, procédé de fabrication de celui-ci et affichage WO2008059633A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2006309551 2006-11-15
JP2006-309551 2006-11-15
JP2007141256 2007-05-29
JP2007-141256 2007-05-29

Publications (1)

Publication Number Publication Date
WO2008059633A1 true WO2008059633A1 (fr) 2008-05-22

Family

ID=39401447

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/062523 WO2008059633A1 (fr) 2006-11-15 2007-06-21 Élément semi-conducteur, procédé de fabrication de celui-ci et affichage

Country Status (1)

Country Link
WO (1) WO2008059633A1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010045369A (ja) * 2008-08-18 2010-02-25 Xerox Corp ピンホールアンダーカット部を含む装置と工程
CN103076703A (zh) * 2012-12-28 2013-05-01 南京中电熊猫液晶显示科技有限公司 一种液晶显示面板及其制造方法
WO2015096374A1 (fr) * 2013-12-23 2015-07-02 京东方科技集团股份有限公司 Substrat de réseau et procédé de fabrication associé, dispositif d'affichage et transistor à couches minces
US9653608B2 (en) 2013-12-23 2017-05-16 Boe Technology Group Co., Ltd. Array substrate and manufacturing method thereof, display device and thin film transistor
CN111863836A (zh) * 2019-04-29 2020-10-30 夏普株式会社 有源矩阵基板及其制造方法
US11543726B2 (en) * 2019-07-31 2023-01-03 Japan Display Inc. Display device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02206173A (ja) * 1989-02-06 1990-08-15 Nec Corp 多結晶薄膜トランジスタ

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02206173A (ja) * 1989-02-06 1990-08-15 Nec Corp 多結晶薄膜トランジスタ

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010045369A (ja) * 2008-08-18 2010-02-25 Xerox Corp ピンホールアンダーカット部を含む装置と工程
EP2157629A3 (fr) * 2008-08-18 2015-05-13 Samsung Electronics Co., Ltd. Dispositif et procédé impliquant une zone d'entaille de piqûre
CN103076703A (zh) * 2012-12-28 2013-05-01 南京中电熊猫液晶显示科技有限公司 一种液晶显示面板及其制造方法
CN103076703B (zh) * 2012-12-28 2015-11-25 南京中电熊猫液晶显示科技有限公司 一种液晶显示面板及其制造方法
WO2015096374A1 (fr) * 2013-12-23 2015-07-02 京东方科技集团股份有限公司 Substrat de réseau et procédé de fabrication associé, dispositif d'affichage et transistor à couches minces
US9653608B2 (en) 2013-12-23 2017-05-16 Boe Technology Group Co., Ltd. Array substrate and manufacturing method thereof, display device and thin film transistor
CN111863836A (zh) * 2019-04-29 2020-10-30 夏普株式会社 有源矩阵基板及其制造方法
CN111863836B (zh) * 2019-04-29 2024-03-26 夏普株式会社 有源矩阵基板及其制造方法
US11543726B2 (en) * 2019-07-31 2023-01-03 Japan Display Inc. Display device

Similar Documents

Publication Publication Date Title
JP5275519B2 (ja) 表示装置用基板及びその製造方法、表示装置
US20130023086A1 (en) Active matrix substrate, display panel provided with same, and method for manufacturing active matrix substrate
US7619256B2 (en) Electro-optical device and electronic apparatus
KR100884118B1 (ko) 전기 광학 장치, 전자 기기, 및 전기 광학 장치의 제조방법
JP5220308B2 (ja) 薄膜トランジスタアレイ基板及びその製造方法
WO2012020525A1 (fr) Substrat de transistor en couches minces, et dispositif d'affichage à cristaux liquides le comportant
JPH11249171A (ja) アクティブマトリクス型表示装置およびその作製方法
WO2012090432A1 (fr) Substrat de matrice active, son procédé de fabrication et panneau d'affichage
EP2521180A1 (fr) Substrat à matrice active et procédé de fabrication associé
WO2012117695A1 (fr) Dispositif à semi-conducteur et son procédé de production, et dispositif d'affichage
WO2008059633A1 (fr) Élément semi-conducteur, procédé de fabrication de celui-ci et affichage
JP2007116164A (ja) 薄膜トランジスタ基板とその製造方法、及びこれを有する液晶表示パネルとその製造方法
US9876039B2 (en) Thin-film transistor substrate, thin-film transistor substrate manufacturing method, and liquid crystal display
JP2010048887A (ja) 表示装置
WO2011161875A1 (fr) Substrat pour dispositif d'affichage ainsi que son procédé de production, et dispositif d'affichage
US20090073364A1 (en) Lateral electric-field type Liquid Crystal Display device and method of fabricating the same
JP6478819B2 (ja) 薄膜トランジスタ基板およびその製造方法
JP6584157B2 (ja) 薄膜トランジスタ、薄膜トランジスタ基板、液晶表示装置及び薄膜トランジスタの製造方法
JP6112886B2 (ja) 薄膜トランジスタアレイ基板およびその製造方法
JP2011222688A5 (fr)
US20080211981A1 (en) Display device
JP2008218626A (ja) Ｔｆｔアレイ基板及びその製造方法
JP4910706B2 (ja) 電気光学装置の製造方法
JP2011171437A (ja) 表示装置
JP4628393B2 (ja) アクティブマトリクス型液晶表示装置の作製方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07767349

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 07767349

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP