WO2008050635A1 - Structure de montage d'élément semiconducteur et procédé de montage d'élément semiconducteur - Google Patents
Structure de montage d'élément semiconducteur et procédé de montage d'élément semiconducteur Download PDFInfo
- Publication number
- WO2008050635A1 WO2008050635A1 PCT/JP2007/070170 JP2007070170W WO2008050635A1 WO 2008050635 A1 WO2008050635 A1 WO 2008050635A1 JP 2007070170 W JP2007070170 W JP 2007070170W WO 2008050635 A1 WO2008050635 A1 WO 2008050635A1
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- WIPO (PCT)
- Prior art keywords
- resin
- semiconductor element
- substrate
- gap
- mounting structure
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 316
- 238000000034 method Methods 0.000 title claims abstract description 54
- 229920005989 resin Polymers 0.000 claims abstract description 237
- 239000011347 resin Substances 0.000 claims abstract description 237
- 239000000758 substrate Substances 0.000 claims abstract description 192
- 238000007789 sealing Methods 0.000 claims abstract description 35
- 239000011800 void material Substances 0.000 claims abstract description 32
- 238000010438 heat treatment Methods 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims description 31
- 229920006223 adhesive resin Polymers 0.000 claims description 14
- 239000012945 sealing adhesive Substances 0.000 claims description 14
- 239000004088 foaming agent Substances 0.000 claims description 11
- 230000002093 peripheral effect Effects 0.000 claims description 10
- 230000008602 contraction Effects 0.000 abstract description 9
- 238000001816 cooling Methods 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 description 14
- 230000006378 damage Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 238000003825 pressing Methods 0.000 description 5
- 230000007423 decrease Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000009172 bursting Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
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- 230000008018 melting Effects 0.000 description 1
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- 238000004904 shortening Methods 0.000 description 1
- 239000003351 stiffener Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
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Definitions
- the element electrode of the semiconductor element and the substrate electrode of the substrate are connected via the protruding electrode, and a sealing adhesive resin is disposed between the semiconductor element and the substrate.
- the present invention relates to a semiconductor element mounting structure in which a semiconductor element is mounted on the substrate, and a semiconductor element mounting method.
- bare chip mounting is used as an electronic component that can greatly reduce the mounting area compared to conventional semiconductor packages
- the circuit formation surface of a semiconductor chip semiconductor element
- the circuit formation surface of a substrate In face-down mounting, where conduction is achieved by overlapping via bumps (projection electrodes) made of metal such as gold, the circuit formation surface of the substrate and the surface opposite to the circuit formation surface of the semiconductor chip face each other.
- face-up mounting where both terminals are connected by pulling out a thin metal wire by wire bonding, the entire semiconductor chip and its mounting structure can be further reduced in size and used widely.
- FIG. 13 shows a schematic plan view of such a conventional semiconductor chip mounting structure 501
- FIG. 14 shows a cross-sectional view taken along line AA in the mounting structure 501 of FIG.
- a pad 3 that is a plurality of element electrodes is formed on the circuit forming surface that is the lower surface side of the semiconductor chip 2 having a substantially square shape, and the upper surface side of the substrate 4.
- a plurality of substrate electrodes 5 are formed on the circuit forming surface.
- Each pad 3 and substrate electrode 5 are individually electrically connected via bumps 6 which are protruding electrodes individually formed on the pad 3.
- an underfill resin 7 is filled and disposed as an insulating resin for sealing and bonding, whereby each pad 3, the substrate electrode 5, and the bumps are arranged.
- a mounting structure in which the semiconductor chip 2 and the substrate 4 are bonded is formed!
- Such a mounting structure includes, for example, a substrate 4 having a bump 6 formed on each pad 3 of the semiconductor chip 2 and a sheet-like underfill resin 7 attached to the surface thereof.
- a so-called sheet method in which the semiconductor chip 2 is pressed against the substrate 4 through the underfill resin 7.
- the filling of the underfill resin 7 between the semiconductor chip 2 and the substrate 4 and the bumps between the pads 3 of the semiconductor chip 2 and the substrate electrodes 5 of the substrate 4 are performed. It is possible to perform electrical connection via 6 at the same time, which is effective in terms of simplifying the process and shortening the time, and is widely used.
- the thermal expansion coefficient of a semiconductor chip is extremely smaller than the thermal expansion coefficient of an underfill resin or a substrate, and the semiconductor is caused by a difference in thermal expansion or contraction of each member caused by heat treatment and cooling treatment during mounting.
- a large tensile load is generated at each part of the chip, particularly at a corner of a rectangular semiconductor chip.
- the semiconductor chip mounting process for example, when performing the cleaving process of the substrate after the semiconductor chip is mounted, that is, the cleaving process of the multi-sided board, the solder ball mounting process on the back surface of the substrate, etc.
- the generated mechanical load causes the substrate to bend, and the load on the semiconductor chip becomes even greater.
- an object of the present invention is to solve the above-described problem, and to connect an element electrode of a semiconductor element and a substrate electrode of a substrate via a protruding electrode, and to connect the semiconductor element and the substrate.
- a sealing adhesive resin is disposed between the semiconductor element mounted structure and the mounting method of the semiconductor element mounted on the substrate. It is possible to reduce the thermal expansion difference and thermal contraction difference of the members and the load generated in the corner portion of the semiconductor element due to the flexure of the substrate with respect to the mechanical load after mounting, and to avoid internal destruction of the mounting structure of the semiconductor element.
- An object of the present invention is to provide a mounting structure for a semiconductor element and a method for mounting a semiconductor element.
- the present invention is configured as follows.
- a semiconductor element having a plurality of element electrodes
- a substrate having a plurality of substrate electrodes
- a plurality of projecting electrodes connecting the respective element electrodes and the substrate electrode; and sealing each of the element electrodes, the substrate electrode, and the projecting electrode, and bonding the semiconductor element and the substrate.
- a sealing adhesive resin disposed between the semiconductor element and the substrate;
- a semiconductor element mounting structure in which a gap is formed in a position corresponding to the edge of the semiconductor element or in the vicinity thereof in the sealing adhesive resin.
- the semiconductor device according to the first aspect, wherein the void portion is a stress relaxation void portion that relieves stress generated in the resin by added external energy.
- An element mounting structure is provided.
- the void portion is formed at a position corresponding to or near a corner portion of the substantially rectangular semiconductor element! / A semiconductor device mounting structure is provided.
- the voids are a plurality of voids arranged in the resin immediately below all the corners of the substantially rectangular semiconductor element. state A mounting structure for a semiconductor device as described above is provided.
- the recess is formed on the substrate at a position facing the corner of the semiconductor element, and the space inside the recess is covered with the resin.
- the recess is formed at a position facing the corner of the semiconductor element on the substrate and is not connected to the element electrode.
- the semiconductor element mounting structure according to the fifth aspect is provided on the upper surface of the semiconductor device.
- the gap is formed at a position corresponding to the side part of the substantially rectangular semiconductor element or in the vicinity thereof! A mounting structure for semiconductor devices is provided.
- the gap portion includes all the positions corresponding to the four side portions or the vicinity thereof excluding the four corner portions and the vicinity thereof of the substantially rectangular semiconductor element.
- a mounting structure for a semiconductor device according to a seventh aspect is provided.
- the gap is formed as an annular gap at a position corresponding to the entire edge of the semiconductor element or in the vicinity thereof.
- a semiconductor element mounting structure according to one aspect is provided.
- the resin has a two-layer structure of first and second resin sheets
- the outer shape of the first resin sheet is formed such that the outer shape of the first resin sheet disposed on the substrate side is smaller than the outer shape of the second resin sheet disposed on the semiconductor element side.
- the semiconductor element mounting structure according to the first aspect wherein a space in contact with the second resin sheet is covered with the second resin sheet to form the gap.
- the semiconductor according to the tenth aspect wherein the outer shape of the first resin sheet is set to be substantially the same or smaller than the outer shape of the semiconductor element.
- An element mounting structure is provided.
- the viscosity of the resin material forming the first resin sheet is higher than the viscosity of the resin material forming the second resin sheet.
- the sealing adhesive resin is an insulating resin sheet or an anisotropic conductive resin sheet.
- a gap is formed between the substrate and the sealing connection resin at a position corresponding to the edge of the semiconductor element mounting region on the substrate or in the vicinity thereof.
- the semiconductor element is pressed against the substrate via the sealing connection resin, and the element electrodes of the semiconductor element and the substrate electrodes of the substrate are connected via the protruding electrodes.
- each of the element electrodes, the substrate electrodes, and the protruding electrodes are sealed with the resin.
- the sealing connecting resin is heated to expand the gap, and then the resin is cured, so that the void is located at a position corresponding to the edge of the semiconductor element or in the vicinity thereof in the sealing connecting resin.
- a method for mounting a semiconductor element is provided, in which a semiconductor element is formed and the semiconductor element is mounted on the substrate.
- the gap is formed at a position corresponding to the corner of the mounting region or in the vicinity thereof, and the sealing connection
- An element mounting method is provided.
- the space inside the recess formed in advance in the corner of the mounting region of the semiconductor element on the substrate is made of the resin.
- the recess is formed in the corner of the mounting region of the semiconductor element on the substrate, and the substrate electrode for forming a recess that is not connected to the element electrode.
- a method for mounting a semiconductor device according to the sixteenth aspect, which is formed on an upper surface, is provided.
- the eighteenth aspect of the present invention by arranging the resin on the surface of the substrate, the gap on the side portion of the mounting region is formed at a position corresponding to the vicinity thereof, By heating and curing the sealing connection resin, the void portion is formed in the sealing connection resin at a position corresponding to the side portion of the semiconductor element or the vicinity thereof.
- a method for mounting a semiconductor device according to the fourteenth aspect is provided.
- the wall member formed of an insulating resin material is disposed at a position inside the side part or the vicinity thereof in the mounting region of the semiconductor element.
- the sealing connecting resin is disposed on the surface of the substrate, and the gap is formed at a position corresponding to the side portion of the mounting region or the vicinity thereof.
- the flow of the sealing connecting resin heated and melted is suppressed by the wall member, thereby forming the void portion between the outer peripheral side surface of the wall member and the resin.
- a method for mounting the described semiconductor device is provided.
- a resin sheet having a two-layer structure of the first and second resin sheets is used as the resin, and the resin is arranged on the substrate side.
- An outer shape of the first resin sheet is formed smaller than an outer shape of the second resin sheet disposed on the semiconductor element side, and the first and second resin sheets are disposed on the substrate.
- the first resin sheet in the arrangement of the resin sheet having the two-layer structure, is configured such that the outer shape is set to be substantially the same as or smaller than the outer shape of the semiconductor element.
- a method for mounting a semiconductor device according to the twentieth aspect is provided.
- the viscosity of the resin material forming the first resin sheet is higher than the viscosity of the resin material forming the second resin sheet.
- a semiconductor device mounting method is provided.
- the sealing adhesive resin an insulating resin sheet or an anisotropic conductive resin sheet is used to place the resin on the substrate.
- a method for mounting a conductor element is provided.
- the foaming agent is disposed at a position corresponding to the edge of the semiconductor element mounting region on the substrate or in the vicinity thereof, and the resin is disposed on the surface of the substrate.
- the semiconductor element is pressed against the substrate via the sealing connection resin, and the element electrodes of the semiconductor element and the substrate electrodes of the substrate are connected via the protruding electrodes.
- each of the element electrodes, the substrate electrodes, and the protruding electrodes are sealed with the resin.
- a semiconductor element mounting method is provided in which a gap is formed at a position where the semiconductor element is to be mounted, and the semiconductor element is mounted on the substrate.
- the semiconductor element is mounted by disposing the gap in the sealing adhesive resin at a position corresponding to the corner of the semiconductor element.
- Differences in thermal expansion and contraction of each member caused by heat treatment and cooling treatment in the process, and stress load generated in the corner portion of the semiconductor element due to the deflection of the substrate with respect to mechanical load after the mounting process, Can be absorbed and reduced. Therefore, it is possible to avoid the destruction of the semiconductor element itself or the destruction inside the mounting structure of the semiconductor element.
- such voids can be formed relatively easily by forming recesses in advance on the substrate surface or using a resin sheet having a two-layer structure with different sizes. The process of mounting the semiconductor element on the substrate can be performed efficiently.
- FIG. 1 is a schematic cross-sectional view of a semiconductor chip mounting structure according to a first embodiment of the present invention
- FIG. 2 is a partial schematic plan view of the semiconductor chip mounting structure of FIG.
- FIG. 3 is a schematic view showing a method for manufacturing the semiconductor chip mounting structure of the first embodiment. It is a formula explanatory drawing, and is a figure showing the state where sheet-like underfill resin was pasted on a substrate,
- FIG. 4 is a schematic explanatory view showing a manufacturing method of the semiconductor chip mounting structure of the first embodiment, and shows a state in which the semiconductor chip is mounted on a substrate via an underfill resin.
- FIG. 5 is a partial schematic cross-sectional view of a semiconductor chip mounting structure according to a modification of the first embodiment
- FIG. 6 is a schematic cross-sectional view of a semiconductor chip mounting structure according to a second embodiment of the present invention.
- FIG. 7 is a schematic explanatory view showing a manufacturing method of the semiconductor chip mounting structure of the second embodiment, in which a sheet-like two-layer underfill resin is pasted on a substrate. It is a figure showing a state,
- FIG. 8 is a schematic explanatory view showing the manufacturing method of the semiconductor chip mounting structure of the second embodiment, wherein the semiconductor chip is mounted on the substrate via two layers of underfill resin. It is a figure which shows the state made,
- FIG. 9 is a partial schematic cross-sectional view of the semiconductor chip mounting structure of FIG. 6, and FIG. 10]
- FIG. 10 is a method for manufacturing a semiconductor chip mounting structure of the third embodiment of the present invention.
- FIG. 11 is a schematic explanatory view showing a state in which a foaming agent is applied on a substrate.
- FIG. 11 shows a method for manufacturing a semiconductor chip mounting structure according to the third embodiment.
- FIG. 2 is a schematic explanatory view showing a state in which a sheet-like underfill resin is pasted on a substrate;
- FIG. 12 is a schematic explanatory view showing a method for manufacturing a semiconductor chip mounting structure according to the third embodiment, and shows a state in which a semiconductor chip is mounted;
- FIG. 13 is a schematic plan view of a conventional semiconductor chip mounting structure.
- FIG. 14 is a cross-sectional view taken along line AA in the semiconductor chip mounting structure of FIG.
- FIG. 15 is a schematic plan view of a semiconductor chip mounting structure according to a modification of the second embodiment
- FIG. 16 is a schematic diagram of a semiconductor chip mounting structure according to the fourth embodiment of the present invention. It is an expression plan view,
- FIG. 17 is a schematic cross-sectional view of the semiconductor chip mounting structure of the fourth embodiment.
- FIG. 18 is a schematic plan view of a semiconductor chip mounting structure according to a fifth embodiment of the present invention.
- FIG. 19 is an enlarged schematic view of a portion A of the semiconductor chip mounting structure of the fifth embodiment.
- FIG. 20 is a partial schematic perspective view of an electrode pattern of the semiconductor chip mounting structure of FIG. 19,
- FIG. 21 is a schematic cross-sectional view of the semiconductor chip mounting structure of the fifth embodiment.
- FIG. 1 shows a schematic cross-sectional view of a semiconductor chip mounting structure 1 as an example of the semiconductor element mounting structure according to the first embodiment of the present invention
- FIG. 2 shows a partial schematic plan view thereof.
- a sheet-like underfill resin which is an example of a sealing adhesive resin on the substrate 4 7 is arranged, and the semiconductor chip 2 is mounted through the underfill resin 7.
- a plurality of pads 3 as an example of element electrodes are formed on the circuit forming surface on the lower surface side of the semiconductor chip 2 in the drawing, and the substrate 4 is shown so as to correspond to the positions where these pads 3 are formed.
- a plurality of substrate electrodes 5 are formed on the upper circuit forming surface, and each pad 3 is individually electrically connected to each substrate electrode 5 via bumps 6 which are examples of protruding electrodes. Has been.
- the underfill resin 7 is made of an insulating resin material, and is electrically connected to each pad 3, the substrate electrode 5, and the bump.
- the chip 6 is completely covered and sealed, and the semiconductor chip 2 and the substrate 4 are interposed and bonded to each other so that these connection states are maintained. In such a state, the semiconductor chip 2 is mounted on the substrate 4 to constitute a semiconductor chip mounting structure 1, that is, a semiconductor package component.
- the semiconductor chip 2 has a substantially square planar shape, and is a substrate that faces a rectangular corner (corner) of the semiconductor chip 2. 4, that is, the corner of the mounting area on which the semiconductor chip 2 is mounted on the substrate 4 (the area where the semiconductor chip 2 is projected onto the substrate surface) has a recess on its surface, and A recess-forming substrate electrode 8 made of the same material as the substrate electrode 5 (for example, copper) is formed.
- the recess-forming substrate electrode 8 is formed in a frame shape with a central portion hollowed out into a square shape, and a concave portion 8a is formed by the hollowed-out portion and the surface (upper surface) of the substrate 4. Has been.
- the recess 8 a is formed at a position facing the apex of the corner portion of the semiconductor chip 2. Furthermore, as shown in FIGS. 1 and 2, the recess-forming substrate electrode 8 is formed at all four corners of the semiconductor chip 2, and furthermore, the space inside each recess 8a. Is formed in the underfill resin 7 so that the space is expanded upward from the recess 8a. In other words, voids 9 are formed in the underfill resin 7 at positions corresponding to the four corners of the semiconductor chip 2. Note that these voids 9 are sealed in the underfill resin 7.
- a manufacturing method of such a semiconductor chip mounting structure 1 that is, a method of mounting the semiconductor chip 2 on the substrate 4, is a schematic cross-sectional view of the semiconductor chip 2 and the substrate 4 shown in FIGS. Will be described below.
- each substrate electrode 5 is formed at a predetermined position on the circuit forming surface, and the recess forming substrate electrode 8 is formed at a position corresponding to each corner of the mounting region of the semiconductor chip 2.
- the formed substrate 4 and the semiconductor chip 2 in which the respective pads 3 are formed at predetermined positions on the circuit formation surface and the bumps 6 are formed on the individual pads 3 are prepared.
- an underfill having a sheet-like form is formed on the circuit forming surface on the upper surface side of the substrate 4.
- Place resin 7. The underfill resin 7 is formed of, for example, a low dielectric insulating resin material (NCF) having thermosetting properties.
- NCF low dielectric insulating resin material
- the underfill resin 7 is disposed on the substrate 4 so as to cover the substrate electrode 5 and the recess forming substrate electrode 8. Further, in the state in which the underfill resin 7 is arranged in this way, the space sealed in the space where the underfinore resin 7 does not enter the space inside the recess 8a in each substrate electrode 8 for forming the recess. S 1 is formed. Also, as shown in FIG. 3, underfill resin 7 does not enter between the substrate electrode 5 and the recess forming substrate electrode 8 depending on the arrangement interval of the electrodes! /, When the gap S2 is formed. There is.
- NCF low dielectric insulating resin material
- each circuit board 4 and the circuit formation surface of the semiconductor chip 2 are opposed to each other as shown in FIG. Both are positioned so that the electrode 5 and the pad 3 are aligned, and then the semiconductor chip 2 starts to descend.
- the lowered semiconductor chip 2 is first formed on each pad 3! /,
- the lower end of the bump 6 is placed on the substrate 4! /,
- the underfill resin 7 is in contact with the lower chip 6. Further, when the semiconductor chip 2 is lowered, the bump 6 comes into contact with the substrate electrode 5 of the substrate 4 so as to push away the underfill resin 7.
- each pad 3 of the semiconductor chip 2 applies the bump 6 to each substrate electrode 5 of the substrate 4. Through an electrical connection.
- the pads 3, the substrate electrodes 5, and the bumps 6 are sealed with the underfill resin 7 in such a state that the electrical bonding is performed as described above.
- the lowering of the semiconductor chip 2 causes the circuit forming surface on the lower surface side of the semiconductor chip 2 to press the upper surface of the underfill resin 7.
- a relatively large pressure is applied to the underfill resin 7 disposed in the region immediately below the semiconductor chip 2 pressed by the semiconductor chip 2, that is, the mounting region of the semiconductor chip.
- the underfill resin 7 enters the gap S2 between the substrate electrode 5 and the recess forming substrate electrode 8 arranged in the mounting region, and the gap S2 disappears.
- the semiconductor chip is disposed outside the mounting area (or substantially at the outer edge of the area). Since the applied pressure is small in the void SI formed inside the recessed portion 8a, the void S1 in which the amount of the underfill resin 7 entering the void S1 is small is not lost and remains. become.
- the semiconductor chip 2 and the underfill resin 7 are heated.
- the underfill resin 7 is first brought into a molten state, and then the heating is further continued, whereby the molten underfill resin 7 is cured.
- the air in the void S1 remaining in the recess 8a expands, and the void S1 is expanded inside the underfill resin 7.
- the underfill resin 7 is cured in a state in which the gap S 1 is expanded and expanded, whereby a gap 9 is formed in each recess 8a as shown in FIG.
- the recess forming substrate electrode 8 can regulate the expansion direction so as to be easily directed upward.
- the semiconductor chip 2 is mounted on the substrate 4 via the underfill resin 7, and the semiconductor chip in which the voids 9 are formed at positions corresponding to the respective corner portions of the semiconductor chip 2 in the underfill resin 7.
- Mounting structure 1 is manufactured
- the semiconductor chip mounting structure 1 manufactured as described above is subjected to a subsequent heat treatment step, the semiconductor chip 2, the underfill resin 7, and the substrate 4 are thermally expanded. Although thermal contraction occurs, stress is generated due to the difference in the coefficient of thermal expansion of each member, and this stress is particularly noticeable at the corners. As shown in Fig. 1, the semiconductor chip mounting structure 1 In this case, since the gaps 9 are formed at the respective corners, the stress generated in the gaps 9 can be absorbed or reduced. Therefore, it is possible to reliably prevent the semiconductor chip 2 and its mounting structure 1 from being damaged due to thermal influence. Furthermore, such a semiconductor chip 2 is a so-called multi-sided substrate.
- a plurality of substrates are mounted on the substrate, and after mounting, the substrate is cut by the force that can be formed as the mounting structure 1 of each semiconductor chip, and the mechanical load applied during such a cutting process. Even if the deflection occurs, the gap portion 9 is deformed, so that the influence can be mitigated at each corner portion. Therefore, external energy applied such as thermal load and mechanical load can be relaxed in the respective gaps 9, that is, stress relaxation gaps. Use force S to prevent damage to chip 2 or peeling from underfill resin 7 in advance.
- Such a void 9 is sealed in the underfill resin 7 and formed as large as possible as long as it does not communicate with the other pads 3, the substrate electrodes 5, and the bumps 6. Load such as stress This is preferable from the viewpoint of relaxation. However, it is necessary not to disturb the strength that can sufficiently maintain the bonding state between the semiconductor chip 2 and the substrate 4. Thus, in order to secure the gap 9 with a sufficient size, for example, as shown in FIG. 5, the recess 18a of the recess-forming substrate electrode 18 formed on the substrate 4 is formed on the surface of the substrate 4. It is preferable to form it deeply so as to scrape off. Such scraping can be performed by laser machining, for example. Furthermore, as shown in FIG.
- the recess forming substrate electrode 8 is formed on the substrate 4 with the same material and the same height as the other substrate electrodes 5, for example, by photo-etching.
- substrate manufacture is simplified, the first embodiment is not limited to such a case.
- a concave portion forming member having a desired height can be formed by a plating process or the like.
- the semiconductor chip 2 has a planar outer size of 10 mm ⁇ 10 mm and a thickness of 200 m
- the substrate 4 has a planar outer size of 15 mm XI 5 mm and a thickness of 500 111.
- the dimension between the semiconductor chip 2 and the substrate 4 is 25 m
- the outer shape of the concave portion forming substrate electrode 8 is 100 m X 100 m
- the diameter of the concave portion 8a is 50 m X 50 mm
- FIG. 6 shows a schematic cross-sectional view of a semiconductor chip mounting structure 21 which is an example of a semiconductor chip mounting structure which is an example of a semiconductor element mounting structure according to the second embodiment of the present invention.
- the underfill resin force disposed on the substrate 4 is the first sealing adhesion disposed on the substrate 4 side.
- the first underfill resin 27, which is a resin sheet for use, and the second underfill resin 28, which is a second sealing adhesive resin sheet disposed on the semiconductor chip 2 side, have a two-layer structure.
- gap part 29, without forming a recessed part has a structure different from the said 1st Embodiment.
- a first underfill resin 27 having a sheet-like form is applied to the semiconductor chip mounting region on the substrate 4 on which the respective substrate electrodes 5 are formed at predetermined positions. Place and paste. By this pasting, each substrate electrode 5 is completely covered with the first underfill resin 27.
- the first underfill resin 27 is formed so that the size thereof is substantially the same as or smaller than the external dimension of the semiconductor chip 2, but at least each substrate electrode 5 on the substrate 4 is completely formed. It is formed in a size that can be covered.
- a second underfill resin 28 having a sheet-like form is disposed and pasted so as to cover the upper surface of the first underfill resin 27.
- the second underfill resin 28 is formed so as to be sufficiently larger than the outer shape of the semiconductor chip 2.
- the first underfill resin 27 and the second underfill resin 28 have, for example, the same material properties.
- Spatial force on the substrate 4 adjacent to the outer periphery of the resin 27 is formed with a void S3 that is covered with the second underfill resin 28 and sealed.
- the gap S3 is formed in a frame shape over the entire outer peripheral portion of the first underfill resin 27, for example.
- a space S3 is formed at a position corresponding to each corner.
- the semiconductor chip 2 is lowered in the same manner as in the mounting method of the first embodiment. As shown in FIG. 8, each pad 3 of the semiconductor chip 2 is electrically connected individually to each substrate electrode 5 of the substrate 4 via the bump 6.
- the semiconductor chip 2 and the respective underfill resins 27 and 28 are heated during this joining process, the air in the gap S3 expands due to this heating, and the gap is enlarged, as shown in FIG. As shown in the drawing, the expanded and expanded gap 29 is formed in a frame shape. Note that the first and second underfill resins 27 and 28 are hardened as an integral layer by heating and subsequent cooling in the joining step, and the shape of the gap 29 is maintained. In this way, the semiconductor chip mounting structure 21 of the second embodiment is formed.
- FIG. 9 a partial schematic cross-sectional view of the semiconductor chip mounting structure 21 formed in this way is shown in FIG.
- the resin material constituting the underfill resin is melted by heating in the bonding process, and the resin flows into a molten state by the pressing force of the semiconductor chip 2.
- the gap S3a formed at a position corresponding to the end portion other than the corner portion of the semiconductor chip 2 has a relatively large resin flow at the position, so the gap S3a becomes smaller.
- the formed void S3b has a relatively small resin flow at the position, the void S3b does not decrease, and a relatively large void 29 can be formed.
- FIG. 15 shows a schematic plan view of the semiconductor chip mounting structure 41 in this case as a modification of the second embodiment. As shown in FIG. 15, the gap 49 is formed at a position corresponding to the entire circumference of the edge of the semiconductor chip 2.
- the thermal load and the mechanical load are alleviated by the respective gaps 29.
- the power S can be made.
- the semiconductor chip mounting structure 41 of the above-described modified example which is formed over the entire periphery of the semiconductor chip 2 in such a void portion force S, a frame shape formed only by the corner portion of the semiconductor chip 2,
- the frame-shaped air gap 49 can relieve thermal and mechanical loads not only at the corners but also near the other edges, more reliably damage the semiconductor chip 2 and underfill resin 27, 28 It is possible to prevent the occurrence of peeling off.
- the mounting structure 21 of the second embodiment has a configuration in which two layers having different sizes are overlapped with each other to form a recess as in the first embodiment.
- the gap 29 can be formed
- the first underfill resin 27 and the second underfill resin 28 have the same physical properties, but the second embodiment is for such a case. It is not limited only. Instead of such a case, for example, the first underfill resin 27 is made of a material having a relatively high viscosity and a viscosity, and the second underfill resin 28 is made of a material having a relatively low viscosity. It may be. As described above, the first underfill resin 27 disposed on the substrate side and the second underfill resin 28 disposed on the semiconductor chip 2 side are positively and positively applied to increase and decrease the viscosity S3. Forming power S is possible.
- the viscosity of the first underfill resin 27 during heat bonding (resin melting) is 300000 Pa's and the viscosity of the second underfill resin 28 during heat bonding to 10 OOOPa's. it can.
- the outer peripheral end portion of the first underfill resin 27 is formed so as to be located 50 m inside from the outer peripheral end surface of the semiconductor chip 2.
- the outer peripheral end portion force of the underfill resin 28 may be formed so as to be positioned 500 m outside the outer peripheral end surface of the semiconductor chip 2.
- the underfill resins 27 and 28 may have the same thickness of 25 m, for example, and the thickness S can be set in accordance with the size of the gap to be formed.
- FIG. 10 The mounting structure 31 of the third embodiment is different from the first and second embodiments in that a foaming agent is used as a means for forming voids in the underfill resin.
- a foaming agent 38 is applied on the substrate 4 at a position where a gap is to be formed, that is, a position corresponding to a corner portion in the mounting region of the semiconductor chip 2. Or it arrange
- the semiconductor chip 2 is bonded to the substrate 4 via the underfill resin 7.
- the foaming agent 38 in the underfill resin 7 is foamed, and then the resin is cured, whereby the void 39 is formed.
- a foaming agent 38 it is possible to select a material having a characteristic that foams at a temperature lower than the temperature at which the underfill resin 7 is melted and solidified (cured) (for example, about 100 ° C.). I like it.
- a foaming agent is applied to a predetermined position on the substrate 4 to form a void at the position. Therefore, it is possible to reliably form a gap at a desired position, and it is not necessary to process the substrate itself, and it is not necessary to make the resin sheet multilayered.
- the semiconductor chip mounting structures according to the first to third embodiments described above have an effect of reducing the load on the semiconductor chip 2 and the mounting structure alone, they are used in combination. Therefore, it is expected to increase the size of the void and obtain further load reduction effect.
- the semiconductor chip 2 has a substantially square shape, and is located at a position corresponding to each corner portion (that is, part of the four corners) in the underfill resin.
- the force S described in the case where a void is formed, and the present invention is not limited to such a case.
- the effect of the present invention can be obtained by forming a gap at least at one of the four corners. Also, by forming a gap at only one of the opposing corners and absorbing the load at one of the corners, the load at the opposite corner is also reduced. You can also.
- each resin material preferably has a sheet-like form from the standpoint of its alignment, but is not limited to such a form.
- each resin material has a paste-like form. It may be.
- the position at which the gap is disposed is preferably a position immediately below the apex of the corner of the semiconductor chip, but the gap is pushed by the applied pressure when the semiconductor chip is joined, In consideration of the fact that a larger stress is generated outside the part, it may be formed so as to extend slightly outside the corner part.
- the semiconductor chip mounting structure 51 of the fourth embodiment the semiconductor chip 2 is positioned at a position corresponding to the corner portion.
- the semiconductor chip 2 has a structure in which the gap is formed along the positions corresponding to the four side portions.
- the corner portions of the substantially square semiconductor chip 2 and the vicinity thereof are directly under the four side portions, respectively.
- Four gaps 59 are formed so as to extend along the side edges of the two.
- each wall member 61 that similarly extends along the side portion is formed on the center side of the semiconductor chip 2 in each gap portion 59.
- each wall member 61 is formed on the upper surface of the substrate 4 by an insulating resin, and is surrounded by the outer peripheral side surface of the wall member 61, the underfill resin 7, and the surface of the substrate 4.
- a space is formed as a gap 59.
- each wall member 61 suppresses the flow of the underfill resin 7, thereby
- the gap 59 can be formed so as to be adjacent to the outer peripheral side surface of the member 61. Even if the wall member 61 that suppresses the flow of the underfill resin 7 is formed in this way, the wall member 61 is not disposed at a position corresponding to each corner portion. It can flow around the chip 2, especially around the corners, so that reliable sealing is not hindered.
- each wall member 61 is formed such that its end is positioned away from the corner of the semiconductor chip 2 by, for example, about 100 inches.
- the wall member 61 is formed to have a width of 50 m, and its inner peripheral side surface is located at a position about 60 ⁇ m inside from the side portion of the semiconductor chip 2.
- the height of the wall member 61 is 20 in with respect to the dimension 40 m between the semiconductor chip 2 and the substrate 4.
- a material for forming the wall member 61 an insulating material is used. If so, other materials such as a solder resist material can be used.
- the thermal load and the mechanical load can be alleviated by the respective gap portions 59. Even when such a gap 59 is formed along the four side portions of the semiconductor chip 2 that is not in the corner portion of the semiconductor chip 2, the gap 59 forms the side of the semiconductor chip 2. It is possible to reduce the thermal load and mechanical load at the side, and to reduce the thermal load and mechanical load generated at each corner. Therefore, it is possible to prevent the occurrence of breakage of the semiconductor chip 2 or peeling from the underfill resin 7 in advance.
- a mounting structure 71 for a semiconductor chip which focuses on the fifth embodiment of the present invention, will be described below with reference to schematic explanatory views shown in FIGS.
- a plurality of gaps are divided along the positions corresponding to the four side parts of the semiconductor chip 2, that is, a structure formed intermittently. have.
- the semiconductor chip mounting structure 51 of the fourth embodiment the case where the gap 59 is formed using the wall member 61 formed of an insulating resin material has been described.
- the substrate electrode 5 formed on the substrate 4 or a part of the electrode pattern is used to form a member having a function similar to such a wall member and intermittently. A typical void is formed!
- FIG. 19 is a schematic partial enlarged view in which part A in FIG. 18 is enlarged
- FIG. 20 which is a schematic perspective view thereof
- FIG. 21, which is a schematic cross-sectional view. This will be specifically described.
- a plurality of substrate electrodes 5 that are electrically connected to the pads 3 of the semiconductor chip 2 via the bumps 6 are formed on the substrate 4.
- Each substrate electrode 5 is electrically connected to an electrode pattern 72 formed so as to expand radially toward the outer periphery of the substrate 4.
- the electrode pattern 72 is a force that is formed so as to extend flat along the surface of the substrate 4 so as not to contact other members such as the semiconductor chip 2.
- a raised portion 73 is formed in a part of the raised portion 73, and the raised portion 73 is provided with the function as the wall member of the fourth embodiment.
- Each electrode pattern 72 is formed with a width of 40 m with an interval of 40 in, for example, between the adjacent electrode patterns 72.
- the raised portion 73 is preferably formed at a position slightly inside the side portion of the semiconductor chip 2. By forming the raised portion 73 at such a position, the gap portion 79 can be formed so as to be in contact with the side surface of the raised portion 73 located in the outer side direction of the semiconductor chip 2.
- the semiconductor chip 2 can be positioned directly below the side portion.
- the height of the bump 6 is about 25 m and the height of the electrode pattern 72 is about 12 m
- the height of the raised portion 73 is preferably formed to be about 20 m. . By forming it at such a height, contact between the raised portion 73 and the semiconductor chip 2 can be reliably prevented.
- the thermal load and the mechanical load are intermittently formed along the side portions of the semiconductor chip 2.
- Each of the gaps 79 can reduce the thermal load and mechanical load on the side portion of the semiconductor chip 2, and accordingly, the thermal load generated at each corner portion can be reduced. Mechanical load can be reduced. Therefore, damage to the semiconductor chip 2 and peeling from the underfill resin 7 can be prevented in advance.
- the semiconductor chip mounting structure has been described with respect to the case where the cavity is arranged symmetrically with respect to the center of the semiconductor chip 2.
- the effect of the present invention can be obtained even when the gaps are asymmetrically arranged due to the shape of 2 and other manufacturing reasons.
- each gap is not limited to being formed in a sealed state, but may be a case where a part of communication with the outside exists in a part thereof. In this way, when there is a communicating portion, it is possible to obtain the effect of suppressing bubble bursting during the bubble growth process by heating. Such communication parts are as small as possible. It is desirable to do.
- the semiconductor chip mounting structure of the present invention provides a gap in the underfill resin at the corner portion of the semiconductor chip, thereby providing a difference in thermal expansion and contraction of each component caused by heating and cooling processes during mounting.
- it is useful because it can reduce the load generated at the corners of the semiconductor chip due to the flexure of the substrate with respect to the mechanical load after mounting, and avoid internal damage.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008540945A JP5066529B2 (ja) | 2006-10-19 | 2007-10-16 | 半導体素子の実装構造体及び半導体素子の実装方法 |
US12/445,793 US8106521B2 (en) | 2006-10-19 | 2007-10-16 | Semiconductor device mounted structure with an underfill sealing-bonding resin with voids |
CN200780038929.1A CN101529584B (zh) | 2006-10-19 | 2007-10-16 | 半导体元件的安装结构体及半导体元件的安装方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006-284895 | 2006-10-19 | ||
JP2006284895 | 2006-10-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2008050635A1 true WO2008050635A1 (fr) | 2008-05-02 |
Family
ID=39324434
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2007/070170 WO2008050635A1 (fr) | 2006-10-19 | 2007-10-16 | Structure de montage d'élément semiconducteur et procédé de montage d'élément semiconducteur |
Country Status (4)
Country | Link |
---|---|
US (1) | US8106521B2 (ja) |
JP (1) | JP5066529B2 (ja) |
CN (1) | CN101529584B (ja) |
WO (1) | WO2008050635A1 (ja) |
Cited By (1)
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WO2020017205A1 (ja) * | 2018-07-19 | 2020-01-23 | ソニーセミコンダクタソリューションズ株式会社 | 撮像素子および電子機器 |
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US8143110B2 (en) * | 2009-12-23 | 2012-03-27 | Intel Corporation | Methods and apparatuses to stiffen integrated circuit package |
JP2013000359A (ja) * | 2011-06-16 | 2013-01-07 | Toshiba Corp | 内視鏡装置および電子機器 |
JP2015119077A (ja) * | 2013-12-19 | 2015-06-25 | ソニー株式会社 | 半導体装置およびその製造方法 |
JP6671835B2 (ja) * | 2014-04-18 | 2020-03-25 | キヤノン株式会社 | プリント回路板 |
CN105047083B (zh) * | 2014-04-29 | 2019-03-15 | 群创光电股份有限公司 | 显示面板 |
WO2015198911A1 (ja) * | 2014-06-26 | 2015-12-30 | ソニー株式会社 | 半導体装置および半導体装置の製造方法 |
US9502368B2 (en) | 2014-12-16 | 2016-11-22 | Intel Corporation | Picture frame stiffeners for microelectronic packages |
US10249515B2 (en) * | 2016-04-01 | 2019-04-02 | Intel Corporation | Electronic device package |
US20180288270A1 (en) * | 2017-03-30 | 2018-10-04 | Canon Components, Inc. | Sensor unit, reading apparatus, and image forming apparatus |
US10622270B2 (en) * | 2017-08-31 | 2020-04-14 | Texas Instruments Incorporated | Integrated circuit package with stress directing material |
US10553573B2 (en) | 2017-09-01 | 2020-02-04 | Texas Instruments Incorporated | Self-assembly of semiconductor die onto a leadframe using magnetic fields |
JP6890520B2 (ja) * | 2017-10-04 | 2021-06-18 | 三菱電機株式会社 | 電力用半導体装置 |
US10886187B2 (en) | 2017-10-24 | 2021-01-05 | Texas Instruments Incorporated | Thermal management in integrated circuit using phononic bandgap structure |
US10833648B2 (en) | 2017-10-24 | 2020-11-10 | Texas Instruments Incorporated | Acoustic management in integrated circuit using phononic bandgap structure |
WO2019082928A1 (ja) * | 2017-10-25 | 2019-05-02 | 京セラ株式会社 | 熱電モジュール |
US10557754B2 (en) | 2017-10-31 | 2020-02-11 | Texas Instruments Incorporated | Spectrometry in integrated circuit using a photonic bandgap structure |
US10371891B2 (en) | 2017-10-31 | 2019-08-06 | Texas Instruments Incorporated | Integrated circuit with dielectric waveguide connector using photonic bandgap structure |
US10444432B2 (en) | 2017-10-31 | 2019-10-15 | Texas Instruments Incorporated | Galvanic signal path isolation in an encapsulated package using a photonic structure |
US10497651B2 (en) | 2017-10-31 | 2019-12-03 | Texas Instruments Incorporated | Electromagnetic interference shield within integrated circuit encapsulation using photonic bandgap structure |
JP7236807B2 (ja) * | 2018-01-25 | 2023-03-10 | 浜松ホトニクス株式会社 | 半導体装置、及び半導体装置の製造方法 |
JP7087495B2 (ja) | 2018-03-16 | 2022-06-21 | 株式会社デンソー | パワー半導体装置、それを備える回転電機、及び、パワー半導体装置の製造方法 |
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WO2007015683A1 (en) * | 2005-08-04 | 2007-02-08 | Infineon Technologies Ag | An integrated circuit package and a method for forming an integrated circuit package |
US8237293B2 (en) * | 2009-11-25 | 2012-08-07 | Freescale Semiconductor, Inc. | Semiconductor package with protective tape |
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2007
- 2007-10-16 US US12/445,793 patent/US8106521B2/en not_active Expired - Fee Related
- 2007-10-16 WO PCT/JP2007/070170 patent/WO2008050635A1/ja active Application Filing
- 2007-10-16 JP JP2008540945A patent/JP5066529B2/ja not_active Expired - Fee Related
- 2007-10-16 CN CN200780038929.1A patent/CN101529584B/zh not_active Expired - Fee Related
Patent Citations (2)
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JPH1126654A (ja) * | 1997-06-30 | 1999-01-29 | Denso Corp | 樹脂封止型半導体装置及びその製造方法 |
JP2001127194A (ja) * | 1999-10-28 | 2001-05-11 | Sharp Corp | フリップチップ型半導体装置及びその製造方法 |
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WO2020017205A1 (ja) * | 2018-07-19 | 2020-01-23 | ソニーセミコンダクタソリューションズ株式会社 | 撮像素子および電子機器 |
Also Published As
Publication number | Publication date |
---|---|
JPWO2008050635A1 (ja) | 2010-02-25 |
US20110001233A1 (en) | 2011-01-06 |
CN101529584B (zh) | 2010-09-08 |
US8106521B2 (en) | 2012-01-31 |
CN101529584A (zh) | 2009-09-09 |
JP5066529B2 (ja) | 2012-11-07 |
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