WO2008029800A1 - Procédé de traitement de substrat et support de stockage - Google Patents
Procédé de traitement de substrat et support de stockage Download PDFInfo
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- WO2008029800A1 WO2008029800A1 PCT/JP2007/067206 JP2007067206W WO2008029800A1 WO 2008029800 A1 WO2008029800 A1 WO 2008029800A1 JP 2007067206 W JP2007067206 W JP 2007067206W WO 2008029800 A1 WO2008029800 A1 WO 2008029800A1
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- Prior art keywords
- substrate processing
- processing method
- film
- substrate
- substance
- Prior art date
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- 239000000758 substrate Substances 0.000 title claims abstract description 89
- 238000003672 processing method Methods 0.000 title claims abstract description 43
- 238000003860 storage Methods 0.000 title claims description 23
- 239000000126 substance Substances 0.000 claims abstract description 92
- 238000000034 method Methods 0.000 claims abstract description 80
- 238000006884 silylation reaction Methods 0.000 claims abstract description 78
- 230000008569 process Effects 0.000 claims abstract description 56
- 239000007788 liquid Substances 0.000 claims abstract description 53
- 238000005530 etching Methods 0.000 claims abstract description 52
- 230000004048 modification Effects 0.000 claims abstract description 34
- 238000012986 modification Methods 0.000 claims abstract description 34
- 238000012545 processing Methods 0.000 claims description 128
- 239000003795 chemical substances by application Substances 0.000 claims description 28
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 28
- 238000004090 dissolution Methods 0.000 claims description 27
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 23
- KZFNONVXCZVHRD-UHFFFAOYSA-N dimethylamino(dimethyl)silicon Chemical compound CN(C)[Si](C)C KZFNONVXCZVHRD-UHFFFAOYSA-N 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 15
- KAHVZNKZQFSBFW-UHFFFAOYSA-N n-methyl-n-trimethylsilylmethanamine Chemical compound CN(C)[Si](C)(C)C KAHVZNKZQFSBFW-UHFFFAOYSA-N 0.000 claims description 8
- GJWAPAVRQYYSTK-UHFFFAOYSA-N [(dimethyl-$l^{3}-silanyl)amino]-dimethylsilicon Chemical group C[Si](C)N[Si](C)C GJWAPAVRQYYSTK-UHFFFAOYSA-N 0.000 claims description 7
- 150000001875 compounds Chemical class 0.000 claims description 7
- 125000000217 alkyl group Chemical group 0.000 claims description 6
- 230000002378 acidificating effect Effects 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 description 148
- 238000004140 cleaning Methods 0.000 description 50
- 239000007789 gas Substances 0.000 description 42
- 238000012546 transfer Methods 0.000 description 32
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 17
- 239000010949 copper Substances 0.000 description 16
- 239000006227 byproduct Substances 0.000 description 13
- 239000011248 coating agent Substances 0.000 description 13
- 238000000576 coating method Methods 0.000 description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 11
- 229910052802 copper Inorganic materials 0.000 description 11
- 230000009977 dual effect Effects 0.000 description 11
- 230000007246 mechanism Effects 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 10
- 229920000642 polymer Polymers 0.000 description 9
- 238000011084 recovery Methods 0.000 description 9
- 210000000078 claw Anatomy 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 7
- 230000032258 transport Effects 0.000 description 7
- FFUAGWLWBBFQJT-UHFFFAOYSA-N hexamethyldisilazane Chemical compound C[Si](C)(C)N[Si](C)(C)C FFUAGWLWBBFQJT-UHFFFAOYSA-N 0.000 description 6
- 239000010410 layer Substances 0.000 description 6
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 6
- 229910052757 nitrogen Inorganic materials 0.000 description 6
- 238000001816 cooling Methods 0.000 description 5
- 230000007423 decrease Effects 0.000 description 5
- 238000004925 denaturation Methods 0.000 description 5
- 230000036425 denaturation Effects 0.000 description 5
- 229910001873 dinitrogen Inorganic materials 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000011161 development Methods 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 239000006200 vaporizer Substances 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
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- 238000011068 loading method Methods 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 238000010926 purge Methods 0.000 description 3
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 3
- 238000005406 washing Methods 0.000 description 3
- 229910018557 Si O Inorganic materials 0.000 description 2
- 150000001412 amines Chemical class 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 239000007888 film coating Substances 0.000 description 2
- 238000009501 film coating Methods 0.000 description 2
- 229910010272 inorganic material Inorganic materials 0.000 description 2
- 239000011147 inorganic material Substances 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 244000132059 Carica parviflora Species 0.000 description 1
- 235000014653 Carica parviflora Nutrition 0.000 description 1
- 201000004029 Immune dysregulation-polyendocrinopathy-enteropathy-X-linked syndrome Diseases 0.000 description 1
- XCOBLONWWXQEBS-KPKJPENVSA-N N,O-bis(trimethylsilyl)trifluoroacetamide Chemical compound C[Si](C)(C)O\C(C(F)(F)F)=N\[Si](C)(C)C XCOBLONWWXQEBS-KPKJPENVSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 239000005441 aurora Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000012993 chemical processing Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
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- 238000009826 distribution Methods 0.000 description 1
- 230000003028 elevating effect Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 125000002887 hydroxy group Chemical group [H]O* 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- QULMGWCCKILBTO-UHFFFAOYSA-N n-[dimethylamino(dimethyl)silyl]-n-methylmethanamine Chemical compound CN(C)[Si](C)(C)N(C)C QULMGWCCKILBTO-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
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- 230000009467 reduction Effects 0.000 description 1
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- 238000007789 sealing Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005063 solubilization Methods 0.000 description 1
- 230000007928 solubilization Effects 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67075—Apparatus for fluid treatment for etching for wet etching
- H01L21/6708—Apparatus for fluid treatment for etching for wet etching using mainly spraying means, e.g. nozzles
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
- H01L21/67225—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process comprising at least one lithography chamber
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02137—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising alkyl silsesquioxane, e.g. MSQ
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
Definitions
- the present invention executes a substrate processing method for performing a modification process for modifying a predetermined substance and a dissolution removal process for the modified substance in a manufacturing process of a semiconductor device by a dual damascene method or the like, and such a method.
- the present invention relates to a storage medium that stores a program for executing the program.
- FIG. 1 is an explanatory diagram for explaining a series of steps for forming a multilayer copper wiring by a dual damascene method.
- a lower wiring 202 made of copper is formed on a low dielectric constant film (low-k film) 200, which is an insulating film made of a low-k material, on a silicon substrate (not shown) through a NORA metal layer 201.
- a low-k film 204 is formed as an interlayer insulating film through an etching stopper film 203, and an antireflection film (BARC; Bottom Anti-Reflective Coating) 205 is formed on the surface of the antireflection film 205.
- a resist film 206 is formed on the surface, and then the resist film 206 is exposed in a predetermined pattern and developed to form a circuit pattern on the resist film 206 (step (a)).
- the low-k film 204 is etched using the resist film 206 as a mask to form a via hole 204a (step (b)).
- a sacrificial film 207 is formed on the surface of the insulating film 204 having the via hole 204a (step (c)).
- the via hole 204a is also filled with the sacrificial film 207.
- a resist film 208 is formed on the surface of the sacrificial film 207, the resist film 208 is exposed in a predetermined pattern, and developed to form a circuit pattern in the resist film 208 (step (d)). .
- the sacrificial film 207 and the low-k film 204 are etched using the resist film 208 as a mask, thereby forming a wider trench 204b on the via hole 204a (step (e)). Thereafter, by removing the resist film 208 and the sacrificial film 207, a via hole 204a and a trench 204b are formed in the insulating film 204 (step (f)). And copper is embedded in these as upper wiring.
- Si—O-based inorganic materials are frequently used as the sacrificial film 207, and it is difficult to remove the sacrificial film 207 by ashing treatment used for conventional resist film removal. In addition, the power that has been tried to dissolve with chemicals is extremely slow.
- Japanese Patent Application Laid-Open No. 2006-049798 discloses that after etching or removing a resist film, the surface of the damaged part is modified with a silylating agent to form a methyl group.
- a silylation treatment with an alkyl group as a terminal group has been proposed, and this technique can be applied to recover damage after the washing treatment or modification treatment.
- An object of the present invention is to provide a substrate processing method capable of sufficiently recovering the k value even when the k value of the low dielectric constant film is increased due to damage caused by the modification treatment and the subsequent dissolution treatment. It is to provide.
- Another object is to provide a storage medium storing a program for executing such a manufacturing method.
- the low dielectric constant film formed on the substrate is etched to form a predetermined pattern, and the material remaining after the etching is finished is predetermined.
- Denatured so as to be solubilized in the liquid, supplying the predetermined liquid to dissolve and remove the denatured substance, and then dissolving the denatured substance in low dielectric constant
- a substrate processing method comprising supplying a silylating agent to the surface of the rate film and performing a silylation treatment, and beta-treating the substrate after the silylation treatment.
- a sacrificial film is formed on a low dielectric constant film formed on a substrate, an etching mask is formed on the sacrificial film, and the sacrificial film is formed.
- a substrate processing method is provided that includes betating the substrate.
- the surface of the low dielectric constant film on which the pattern is formed is silanolized after the remaining substance is modified and before the modified substance is dissolved and removed. It is possible to have a further process step. Further, a porous low dielectric constant material is suitable as the low dielectric constant film. As the low dielectric constant film, one having an alkyl group as a terminal group can be used.
- the modification of the remaining substance can be performed by supplying a processing gas containing water vapor and ozone. Further, the modification of the remaining substance can be performed by supplying a processing gas containing ozone.
- a processing gas containing ozone As the predetermined liquid, an acidic or alkaline chemical liquid can be used.
- a compound having a silazane bond (Si—N) in the molecule can be used, and as a compound having a silazane bond in the molecule.
- TMDS (1,1,3,3-Tetramethyldisilazane
- TMSDMA Dimethyla minotrimethylsilane
- DMSDMA Dimethylsilyldimethylamine
- the beta of the substrate is preferably performed at a temperature higher than that of the silylation treatment step S, and specifically, it is preferably performed at 150 to 400 ° C. Furthermore, a beta treatment may be performed prior to the silylation treatment.
- the etching target film has a film to be etched, a predetermined pattern is formed on the etching film by the etching process, and the substance remaining after the etching process is solubilized in the predetermined liquid.
- a silylation treatment is performed by supplying a silylating agent to the surface of the film to be etched on the substrate on which the modified substance is dissolved and removed by the predetermined liquid, and the silylation treatment is performed. And a substrate processing method is provided.
- a storage medium that operates on a computer and stores a program for controlling the substrate processing apparatus, and the program is stored on the substrate at the time of execution.
- a storage medium is provided that allows a computer to control the substrate processing apparatus such that a substrate processing method is performed that includes betating the substrate after the silylation process.
- a storage medium that operates on a computer and stores a program for controlling a substrate processing apparatus.
- a substrate processing method comprising: processing and betalying the substrate after the silylation treatment;
- a storage medium for controlling the processing device is provided.
- a storage medium that operates on a computer and stores a program for controlling the substrate processing apparatus.
- a predetermined pattern is formed on the film to be etched by the etching process, the substance remaining after the etching process is modified so as to be solubilized in the predetermined liquid, and the modified substance by the predetermined liquid
- a substrate processing method is performed which includes supplying a silylating agent to the surface of the film to be etched and silylating the substrate from which the substrate has been dissolved and removing, and beta-treating the substrate after the silylation processing.
- the silylation treatment is performed after the dissolution treatment after the modification treatment, and then the substrate is baked, the low dielectric constant film whose relative dielectric constant (k value) is reduced due to damage is obtained.
- the k value can be recovered sufficiently. That is, after the dissolution treatment, the low dielectric constant film contains moisture, and a Si-based byproduct is formed by the reaction between the moisture and the silylating agent. Since this Si-based by-product has a high k value, even if the silylation process recovers damage using an alkyl group such as a methyl group as a terminal group, the k value does not decrease sufficiently as a result. .
- FIG. 1 is an explanatory diagram for explaining a series of steps for forming a multilayer copper wiring by a conventional dual damascene method.
- FIG. 2 is an explanatory diagram showing a schematic configuration of a wafer processing system used in a semiconductor device manufacturing process by a dual damascene method, to which a substrate processing method is applied according to an embodiment of the present invention.
- FIG. 3 is a plan view showing a schematic structure of a cleaning processing apparatus used in the wafer processing system of FIG. 4 is a front view showing a schematic structure of a cleaning processing apparatus used in the wafer processing system of FIG.
- FIG. 5 is a rear view showing a schematic structure of a cleaning processing apparatus used in the wafer processing system of FIG.
- FIG. 6 is a schematic cross-sectional view showing a denaturing treatment unit mounted on a cleaning treatment apparatus.
- FIG. 7 is a schematic cross-sectional view showing a silylation unit mounted on a cleaning treatment apparatus.
- FIG. 8 is a schematic sectional view showing a cleaning unit mounted on the cleaning processing apparatus.
- FIG. 9 is a schematic cross-sectional view showing a hot plate unit mounted on a cleaning processing apparatus.
- FIG. 10 is a flowchart showing a semiconductor device manufacturing process by a dual damascene method to which the substrate processing method is applied according to an embodiment of the present invention.
- FIG. 11 is an explanatory diagram for explaining the state of each process shown in the flowchart of FIG.
- FIG. 12 A diagram for explaining damage of a low-k film and recovery by silylation.
- FIG. 2 is an explanatory diagram showing a schematic configuration of a wafer processing system used in a semiconductor device manufacturing process by a dual damascene method, to which a substrate processing method is applied according to an embodiment of the present invention.
- This wafer processing system includes a SOD (Spin On Dielectric) device 101, a resist coating / developing device 102, an exposure device 103, a cleaning processing device 104, an etching device 105, and a sputtering device that is one of PVD devices.
- a processing unit 100 including an apparatus 106, an electrolytic plating apparatus 107, and a CMP apparatus 109 as a polishing apparatus, and a main control unit 110 including a process controller 111, a user interface 112, and a storage unit 113 are provided.
- the SOD device 101, the sputtering device 106, and the electrolytic plating device 107 of the processing unit 100 are film forming devices.
- a transport method by an operator, an unillustrated transport, or a transport method by a transport device is used as a method for transporting the wafer W between the apparatuses of the processing unit 100.
- Each device of the processing unit 100 is connected to and controlled by a process controller 111 having a CPU.
- the process controller 111 the process manager A user interface 112 consisting of a keyboard that performs command input operations to manage each device, a display that visualizes and displays the operating status of each device in the processing unit 100, and various types of processing executed by the processing unit 100 Connected to the storage unit 113 storing a recipe in which a control program, processing condition data, and the like for realizing the processing by the control of the process controller 111 are stored.
- an arbitrary recipe is called from the storage unit 113 and executed by the process controller 111, so that the processing unit 111 is controlled under the control of the process controller 111.
- the recipe may be stored in a readable storage medium such as a CD-ROM, a hard disk, a flexible disk, or a nonvolatile memory. Alternatively, it can be transmitted online from an external device, for example via a dedicated line, and used online.
- the main control unit 110 does not perform overall control, or the main control unit 1
- control unit including a process controller, a user interface, and a storage unit is individually provided for each device of the processing unit 100 to perform control.
- the SOD device 101 is used for applying a chemical solution to the wafer W to form an interlayer insulating film such as a low-k film, an etching stagger film, or the like by a spin coating method.
- the SOD apparatus 101 includes a spin coater unit and a heat treatment unit for heat treating the wafer W on which the coating film is formed.
- a CVD apparatus that forms an insulating film or the like on the wafer W by chemical vapor deposition (CVD) may be used instead of the SOD apparatus 101.
- the resist coating / developing apparatus 102 is used for forming a resist film, an antireflection film, or the like used as an etching mask. Although the detailed configuration of the resist coating / developing apparatus 102 is not illustrated, the resist coating / developing apparatus 102 includes a resist coating processing unit that applies a resist solution or the like to the wafer W and spin-coats a resist film, and the wafer W.
- Development processing unit for developing the resist film exposed in step 1 and thermal processing for thermally processing the wafer w on which the resist film is formed, the wafer W that has been subjected to the exposure processing, and the wafer W that has been subjected to the development processing.
- the exposure device 103 is used for exposing a predetermined circuit pattern to the wafer W on which a resist film is formed.
- the cleaning processing apparatus 104 performs a cleaning process using pure water or a chemical solution, a modification process such as a polymer residue after the etching process, and a recovery process from damage caused by etching the interlayer insulating film.
- the etching apparatus 105 is for performing an etching process on an interlayer insulating film or the like formed on the wafer W.
- the etching process may use plasma or may use a chemical solution.
- the sputtering apparatus 106 is used, for example, to form a diffusion prevention film or a Cu seed.
- Cu is embedded in a trench wiring or the like in which a Cu seed is formed, and the CMP apparatus 109 is used for planarizing the surface of the trench wiring or the like in which Cu is embedded.
- FIG. 3 is a schematic plan view of the cleaning processing apparatus 104
- FIG. 4 is a schematic front view thereof
- FIG. 5 is a schematic rear view thereof.
- the carrier in which the wafer W is accommodated is sequentially loaded from another processing apparatus or the like, and conversely, the carrier in which the wafer W that has been processed in the cleaning processing apparatus 104 is processed is subjected to the next processing.
- the wafers W are accommodated in a substantially horizontal posture at regular intervals in the vertical direction (Z direction).
- Such loading / unloading of the wafer W to / from the carrier C is performed through one side surface of the carrier C, and this side surface is the lid 10a (not shown in FIG. 3.
- the state where the lid 10a is removed in FIGS. 4 and 5) Can be opened and closed freely.
- carrier station 4 has carrier C at three locations along the Y direction in the figure. It has a mounting table 6 on which can be mounted.
- the carrier C is placed on the placing table 6 such that the side surface on which the lid 10a is provided faces the boundary wall 8a between the carrier station 4 and the transfer station 3.
- a window portion 9a is formed at a position corresponding to the place where the carrier C is placed on the boundary wall 8a, and a shirter 10 that opens and closes the window portion 9a is provided on the transfer station 3 side of each window portion 9a.
- This shirter 10 has a gripping means (not shown) for gripping the lid 10a of the carrier C. As shown in FIG. 4 and FIG. 5, the gripper 10a is gripped on the conveyance station 3 side. The lid 10a can be retracted.
- the wafer transfer device 7 provided in the transfer station 3 has a wafer transfer pick 7a capable of holding the wafer W.
- the wafer transfer device 7 is movable in the Y direction along a guide 7b (see FIGS. 4 and 5) provided on the floor of the transfer station 3 so as to extend in the Y direction. Further, the wafer transfer pick 7a is slidable in the X direction, can be moved up and down in the Z direction, and is rotatable ( ⁇ rotation) in the XY plane.
- the wafer transfer pick 7a is mounted on the mounting table 6 in a state in which the shirter 10 is retracted so that the inside of the carrier C and the transfer station 3 communicate with each other through the window 9a. All the placed carriers C are accessible, and the wafer W at any height in the carrier C can be unloaded from the carrier C. Conversely, the wafer W can be loaded at any position on the carrier C. can do.
- the processing station 2 has two wafer mounting units (TRS) 13 a and 13 b on the transfer station 3 side.
- the wafer placement unit (TRS) 13b is used to place the wafer W when receiving the wafer W at the transfer station 3 force
- the wafer placement unit (TRS) 13a is Used to place the wafer W when the processed wafer W is returned to the transfer station 3.
- the polymer residue after the etching process, the resist film, the sacrificial film, and the like are solubilized in a predetermined chemical solution with a gas containing water vapor and ozone (O 2).
- Modification processing units (VOS) 15a to 15f for modification are arranged as described above.
- VOS Modification processing units
- the shape of the polymer residue after etching and the resist film, sacrificial film, etc. are maintained as they are, and only their chemical properties are solubilized in a predetermined chemical solution. Change.
- a silylation unit (for silylation treatment for recovering the interlayer insulating film damaged by the modification treatment and the cleaning treatment from damage) SCH) 11a, 1 lb is provided!
- a cleaning unit (VOS) 15a to 15f is a cleaning unit that removes the modified polymer residues and the like by subjecting the wafer W, which has been processed, to chemical treatment or water washing treatment.
- CNU) 12a-12d are arranged! /
- the silylation process was performed with the silylation units (SCH) 11a and l ib at the positions facing the wafer placement units (TRS) 13a and 13b across the main wafer transfer device 14.
- Hot plate units (HP) 19a to 19d that heat and dry the wafers W that have been processed in the later beta and cleaning processing units (CNU) 12a to 12d are arranged in four layers.
- cooling plate units (COU 21a, 21b) for cooling the heat-dried wafer W are stacked on the upper side of the wafer mounting unit (TRS) 13a. 13b can be used as a cooling plate unit, and a fan filter unit (FFU) 25 for blowing clean air inside the processing station 2 is provided above the processing station 2.
- FFU fan filter unit
- a main wafer transfer device 14 that transfers the wafer W in the processing station 2 is provided at a substantially central portion of the processing station 2.
- the main wafer transfer device 14 has a wafer transfer arm 14a for transferring the wafer W.
- the main wafer transfer device 14 is rotatable around the Z axis. Further, the wafer transfer arm 14a can move back and forth in the horizontal direction and can move up and down in the Z direction. With this structure, the main wafer transfer device 14 can access each unit provided in the processing station 2 without moving itself in the X direction, and transfer the wafer W between these units. I am able to do that.
- the chemical station 5 includes a processing gas supply unit 16 for supplying ozone, water vapor and the like as processing gases to the modification processing units (VOS) 15a to 15f provided in the processing station 2, and a cleaning unit (CNU) 12a.
- the cleaning liquid supply unit 17 supplies the cleaning liquid to ⁇ 12d
- the silylating agent supply unit 18 supplies silylating agent, carrier gas, and the like to the silylation processing units (SCH) 11a and ib.
- This denaturation processing unit (VOS) 15a has a closed chamber 30 that accommodates the wafer W.
- the chamber 30 is composed of a fixed lower container 41a and a lid 41b that covers the upper surface of the lower container 41a.
- the lid 4 lb can be moved up and down by a cylinder 43 fixed to the frame 42 of the membrane modification processing unit (VOS) 15a.
- FIG. 6 shows a state in which the lid 41b is in close contact with the lower container 41a, and a state in which the lid 41b is retracted above the lower container 41a.
- An O-ring 51 is disposed on the upper surface of the rising portion at the periphery of the lower container 41a.
- the lid 43b is lowered by driving the cylinder 43, the back surface periphery of the cover body 41b comes into contact with the upper surface of the rising portion of the periphery of the lower container 41a, and the O-ring 51 is compressed and sealed in the chamber 30.
- a processing space is formed.
- the lower container 41a is provided with a stage 33 on which the wafer W is placed.
- Proximity pins 44 for supporting the wafer W are provided at a plurality of locations on the surface of the stage 33.
- a heater 45a is embedded in the stage 33, and a heater 45b is embedded in the lid 41b, respectively, so that the stage 33 and the lid 41b can be held at predetermined temperatures respectively. The As a result, the temperature of the wafer W is kept constant.
- claw members 46 for holding the wafer W are provided, for example, at three locations (only two locations are shown in FIG. 6).
- Wafer transfer arm 14a delivers wafer W to claw member 46.
- the wafer W is transferred to the proximity pins 44 provided on the stage 33 during the lowering.
- the lower container 41a is provided with a gas inlet 34a for introducing a processing gas into the interior and a gas outlet 34b for exhausting the processing gas to the outside.
- the processing gas supply device 16 is connected to the gas inlet 34a, and the exhaust device 32 is connected to the gas outlet 34b.
- the processing of the wafer W with the processing gas is preferably performed while the inside of the chamber 30 is maintained at a constant positive pressure.
- the lower container 41a and the lid 41b are pressed by the cylinder 43.
- the projections 47a and 47b provided on these end faces are simply tightened by the lock mechanism 35.
- the lock mechanism 35 includes a support shaft 52 and a rotating cylinder that is rotatable by a rotating device 54.
- the clamping member 57 includes pressing rollers 59a and 59b and a roller holding member 48 that holds the rotating shaft 58.
- the projecting portions 47a, 47b are provided at four force points at equal intervals, and a gap portion 49 is formed between them.
- the protrusions 47a and 47b are disposed at overlapping positions. In a state where the clamping member 57 is disposed at the position of the gap portion 49, the force S can move the lid 41b up and down freely.
- the silylation unit (SCH) 11a includes a chamber 61 that accommodates a wafer W.
- the chamber 61 includes a fixed lower container 61a and a lid 61b that covers the lower container 61a. It can be raised and lowered by a lifting device (not shown).
- the lower container 61a is provided with a hot plate 62, and the surrounding force of the hot plate 62 and nitrogen gas containing a silylating agent such as DMSD MA (Dimethylsilyldimethylamine) vapor are supplied into the chamber 61. Yes. DMSDMA is vaporized by vaporizer 63 and carrier into N gas
- the temperature of the hot plate 62 can be adjusted, for example, in the range of room temperature to 400 ° C., and pins 64 that support the wafer W are provided on the surface thereof. By not placing the wafer W directly on the hot plate 62, contamination of the back surface of the wafer W is prevented.
- a first seal ring 65 is provided on the upper surface of the outer periphery of the lower container 61a, and the lower surface of the outer periphery of the lid 61b contacts the first seal ring 65 when the lid 61b is pressed against the lower container 61a.
- a second scenario 66 is provided. The space between these first and second seal rings 65, 66 is Depressurization is possible, and the airtightness of the chamber 61 is ensured by depressurizing this space.
- An exhaust port 67 for exhausting nitrogen gas containing DMSDMA supplied to the chamber 61 is provided in the substantially central portion of the lid 61b. The exhaust port 67 is evacuated via a pressure adjusting device 68. Connecte
- liquid DMSDMA gas is vaporized by the vaporizer 63, and N gas is used.
- the force S supplied as a carrier and supplied to the chamber 61 may be configured to supply the chamber 61 with only the gas S (ie, DMSDMA vapor) vaporized from the DMSDMA.
- the chamber 61 When supplying DMSDMA into the chamber 61, the chamber 61 is maintained at a predetermined degree of vacuum. Therefore, the DMSDMA gas is introduced into the chamber 61 using the pressure difference between the vaporizer 63 and the chamber 61. Can be done easily.
- the cleaning unit (CNU) 12a has an annular cup (CP) disposed at the center thereof, and a spin chuck 71 disposed inside the cup (CP).
- the spin chuck 71 is rotationally driven by a drive motor 72 in a state where the wafer W is fixed and held by vacuum suction.
- a drain pipe 73 is provided at the bottom of the cup (CP) to discharge cleaning liquid and pure water.
- the drive motor 72 is disposed in an opening 74a provided in the unit bottom plate 74 so as to be movable up and down, and is coupled to a lift drive mechanism 76 and a lift guide 77 made of, for example, an air cylinder via a cap-shaped flange member 75.
- a lift drive mechanism 76 and a lift guide 77 made of, for example, an air cylinder via a cap-shaped flange member 75.
- a cylindrical cooling jacket 78 is attached to the side surface of the drive motor 72, and the flange member 75 is attached so as to cover the upper half of the cooling jacket 78.
- the elevating drive mechanism 76 lifts the drive motor 72 and the spin chuck 71 upward so that the lower end of the flange member 75 is moved from the unit bottom plate 74. It ’s floating.
- a denaturing treatment unit (VOS) 15a to 15f Above the cup (CP), a denaturing treatment unit (VOS) 15a to 15f; A cleaning liquid supply mechanism 80 for supplying a predetermined cleaning liquid for dissolving the denatured substance is provided on the surface of the wafer W on which the denatured substance (hereinafter referred to as a denatured substance), for example, a denatured sacrificial film is present.
- a denatured substance for example, a denatured sacrificial film is present.
- the cleaning liquid supply mechanism 80 includes a cleaning liquid discharge nozzle 81 that discharges the cleaning liquid onto the surface of the wafer W held by the spin chuck 71, a cleaning liquid supply unit 17 that supplies a predetermined cleaning liquid to the cleaning liquid discharge nozzle 81, and a cleaning liquid. It is attached to a scanarm 82 that holds the discharge nozzle 81 and is movable back and forth in the Y direction, a vertical support member 85 that supports the scan arm 82, and a guide rail 84 that is laid in the X-axis direction on the unit bottom plate 74. And an X-axis drive mechanism 86 that moves the vertical support member 85 in the X-axis direction.
- the scan arm 82 can be moved in the vertical direction (Z direction) by the Z-axis drive mechanism 87. This allows the cleaning liquid discharge nozzle 81 to be moved to an arbitrary position on the wafer W, and also to move to a predetermined position outside the cup (CP). It can be retracted to the position.
- the cleaning liquid supply unit 17 includes, as a rinsing liquid, a dissolution removal liquid such as dilute hydrofluoric acid and an amine chemical liquid that dissolves a denatured substance such as a sacrificial film modified by a denaturation treatment unit (VOS) 15a to 15f.
- a dissolution removal liquid such as dilute hydrofluoric acid
- an amine chemical liquid that dissolves a denatured substance such as a sacrificial film modified by a denaturation treatment unit (VOS) 15a to 15f.
- VOS denaturation treatment unit
- the hot plate unit (HP) 19a used for the beta treatment after the silylation treatment will be described in detail with reference to the schematic cross-sectional view shown in FIG.
- the hot plate units (HP) 19b to 19d have exactly the same structure.
- the hot plate unit (HP) 19a includes a processing chamber 91 formed in a substantially cylindrical shape, and a wafer mounting table 92 is provided at the bottom of the processing chamber 91.
- a heater 93 is embedded in the wafer mounting table 92, whereby the wafer W on the wafer mounting table 92 is subjected to heat treatment such as beta treatment after silylation.
- a heater power supply 94 is connected to the heater 93.
- a wafer lift pin (not shown) is provided on the wafer mounting table 93 so as to protrude and retract, and the wafer W is positioned at a predetermined position above the wafer mounting table 92 when the wafer W is loaded and unloaded.
- a wafer loading / unloading port (not shown) is provided on the side wall 91a of the chamber 91.
- An air inlet 95 is provided at a position corresponding to the wafer W placed on the stage 92 on the side wall 91a of the chamber 91, and an air outlet 96 is provided at the center of the top wall 91b of the chamber 91. But Is provided.
- the modification unit (VOS) 15a to 15c and the modification unit (VOS) 15d to 15f described above have a substantially symmetrical structure with respect to the boundary wall 22b, and the silylation unit (SCH) 1 la and the silylation unit (SCH) 1 lb have a nearly symmetrical structure on the boundary wall 22b.
- the cleaning units (CNU) 12a, 12b and the cleaning units (CNU) 12c, 12d are connected to the boundary wall 22a!
- FIG. 10 is a flowchart showing the manufacturing process of the semiconductor device by the dual damascene method
- FIG. 11 is an explanatory diagram for explaining the state of each process shown in the flowchart of FIG.
- an insulating film 120 is formed on a Si substrate (not shown), and a lower copper wiring 122 is formed above the insulating film 120 via a barrier metal layer 121.
- the insulating film 120 and the lower copper wiring 122 A wafer W having a stopper film (for example, SiN film, SiC film) 123 formed thereon is formed, and this wafer W is loaded into the SOD device 101, where a low dielectric constant material (A), An interlayer insulating film (hereinafter referred to as a low-k film) 124 made of a low-k material is formed (step 1). As a result, the state shown in FIG. 11A is formed.
- the wafer W on which the low-k film 124 is formed is carried into the resist coating / developing apparatus 102, where the anti-reflection film 125,
- the resist film 126 is sequentially formed, and then the wafer W is transported to the exposure apparatus 103, where it is subjected to exposure processing in a predetermined pattern, and the wafer W is returned to the resist coating / developing apparatus 102, in the development processing unit.
- a predetermined circuit pattern is formed on the resist film 126 by developing the resist film 126 (step 2).
- the wafer is transferred to the etching apparatus 105, where etching is performed (step 3).
- a via hole 124a reaching the stopper film 123 is formed in the low-k film 124.
- the wafer W on which the via hole 124a has been formed is then transferred to the cleaning processing apparatus 104, where it is subjected to chemical processing in any of the cleaning processing units (CNU) 12a to 12d, and the wafer is processed.
- the resist film 126 and the antireflection film 125 are removed from W (step 4, FIG. 11 (c)).
- the wafer W is transferred to the resist coating / developing apparatus 102, where an inorganic material (for example, Si) is formed on the surface of the low-k film 124 having the via hole 124a using a sacrificial film coating processing unit.
- an inorganic material for example, Si
- Sacrificial film 127 made of an O-based material is formed (step 5).
- the via hole 124 a is also filled with the sacrificial film 127.
- a resist film 128 serving as an etching mask is formed on the surface of the sacrificial film 127 in the resist coating processing unit, the resist film 128 is exposed in a predetermined pattern in the exposure device 103, and then the resist film 128 is developed in the development processing unit.
- Develop (Step 6).
- a circuit pattern is formed on the resist film 128 as shown in FIG.
- a groove wider than the width of the via hole 124a is formed in the resist film 128 above the via hole 124a.
- the wafer W is transferred to the etching apparatus 105, where the low-k film 124 of the wafer W is subjected to an etching process (step 7).
- a wider trench 124b is formed above the via hornore 124a.
- the wafer W that has been subjected to the etching process is transferred to the cleaning processing apparatus 104, where the sacrificial film 127 and the resist film 128 are modified (step 8, FIG. 11 (f)), the sacrificial film 127, and the resist film. 128 and the polymer residue are removed (step 9, FIG. 11 (g)).
- the carrier C containing the wafer after the etching process is placed on the placing table 6, and the lid 10a and the shirter 10 of the carrier C are retracted to the transport station 3 side. As a result, the window 9a is opened. Subsequently, one wafer W at a predetermined position of the carrier C is transferred to the wafer placement unit (TRS) 13b by the wafer transfer pick 7a.
- TRS wafer placement unit
- the wafer placed on the wafer placement unit (TRS) 13b is carried into one of the modification processing units (VOS) 15a to 15h by the wafer transfer arm 14a, and the sacrificial film in the above step 8
- the modification process of 127 and the resist film 128 is performed ((f) in FIG. 11).
- the lid 41b of the chamber 30 is first withdrawn above the lower container 41a, and then the portion of the claw member 46 provided on the lid 41b for holding the wafer W (horizontal direction) The wafer W so that the wafer W enters a position slightly higher than The held wafer transfer arm 14a is entered. Next, when the wafer transfer arm 14a is lowered, the wafer W is delivered to the claw member 46.
- the lid 41b After retracting the wafer transfer arm 14a from the modification processing unit (VOS) 15a, the lid 41b is lowered, the lid 41b is brought into close contact with the lower container 41a, and the lock mechanism 35 is operated. Chamber 30 is sealed. The wafer W is transferred from the claw member 46 to the proximity pin 44 while the lid 41b is being lowered.
- VOS modification processing unit
- the stage 33 and the lid 41b are held at a predetermined temperature by the heaters 45a and 45b.
- the stage 33 is held at 100 ° C
- the lid 41b is held at 110 ° C.
- stage 33 and the lid 41b are maintained at a predetermined temperature (for example, 110 ° C to 120 ° C) and the temperature distribution of the wafer W becomes substantially constant, first, the processing gas supply device 16 To supply ozone / nitrogen mixed gas (for example, ozone content is 9wt%, flow rate is 4L / min) into chamber 30, chamber 30 is filled with ozone / nitrogen mixed gas, and Then, a predetermined positive pressure, for example, a gauge pressure is adjusted to 0.2 MPa.
- ozone / nitrogen mixed gas for example, ozone content is 9wt%, flow rate is 4L / min
- a processing gas in which water vapor is mixed with ozone / nitrogen mixed gas (for example, the amount of water vapor is 16 ml / min in terms of water) is supplied from the processing gas supply device 16 into the chamber 30.
- the sacrificial film 127 formed on the wafer W by this processing gas is denatured to be easily dissolved in a specific chemical solution, for example, HF, and polymer residues (for example, etching process) adhering to the resist film 128 and the wafer W are modified. Later polymer residues) are also easily dissolved by the chemical solution.
- the processing gas modifies the sacrificial film 127, the resist film, and the polymer residue.
- the supply amount of the processing gas to the chamber 30 and the exhaust amount from the chamber 30 are adjusted so that the inside of the chamber 30 has a predetermined positive pressure.
- the internal pressure of the chamber 30 is the same as the external pressure. This is the case when the internal pressure of chamber 30 is higher than atmospheric pressure. This is because opening the yamba 30 may damage the chamber 30.
- the locking of the lower container 41a and the lid 41b by the lock mechanism 35 is released, and the lid 4 lb is raised.
- the lid 41b is raised, the wafer W is held by the claw member 46 and rises together with the lid 41b. Wafer transfer arm 14a is moved into the gap between lower container 41a and lid 41b, and wafer W is transferred from claw member 46 to wafer transfer arm 14a.
- the sacrificial film 127 and the like are not removed from the wafer W at the time when the modification treatment in any of the modification processing units (VOS) 15a to 15f is completed. Therefore, a dissolution removal process (cleaning process) for removing the sacrificial film 127 and the like from the wafer W is performed (step 9 above).
- the wafer W is transported onto one spin chuck 71 of the cleaning units (CNU) 12a to 12d, and is adsorbed and held in a substantially horizontal posture.
- a chemical solution in which a denatured substance such as a sacrificial film 127 can be dissolved is supplied from the cleaning liquid discharge nozzle 81 to the surface of the wafer W to form a paddle, and after a predetermined time has elapsed, the wafer W is rotated to start the chemical from the surface of the wafer W. Shake off. Further, while rotating the wafer W, a chemical solution is supplied to the surface of the wafer W to completely remove the sacrificial film 127 and the like.
- the resist film 128 and polymer residue are also dissolved and removed by the chemical solution used to remove the sacrificial film 127 and the like.
- pure water is supplied to the wafer W while the wafer W is rotated by the drive motor 72, the wafer W is washed with water, and the wafer W is rotated at a high speed to perform spin drying.
- the wafer W may be spin-dried while supplying a drying gas to the wafer W.
- a damaged portion 130 as shown in FIG. 11G is formed on the surface portion of the low-k film 124.
- the damaged portion 130 is a portion where the low-k film 124, which was initially hydrophobic, was damaged and hydrophilized by the dissolution and removal treatment of step 9, and the relative dielectric constant of the low-k film 124 was increased.
- the parasitic capacitance between the wirings increases after the wirings are formed, resulting in problems in electrical characteristics such as signal delay and deterioration in insulation between the trench wirings.
- the damaged part 130 formed in the low-k film 124 is clearly shown for convenience. The boundary between force S, damaged part 130 and non-damaged part is not always clear.
- the silylation process is performed after the dissolution removal process in Step 9 (Step 10, (h) in FIG. 11), and the damage of the damaged portion 130 of the low-k film 124 is recovered. .
- such a damaged portion has a low-k film 124 whose end group is a methyl group (Me) and is hydrophobic during the modification treatment and dissolution removal treatment with water vapor and ozone.
- This is the part where the methyl group near the side wall of the via hole 124a has decreased due to the reaction with water molecules and the hydroxyl group has increased, which increases the relative dielectric constant (k value). For this reason, it is possible to recover the damage by applying a silinolation treatment to make the surface of the low-k membrane hydrophobic.
- the wafer W is transferred to one of the silylation units (SCH) 11a and ib and placed on the support pins 64 on the hot plate 62, and a silylating agent, for example, DMSDMA vapor is supplied.
- a silylating agent for example, DMSDMA vapor is supplied.
- N gas is introduced into the chamber 61 as a carrier.
- the temperature of the vaporizer 63 is from room temperature to 50 ° C
- the flow rate of the silylating agent is from 0 ⁇ 6 to ⁇ ⁇ Og / min
- the flow rate of N gas (purge gas) is ;! ⁇ 10L / m
- the processing pressure is 532 to 95976? & (4 to 720 0 ), and the temperature of the hot plate 62 can be set as appropriate from the range of room temperature to 200 ° C.
- the temperature of the hot plate 62 is set to 100 ° C.
- a method may be used in which the pressure is supplied until the pressure reaches 55 Torr and the pressure is maintained, for example, held for 3 minutes and then processed.
- the silylation reaction using DMSDMA is represented by the following formula 1.
- the silylating agent is not limited to the above DMSDMA, but can be used without limitation as long as it is a substance that causes a silylation reaction S, and has a silazane bond (Si-N bond) in the molecule.
- silazane bond Si-N bond
- those having a relatively small molecular structure for example, those having a molecular weight of 260 or less are preferred, and those having a molecular weight of 170 or less are more preferred.
- DM SDMA HMDS (Hexamethyldisilazane)
- TMSDMA Dimethylaminotrimet nylsilane
- TMD3 ⁇ 4 1,3,3-Tetrametnyldisilazane
- TMSpyrole 1-Trimethylsilylp yrole
- BSTFA N 0-Bis (trimethylsilyl) trifluoroacetamide
- BDMADMS Bis (dim
- TMDS 1,3,3-Tetrametnyldisilazane, 1 SuMA (Dimethylaminotrimethylsilane), and DMSDMA (Dimethylsilyldimethylamine) are preferred.
- TMDS 1,3,3-Tetrametnyldisilazane, 1 SuMA (Dimethylaminotrimethylsilane), and DMSDMA (Dimethylsilyldimethylamine) are preferred.
- the chemical structures are shown below.
- beta processing is performed on the wafer W after such silylation processing by! / Of the hot plate units (HP) 19a to 19d! (Step 11, Fig. 11 (i)).
- wafer W is loaded from a wafer loading / unloading port (not shown) provided on the side wall 91a of the chamber 91. Then, the wafer W is mounted on the mounting table 92, and the wafer W on the mounting table 92 is heated by supplying power to the heater 93.
- the heating temperature at this time is preferably higher than the temperature during the silylation treatment because the Si-based by-product needs to be decomposed. Specifically, 150-400 ° C is preferred. 300-360 ° C force S-layer is preferred.
- such a beta treatment can be performed using silylation units 11a and ib.
- the wafer W after the beta processing is carried out in this manner is unloaded from the hot plate unit (HP) by the transfer arm 14a and mounted on the wafer mounting unit (TRS) 13a. 7 is accommodated in the carrier C and carried out of the cleaning processing apparatus 104.
- the wafer W is transferred to the sputtering apparatus 106, where a barrier metal film and a Cu seed layer (that is, a seed layer) are formed on the inner walls of the via hole 124a and the trench 124b, and then the wafer W is electrolyzed. It is transferred to the plating apparatus 107, where copper 131 is embedded as a wiring metal in the via hole 124a and the trench 124b by electrolytic plating (step 12 in FIG. 11). Thereafter, annealing of the copper 131 embedded in the via 124a and the trench 1 24b is performed by heat-treating the wafer W (an annealing apparatus is not shown in FIG. 1). Further, the wafer W is transferred to the CMP apparatus 109, where planarization processing by CMP is performed (step 13). Thereby, a desired semiconductor device is manufactured.
- a barrier metal film and a Cu seed layer that is, a seed layer
- the sacrificial film 127 and the like are denatured so as to be solubilized in a predetermined chemical solution, and then the denatured substance is dissolved and removed using such a chemical solution.
- the damage given to the low-k film 124 is recovered by silylation before the dissolution and removal process, and then further beta treatment is performed.
- the Si-based by-product that hinders the recovery of the formed k value can be decomposed, and the k value of the low-k film 124 can be sufficiently recovered.
- the treatment of water vapor and ozone in the modification processing unit may damage the low-k film 124 on which the pattern is formed. Since there is a possibility that pattern peeling may occur when the dissolution removal process is performed using silane, a silylation process may be performed prior to the dissolution removal process to recover such damage to the low-k film 124. Good. In this case, the silylation treatment can be carried out in exactly the same procedure in any of the silylation units 11a and ib as in the silylation treatment after the dissolution removal treatment.
- a pre-beta treatment may be performed prior to the silylation treatment after the dissolution removal treatment! This heating can remove the water remaining on the wafer W and increase the effect of the silylation treatment.
- the heating temperature is preferably 200 ° C. or lower. Also, 50 ° C or higher is preferable for effective water removal.
- This pre-beta treatment may be performed by the hot plate units (HP) 19a to 19d, or may be performed by the silino ray unit 1 la, ib.
- VOS Denaturation treatment
- the k value was recovered by the silylation treatment, the force S was found to decrease the leakage current, and then the k value was restored by the beta treatment.
- the k value recovered by about 0.3 compared to the case of only the silylation treatment.
- the degas of the substance having a molecular weight of 75 is large, but it can be seen that the degas decreases when the beta treatment is performed, particularly when the beta treatment is performed at 350 ° C.
- a substance with a molecular weight of 75 is considered to be a Si-based byproduct, and the recovery of the k value due to the beta treatment is presumed to be due to a decrease in this Si-based byproduct.
- the water content decreased slightly due to the beta treatment, and it is speculated that the decrease in water content contributed somewhat to the recovery of k value!
- the modification treatment of the sacrificial film or the like is performed using a mixed gas of water vapor and ozone, but the treatment may be performed using only ozone without using water vapor.
- the reactivity is lower than with water vapor + ozone, but with subsequent chemicals
- a sacrificial film or the like modified by dissolution and removal treatment can be sufficiently dissolved.
- the low-k film that can recover damage by silylation treatment is not particularly limited, but porous MSQ that is an SOD film can be used.
- a SiOC film which is one of inorganic insulating films formed by CVD, can be targeted. This is because a methyl group (one CH 3) is introduced into the Si—O bond of the conventional SiO film, and Si—
- the SiOC film may be porous. Further, the MSQ insulating film is not limited to a porous film, and may be dense.
- the force S shown for the example in which the present invention is applied to the manufacturing process of the semiconductor device including the copper wiring by the dual damascene method is not limited thereto, and there is a concern about deterioration of the etching target film. Any treatment that has a removal substance to be denatured is applicable.
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- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
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- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Cleaning Or Drying Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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DE112007000177T DE112007000177T5 (de) | 2006-09-07 | 2007-09-04 | Substratbearbeitungsverfahren und Speichermedium |
JP2008533160A JPWO2008029800A1 (ja) | 2006-09-07 | 2007-09-04 | 基板処理方法および記憶媒体 |
US12/086,298 US20090286399A1 (en) | 2006-09-07 | 2007-09-04 | Substrate Processing Method and Storage Medium |
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JP2006242524 | 2006-09-07 | ||
JP2006-242524 | 2006-09-07 |
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WO2008029800A1 true WO2008029800A1 (fr) | 2008-03-13 |
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PCT/JP2007/067206 WO2008029800A1 (fr) | 2006-09-07 | 2007-09-04 | Procédé de traitement de substrat et support de stockage |
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US (1) | US20090286399A1 (ja) |
JP (2) | JPWO2008029800A1 (ja) |
DE (1) | DE112007000177T5 (ja) |
TW (1) | TWI381446B (ja) |
WO (1) | WO2008029800A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013145925A (ja) * | 2013-04-26 | 2013-07-25 | Tokyo Electron Ltd | 処理装置 |
JP2013207220A (ja) * | 2012-03-29 | 2013-10-07 | Dainippon Screen Mfg Co Ltd | 基板処理方法および基板処理装置 |
Families Citing this family (4)
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JP5057647B2 (ja) * | 2004-07-02 | 2012-10-24 | 東京エレクトロン株式会社 | 半導体装置の製造方法および半導体装置の製造装置 |
DE102008035815A1 (de) | 2008-07-31 | 2010-02-04 | Advanced Micro Devices, Inc., Sunnyvale | Verbessern der strukturellen Integrität und Definieren kritischer Abmessungen von Metallisierungssystemen von Halbleiterbauelementen unter Anwendung von ALD-Techniken |
KR20110125651A (ko) * | 2009-03-10 | 2011-11-21 | 레르 리키드 쏘시에떼 아노님 뿌르 레드 에렉스뿔라따시옹 데 프로세데 조르즈 클로드 | 저 유전상수 실릴화를 위한 시클릭 아미노 화합물 |
JP5538128B2 (ja) * | 2010-08-09 | 2014-07-02 | 東京エレクトロン株式会社 | 排気方法およびガス処理装置 |
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JP2004214388A (ja) * | 2002-12-27 | 2004-07-29 | Tokyo Electron Ltd | 基板処理方法 |
JP2006086411A (ja) * | 2004-09-17 | 2006-03-30 | Dainippon Screen Mfg Co Ltd | 基板処理装置 |
JP2006114719A (ja) * | 2004-10-15 | 2006-04-27 | Jsr Corp | 表面疎水化用組成物、表面疎水化方法、半導体装置およびその製造方法 |
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US7083991B2 (en) * | 2002-01-24 | 2006-08-01 | Novellus Systems, Inc. | Method of in-situ treatment of low-k films with a silylating agent after exposure to oxidizing environments |
JP5057647B2 (ja) | 2004-07-02 | 2012-10-24 | 東京エレクトロン株式会社 | 半導体装置の製造方法および半導体装置の製造装置 |
JP4903374B2 (ja) | 2004-09-02 | 2012-03-28 | ローム株式会社 | 半導体装置の製造方法 |
KR101063591B1 (ko) * | 2004-10-27 | 2011-09-07 | 인터내셔널 비지네스 머신즈 코포레이션 | 금속간 유전체로서 사용된 낮은 k 및 극도로 낮은 k의 오가노실리케이트 필름의 소수성을 복원하는 방법 및 이로부터 제조된 물품 |
US7488689B2 (en) * | 2004-12-07 | 2009-02-10 | Tokyo Electron Limited | Plasma etching method |
-
2007
- 2007-09-04 WO PCT/JP2007/067206 patent/WO2008029800A1/ja active Application Filing
- 2007-09-04 US US12/086,298 patent/US20090286399A1/en not_active Abandoned
- 2007-09-04 DE DE112007000177T patent/DE112007000177T5/de not_active Withdrawn
- 2007-09-04 JP JP2008533160A patent/JPWO2008029800A1/ja active Pending
- 2007-09-06 TW TW096133247A patent/TWI381446B/zh not_active IP Right Cessation
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2012
- 2012-07-09 JP JP2012153943A patent/JP2012195613A/ja not_active Withdrawn
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2004214388A (ja) * | 2002-12-27 | 2004-07-29 | Tokyo Electron Ltd | 基板処理方法 |
JP2006086411A (ja) * | 2004-09-17 | 2006-03-30 | Dainippon Screen Mfg Co Ltd | 基板処理装置 |
JP2006114719A (ja) * | 2004-10-15 | 2006-04-27 | Jsr Corp | 表面疎水化用組成物、表面疎水化方法、半導体装置およびその製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2013207220A (ja) * | 2012-03-29 | 2013-10-07 | Dainippon Screen Mfg Co Ltd | 基板処理方法および基板処理装置 |
JP2013145925A (ja) * | 2013-04-26 | 2013-07-25 | Tokyo Electron Ltd | 処理装置 |
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TWI381446B (zh) | 2013-01-01 |
US20090286399A1 (en) | 2009-11-19 |
DE112007000177T5 (de) | 2008-10-23 |
JP2012195613A (ja) | 2012-10-11 |
JPWO2008029800A1 (ja) | 2010-01-21 |
TW200822222A (en) | 2008-05-16 |
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