WO2008023402A1 - Circuit de décodage - Google Patents

Circuit de décodage Download PDF

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Publication number
WO2008023402A1
WO2008023402A1 PCT/JP2006/316368 JP2006316368W WO2008023402A1 WO 2008023402 A1 WO2008023402 A1 WO 2008023402A1 JP 2006316368 W JP2006316368 W JP 2006316368W WO 2008023402 A1 WO2008023402 A1 WO 2008023402A1
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WIPO (PCT)
Prior art keywords
node
input
output
value
circuit
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PCT/JP2006/316368
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English (en)
Japanese (ja)
Inventor
Yutaka Orioku
Original Assignee
Fujitsu Limited
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Priority to PCT/JP2006/316368 priority Critical patent/WO2008023402A1/fr
Publication of WO2008023402A1 publication Critical patent/WO2008023402A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/14—Conversion to or from non-weighted codes
    • H03M7/20—Conversion to or from n-out-of-m codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors

Definitions

  • the present invention relates to a decoding circuit, and more particularly to a 2 to 4 decoding circuit.
  • a decode circuit is used in various devices such as an information processing device.
  • a typical decode circuit is a 2-to-4 (2-input, 4-output) decode circuit.
  • FIG. 1 shows two pairs for outputting a negative logic signal (or a negative polarity signal or an inverted signal, and so on) to a positive logic signal (or a positive signal or a non-inverted signal, and so on)
  • FIG. 4 is a diagram showing a case where a main part of the decoding circuit of 4 is configured by a NAND gate.
  • the decode circuit 1 has inverters 11 and 12 and NAND gates 13 to 16 connected as shown in FIG.
  • decode circuit 1 outputs 4 outputs ZDO to ZD3.
  • a negative logic signal (inverted signal) is indicated by “Z”
  • a negative logic signal (inverted signal) of the signal DO is indicated by “ZDO”.
  • FIG. 2 is a diagram showing a case where the main part of a 2-to-4 decoding circuit for outputting a positive logic signal with respect to a positive logic signal input is configured by a NAND gate and an inverter.
  • the decode circuit 2 includes inverters 11 and 12, NAND gates 13 to 16, and inverters 17 to 20 connected as shown in FIG. For 2 manpower AO and A1, decode circuit 1 outputs 4 outputs DO ⁇ D3.
  • FIG. 3 is a circuit diagram showing a configuration of a general NAND gate 100 that can be used as the NAND gates 13 to 16 in FIG. 1 and FIG.
  • the NAND gate 100 has P-channel transistors 111 and 112 and N-channel transistors 113 and 114 connected as shown in FIG. VDD indicates a power supply voltage, and VSS indicates a ground voltage.
  • INO and IN 1 are input signals to the NAND gate 100, and OUT is an output signal of the NAND gate 100.
  • a data signal switching circuit in which a switch circuit having a signal path between a source and a drain of a nos transistor is connected in a binary tree structure, and each bit signal of an address signal is converted into a binary tree-like stage of the data signal switching signal.
  • Control input of switch circuit on selected path in for example, Patent Document 1 proposes a decoding circuit including an address signal distribution circuit that supplies only to terminals.
  • Patent Document 1 JP-A-9 312558
  • the present invention provides a circuit scale, circuit area, drive capability, power consumption, and relative input / output signal delay time regardless of whether it is for negative logic signal output or positive logic signal output. It is a general object to provide a decoding circuit capable of setting the interval substantially the same.
  • the above problem is that the first node to which the first input is connected, the second node to which the inversion logic of the first input is connected, and the second node to which the second input is connected.
  • the value of the first node reflects the value of the third node by the value of the first and second nodes, and the value of the fourth node by the value of the first and second nodes.
  • the control input is connected to the eighth node reflecting the value of the third node and the first node, the input is connected to the fourth node, and the fifth node.
  • a first switching element having an output connected to the second node, a control input connected to the second node, an input connected to the fourth node, and an output connected to the fifth node.
  • the switching element a third switching element having a control input connected to the first node, an input connected to the third node, and an output connected to the sixth node, and the second node
  • a control input is connected to the second node, an input is connected to the third node, an output is connected to the sixth node, and a control input is connected to the second node.
  • a fifth switching element having an output connected to a node, a control input connected to the first node, an input connected to the fourth node, and an output connected to the seventh node.
  • the above problem is that the first node to which the first input is connected, the second node to which the inversion logic of the first input is connected, and the third node to which the second input is connected.
  • a fourth node to which the inverted logic of the second input is connected a fifth node in which the value of the third node is reflected by the values of the first and second nodes, The value of the fourth node is reflected by the value of the first and second nodes, and the value of the third node is reflected by the values of the sixth node and the values of the first and second nodes.
  • a control input is connected to the first node and the eighth node reflecting the value of the fourth node according to the values of the first node and the second and second nodes.
  • a first switching element having an input connected to the third node and an output connected to a fifth node, and a control to the second node
  • a second switching element having an input connected to the third node and an output connected to the fifth node, a control input connected to the first node, and the fourth node
  • a third switching element having an input connected to the second node and an output connected to the sixth node, and the second node A control input is connected, an input is connected to the fourth node, an output is connected to the sixth node, and a control input is connected to the second node.
  • a fifth switching element having an input connected to a third node and an output connected to a seventh node; a control input connected to the first node; an input connected to the third node; A sixth switching element having an output connected to the seventh node; a control input connected to the second node; an input connected to the fourth node; and an output to the eighth node And a seventh switching element connected to the first node, a control input connected to the first node, an input connected to the fourth node, and an eighth switching connected to the output of the eighth node.
  • a decoding circuit characterized by having an element. Can be achieved.
  • the above problem is that a first node to which a first input is connected, a second node to which an inversion logic of the first input is connected, and a second node to which a second input is connected And a fourth node to which a logical operation output reflecting the value of the third node is reflected by the values of the first node and the second node, and a gate is connected to the first node. Connected, an input connected to the third node, an output connected to the fourth node, and a control input connected to the second node, and an input to the third node And a first N-type pass transistor having an output connected to the fourth node. This can be achieved by a logic circuit.
  • the above problem is that a first node to which a first input is connected, a second node to which the inversion logic of the first input is connected, and a second node to which a second input is connected.
  • a gate is connected to the first node, the fourth node from which the value of the third node reflected by the values of the first and second nodes is output, and the first node.
  • a P-type pass transistor having an input connected to the node 3 and an output connected to the fourth node; a control input connected to the second node; an input connected to the third node;
  • a first N-type pass transistor having an output connected to the fourth node, a control input connected to the first node, an input connected to a ground potential, and an output connected to the fourth node; Connected to the second N-type pass transistor, the fourth node and the logic output. That it has a converter can be achieved by a logic circuit that feature.
  • the above-mentioned problem is that the first node to which the first input is connected and the inversion theory of the first input.
  • a fourth node with an output connected; a first P-type with a gate connected to the first node; an input connected to the third node; and an output connected to the fourth node A pass transistor; and an N-type pass transistor having a control input connected to the second node, an input connected to the third node, and an output connected to the fourth node.
  • the above problem is that the first node to which the first input is connected, the second node to which the inversion logic of the first input is connected, and the second node to which the second input is connected.
  • a gate is connected to the first node, a fourth node reflecting the value of the third node, and a gate connected to the first node.
  • a first P-type pass transistor having an input connected to the node and an output connected to the fourth node, a control input connected to the second node, and an input connected to the third node.
  • An N-type transistor having an output connected to the fourth node, a control input connected to the first node, an input connected to a power supply voltage, and an output connected to the fourth node It has a second P-type pass transistor and an inverter connected to the fourth node and logic output. It can be achieved by logic circuits according to claim Rukoto.
  • the circuit scale, circuit area, drive capability, power consumption, and relative delay time of input / output signals can be reduced regardless of whether they are for negative logic signal output or positive logic signal output.
  • An effect of realizing a decoding circuit that can be set substantially the same is obtained.
  • FIG. 1 is a diagram showing a case where a main part of a 2-to-4 decoding circuit for outputting a negative logic signal is configured by a NAND gate.
  • FIG. 2 is a diagram showing a case where a main part of a 2-to-4 decoding circuit for outputting a positive logic signal is configured by a NAND gate.
  • FIG. 3 is a circuit diagram showing a configuration of a general NAND gate that can be used as the NAND gate of FIGS. 1 and 2.
  • FIG. 4 is a circuit diagram showing a first embodiment of the present invention.
  • FIG. 5 is a circuit diagram showing a second embodiment of the present invention.
  • FIG. 6 is a diagram showing a model of a system in which a decoding circuit and a selector circuit are relayed by a two-stage inverter.
  • FIG. 7 is a diagram for explaining a circuit change in a part other than the transfer system of the system.
  • FIG. 8 is a diagram for explaining a circuit change in a part other than the transfer system of the system.
  • FIG. 9 is a diagram showing a comparative example using a conventional decoding circuit.
  • FIG. 10 is a diagram showing a third embodiment of the present invention.
  • FIG. 11 is a timing chart for explaining the operation of the third embodiment in comparison with the operation of the comparative example.
  • a decode circuit is configured using a pass transistor without using a NAND gate.
  • the circuit size, circuit area, drive capability, power consumption, and input power of the decode circuit are independent of whether the output is a negative logic signal output for a positive logic signal input or a positive logic signal output for a positive logic signal input.
  • the relative delay time of the output signal can be set approximately the same.
  • FIG. 4 is a circuit diagram showing a first embodiment of the present invention.
  • the 2-to-4 decode circuit 30 for outputting a negative logic signal has inverters 31, 32, P-channel transistors 41 to 44, N-channel transistors 51 to 58, and inverters 61 to 64 connected as shown in FIG. .
  • the decode circuit 30 outputs 4 negative outputs ZDO to ZD3.
  • VS s represents the ground voltage.
  • the channel transistor 42 and the N-channel transistor 53 are connected in parallel
  • the P-channel transistor 43 and the N-channel transistor 55 are connected in parallel
  • the P-channel transistor 44 and the N-channel transistor 57 are connected in parallel.
  • the node N1 to which the input signal AO is input is connected to the gates of the transistors 41, 42, 52, 54, 55, and 57.
  • the node N2 to which the output of the inverter 31 is input is connected to the gates of the transistors 4 3, 44, 51, 53, 56, and 58 !.
  • Parallel arrangement of transistors 41 and 51 [J connection circuit is connected between node N4 to which the output of inverter 32 is inputted and node N5 to be connected to the input of inverter 61.
  • the parallel connection circuit of the transistors 42 and 53 is connected between a node N3 to which the input signal A1 is input and a node N6 connected to the input of the inverter 62.
  • the parallel connection circuit of the transistors 43 and 55 is connected between the node N4 and a node N7 connected to the input of the inverter 63.
  • the parallel connection circuit of the transistors 44 and 57 is connected between the node N3 and the node N8 connected to the input of the inverter 64.
  • the transistor 52 is connected between the node N5 and the ground voltage VSS.
  • Transistor 54 is connected between node N6 and ground voltage VSS.
  • Transistor 56 is connected between node N7 and ground voltage VSS.
  • Transistor 58 is connected between node N8 and ground voltage VSS.
  • the nodes N1 to N8 constitute first to eighth nodes
  • the inverters 31, 32 constitute first and second input inverters
  • the inverters 61 to 64 constitute first to second nodes.
  • 4 output inverters are configured.
  • the 10th pass transistor is composed of transistors 51, 53, 43, 44, 56, 58, respectively, and the gate power ⁇ 2nd, 4th, 5th, 11th, 12th connected to node 2 Configure a no-transistor.
  • the logic circuit includes a first node to which the first input is connected, a second node to which the inverted logic of the first input is connected, and a third node to which the second input is connected.
  • the control input is connected to the second node, and the input is connected to the third node.
  • the first to fourth nodes correspond to the nodes Nl, N2, N3, and N6, respectively
  • the P-type The no-transistor corresponds to the pass transistor 42
  • the first N-type pass transistor corresponds to the pass transistor 53
  • the second N-type pass transistor corresponds to the pass transistor 54
  • the inverter corresponds to the inverter 62.
  • the decoded output values ZDO to ZD3 obtained by inverting the logical value “1000” of the nodes N5, N7, N6, and N8 by the inverters 61, 63, 62, and 64 have the value “0111”.
  • the node N1 When 0 is input to the A1 input and 1 is input to the AO input, the node N1 has a logic value of 1, the node N2 has a value of 0, the node N3 has a logic value of 0, and the node N4 has a logic value of 1. Accordingly, since the pass transistors 41 and 51 are turned off and the pass transistor 52 is turned on, the node N5 is pulled down by the pass transistor 52 and has a logic value of 0. Similarly, the nos transistors 42 and 53 are turned off and the pass transistor 54 is turned on, so that the node N6 has a logic value of zero.
  • the pass transistors 43 and 55 are turned on, and the pass transistors Since the star 56 is turned off, the logical value of the node N4 is reflected, so that the node N7 has a logical value of 1. Further, since the node transistors 44 and 57 are turned on and the transistor 58 is turned off, the logical value of the node N3 is reflected, so that the node N8 has a logical value of 0. Therefore, the decoded output value / DO to / D3 obtained by inverting the logical value “0100” of the nodes N5, N7, N6, and N8 by the inverters 61, 63, 63, and 64 has the value “1011”. .
  • the node N1 When 1 is input to the A1 input and 0 is input to the AO input, the node N1 has a logic value of 0, the node N2 has a value of 1, the node N3 has a value of 1, and the node N4 has a logic value of 0. Accordingly, since the pass transistors 41 and 51 are turned on, the logical value of the node N4 is reflected, so that the node N5 has a logical value of 0. Similarly, since the pass transistors 42 and 53 are turned on and the pass transistor 54 is turned off, the logical value of the node N3 is reflected, so that the node N6 has a logical value of 1.
  • the decoded output values ZDO to ZD3 obtained by inverting the logical values “0 010” of the nodes N5, N7, N6, and N8 by the inverters 61, 63, 62, and 64 have a value of “1101”.
  • the node N1 When 1 is input to the A1 input and 1 is input to the AO input, the node N1 has a logic value of 1, the node N2 has a value of 0, the node N3 has a value of 1, and the node N4 has a logic value of 0. Accordingly, since the pass transistors 41 and 51 are turned off and the pass transistor 52 is turned on, the node N5 is pulled down by the pass transistor 52 and has a logic value of 0. Similarly, pass transistors 42 and 53 are turned off and pass transistor 54 is turned on, so that node N6 has a logic value of zero.
  • the logical value “0001” of nodes N5, N7, N6, N8 is The decoded output values / D0 to / D3 inverted by the barters 61, 63, 62, and 64 have a value of “1110”.
  • FIG. 5 is a circuit diagram showing a second embodiment of the present invention.
  • the 2-to-4 decode circuit 70 for outputting a positive logic signal has inverters 71 and 72, P-channel transistors 81 to 88, N-channel transistors 91 to 94, and inverters 101 to 104 connected as shown in FIG. .
  • the decode circuit 70 outputs four positive logic outputs DO to D3.
  • VDD indicates the power supply voltage.
  • the channel transistor 83 and the N-channel transistor 92 are connected in parallel
  • the P-channel transistor 85 and the N-channel transistor 93 are connected in parallel
  • the P-channel transistor 87 and the N-channel transistor 96 are connected in parallel.
  • the parallel connection circuit of the transistors 85 and 93 is connected between the node N13 and the node N17 connected to the input of the inverter 103.
  • the parallel connection circuit of the transistors 87 and 94 is connected between the node N14 and a node N18 connected to the input of the inverter 104.
  • the transistor 82 is connected between the node N15 and the power supply voltage VDD.
  • Transistor 84 is connected between node N16 and power supply voltage VDD.
  • Transistor 86 is connected between node N17 and power supply voltage VDD.
  • Transistor 88 is connected between node N18 and power supply voltage VDD.
  • Nodes N11 to N18 constitute first to eighth nodes
  • inverters 71 and 72 constitute first and second input inverters
  • inverters 101 to 104 constitute first to second nodes.
  • the first, third, sixth, eighth, eleventh and twelfth node transistors connected to the first node Ni l to which AO is input are configured as transistors 91, 92, 85, 87, 82. , 84 ⁇ , and the gate power ⁇ 2nd, 4th, 5th, 7th, 9th and 10th pass transistors connected to the second node N12, respectively.
  • the logic circuit includes a first node to which the first input is connected, a second node to which the inverted logic of the first input is connected, and a third node to which the second input is connected.
  • the first ⁇ -type node transistor whose output is connected to the node 4 and the control input is connected to the second node, the input is connected to the third node, and the output is connected to the fourth node ⁇ Type pass transistor, a second vertical node transistor with a control input connected to the first node, an input connected to the power supply voltage, and an output connected to the fourth node, and a fourth node and a logic output
  • the first to fourth nodes are nodes Nil, N12, N, respectively. 13, N15, the first P-type pass transistor corresponds to the pass transistor 81, the N-type pass transistor corresponds to the pass transistor 91, and the second P-type pass transistor corresponds to the pass transistor 82.
  • the inverter corresponds to the inverter 101.
  • the node Nil When 0 is input to the A1 input and 0 is input to the AO input, the node Nil is 0, the node N12 is 1, the node N13 is 0, and the node N14 is 1. Accordingly, since the pass transistors 81 and 91 are turned on and the pass transistor 82 is turned off, the logical value of the node N13 is reflected, so that the node N15 has a logical value of 0. Similarly, since the pass transistors 83 and 92 are turned on and the pass transistor 84 is turned off, the logical value of the node N14 is reflected, so that the node N16 has a logical value of 1.
  • the pass transistors 85 and 93 are turned off and the pass transistor 86 is turned off, the node N17 is pulled down by the pass transistor 86 and has a logic value of 0. Further, since the nos transistors 87 and 94 are turned off and the pass transistor 88 is turned on, the node N 18 is pulled down by the pass transistor 88 and has a logic value of 0. Therefore, the logical values “0010” of the nodes N15, N17, N1 6 and N18 are inverted by the inverters 101, 103, 102 and 104.
  • the code output values ZD0 to ZD3 have a value of “1101”.
  • the decoded output values ZDO to ZD3 obtained by inverting the logical values “0001” of the nodes N15, N17, N16, and N18 by the inverters 101, 103, 102, and 104 have a value of “1110”.
  • the node Ni l When 1 is input to the A1 input and 0 is input to the AO input, the node Ni l is 0, the node N12 is 1, the node N13 is 1, and the node N14 has a logical value of 0. Accordingly, since the pass transistors 81 and 91 are turned on, the logical value of the node N13 is reflected, so that the node N15 has a logical value of 1. Similarly, since the pass transistors 83 and 92 are turned on and the pass transistor 84 is turned off, the logical value of the node N14 is reflected, so that the node N16 has a logical value of 0.
  • the decoded output values ZD0 to ZD3 obtained by inverting the logical value “1000” of the nodes N5, N17, N16, and N18 by the inverters 101, 103, 102, and 104 have the value “0111”.
  • the node Nil When 1 is input to the A1 input and 1 is input to the AO input, the node Nil is 1, the node N12 is 0, the node N13 is 1, and the node N14 has a logical value of 0. Therefore, the pass transistors 81 and 91 are turned off, and the pass transistor 82 is turned on. By being pulled down by the transistor 82, it has a logical value of zero. Similarly, since pass transistors 83 and 92 are turned off and pass transistor 84 is turned on, node N 16 has a logic value of zero. Since the pass transistors 85 and 93 are turned on and the pass transistor 86 is turned off, the logical value of the node N13 is reflected, so that the node N17 has a logical value of 1.
  • the decoded output values Z DO to / D3 obtained by inverting the logical values “0100” of the nodes N5, N7, N6, and N8 by the inverters 101, 103, 102, and 104 have a value of “1011”.
  • Each of the decoding circuits 30 and 70 is configured using a pass transistor without using a NAND gate.
  • the number of elements constituting the decoding circuits 30 and 70 is the same, and the number of gates between the input and output is also the same. Therefore, regardless of whether the decoding circuit 30 is for negative logic signal output or the decoding circuit 70 for negative logic signal output, the circuit scale, circuit area, drive capability, power consumption, and relative delay of input / output signals The time can be set to approximately the same.
  • Negative. Out [3: 0] is the output terminal of the decode circuit 330 that outputs the output signals ZDO to ZD3, and Positiv e_out [3: 0] is the decode circuit that outputs the output signals D0 to D3.
  • Negativej n [3: 0] is the selector input terminal of the selector circuit 301
  • Positive_in [3: 0] is the selector input signal of the selector circuit 301-1
  • DATA [3: 0] is the selector circuit 301, 301— 1 input data signal
  • OUT [3: 0] indicates the output terminals of the selector circuits 301 and 301-1.
  • the decode circuit 330 outputs negative logic signals ZD0 to ZD3 to the positive logic inputs Al and AO as in the decode circuit 1 shown in FIG. , 203 to select and output the input data signal DATA [3: 0] according to the negative logic signals ZD0 to ZD3.
  • the decoding circuit 370 outputs positive logic signals D0 to D3 to the positive inputs Al and AO in the same manner as the decoding circuit 2 shown in FIG. 2, and the selector circuit 301 is connected via inverters 201 to 203. Select and output the input data signal DATA [3: 0] according to the obtained negative logic signals ZD0 to ZD3.
  • the decode circuit 370 Like the decoding circuit 2 shown in FIG.
  • the positive logic signals DO to D3 are output to the positive logic inputs Al and AO, and the selector circuit 301-1 receives the positive logic signals DO to D obtained through the inverters 201 and 202. Selects and outputs the input data signal DATA [3: 0] according to D3.
  • FIG. 6 is a diagram showing a model of a system that relays between a decoding circuit and a selector circuit with a two-stage inverter.
  • a negative logic signal output 2 to 4 decoding circuit 330 is connected to a selector circuit 301 via two stages of inverters 201 and 202.
  • FIG. 1 For example, when the transfer distance between the decode circuit 330 and the selector circuit 301 is increased for some reason, it is necessary to increase the number of inverter stages in the transfer system by one, or as a result of simulation, FIG.
  • a new relay circuit may be provided to shape the waveform.
  • the transfer performance will be degraded, so the buffer cannot be used when high transfer performance is required. Therefore, when high transfer performance is required, the inverter 203 is used as a relay circuit as shown in FIG.
  • the decoding circuits 30 and 70 shown in FIG. 4 and FIG. 5 are used, if there is a circuit change from FIG. 6 to FIG. Therefore, it is necessary to change the decoding circuit 30 shown in FIG. 5 to the decoding circuit 70 shown in FIG.
  • the decode circuit 30 and the decode circuit 70 are set to have substantially the same circuit scale, circuit area, drive capability, power consumption, relative delay time of input / output signals, and the like. Even if the decoding circuit 70 is changed to the decoding circuit 70, it is not necessary to perform optimization again for the entire system, and redesign associated with the change does not require much time. Also, when there is a circuit change from Fig. 7 to Fig. 6, when there is a circuit change from Fig.
  • FIG. 10 is a diagram showing an application example of the decoding circuit of the third embodiment of the present invention, and FIG. 9 shows a conventional example using a conventional decoding circuit for comparison with the present invention. It is.
  • FIG. 9 and FIG. 10 the same parts as those in FIG. 1, FIG. 2, and FIGS.
  • a combination of a 2 to 4 decoding circuit for negative logic signal output and a 2 to 4 decoding circuit for positive logic signal output is connected to the selector circuit.
  • the decoding circuits 1 and 2 shown in FIGS. 1 and 2 are connected to the selector circuit 301-2.
  • the decode circuit 1 outputs negative logic signals ZD 0 to ZD3 as N_NETA [3: 0] to the positive logic inputs Al and AO, and the selector input terminal Neg of the selector circuit 301-2. Input to ative_in [3: 0].
  • the decode circuit 2 outputs the positive logic signals DO to D3 as P_NETA [3: 0] to the positive logic inputs Al and AO, and outputs them to the selector input terminal Positive_in [3: 0] of the selector circuit 301-2. Entered.
  • the selector circuit 301-2 outputs the input data signal DATA_A [3: 0] according to the negative logic signal N_NETA [3: 0] and the positive logic signal P_NETA [3: 0] obtained from the decoding circuits 1 and 2 Select and output as signal S_A_OUT [3: 0].
  • the decode circuits 30 and 70 shown in FIGS. 4 and 5 are connected to the selector circuit 3 01-2.
  • the decode circuit 30 outputs negative logic signals ZDO to ZD3 as N_NETB [3: 0] to the positive logic inputs Al and AO, and inputs them to the selector input terminal Negative_in [3: 0] of the selector circuit 301-2.
  • the decode circuit 70 outputs positive logic signals D0 to D3 as P_NETB [3: 0] to the positive logic inputs Al and AO, and outputs them to the selector input terminal Positive_in [3: 0] of the selector circuit 301-2. Entered.
  • the selector circuit 301-2 is a decoding circuit
  • FIG. 11 is a timing chart for explaining the operation of the third embodiment in comparison with the operation of the conventional decoding circuit.
  • the input signals input to the decoding circuits 1 and 2 in FIG. 9 and the input signals input to the decoding circuits 30 and 70 in FIG. 10 are shown as common input signals AO and Al. Yes.
  • Output signal P_NETA [3: 0] determines the transition timing of the output signal S_A_OUT [3: 0] of the selector circuit 301-2.
  • the delay amount of the decode circuit 30 and the delay amount of the decode circuit 70 are substantially the same. Therefore, as shown in FIG. 11, the output signal P_NE TB [3: 0] of the decoding circuit 30 or the output signal N_NETB [3: 0] of the decoding circuit 7O is the output signal S_B_OUT [3: 3 of the selector circuit 3O1-2. 0] transition timing is determined. [0055] As shown in Fig. 11, for the input signals Al and AO, the delay amount of the system in Fig. 9 is A_DEL AY. The delay amount of the system in Fig. 10 is B_DELAY. Can be reduced.
  • the relative delay time of the input / output signal is larger in the decoding circuit 2 than in the decoding circuit 1, so that the high speed operation is limited by the operating speed of the decoding circuit 2.
  • the relative delay time of the input / output signals is the same for both decoding circuits 30 and 70, and is smaller than the relative delay time of the conventional decoding circuit 2, so the high-speed operation speed is the delay time. It is not limited by the operating speed of the larger decoding circuit. According to the results of experiments by the inventor, it was confirmed that the delay time was improved by about 10% in the system shown in FIG. 10 compared to the conventional system shown in FIG.
  • the power of explaining a system having a selector circuit as an example of a system to which the decoding circuit of the present invention is applied is limited to this.
  • the decoding circuit of the present invention is applicable to various systems in which a decoding circuit for outputting a negative logic signal and a decoding circuit for outputting a positive logic signal are used.
  • the present invention can be applied to various systems in which a decoding circuit for outputting a negative logic signal and a decoding circuit for outputting a positive logic signal are used.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Logic Circuits (AREA)

Abstract

La présente invention concerne un circuit de décodage configuré en n'utilisant aucune porte NON-ET mais en utilisant des transistors passants. Que le circuit de décodage soit utilisé pour sortir un signal logique négatif pour une entrée positive du signal logique ou pour sortir un signal logique positif pour une entrée positive du signal logique, il est possible de régler sur des valeurs respectives sensiblement identiques son échelle de circuit, sa surface de circuit, sa capacité conductrice, sa consommation d'électricité et le délai d'attente relatif des signaux d'entrée/sortie.
PCT/JP2006/316368 2006-08-22 2006-08-22 Circuit de décodage WO2008023402A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2006/316368 WO2008023402A1 (fr) 2006-08-22 2006-08-22 Circuit de décodage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2006/316368 WO2008023402A1 (fr) 2006-08-22 2006-08-22 Circuit de décodage

Publications (1)

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WO2008023402A1 true WO2008023402A1 (fr) 2008-02-28

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012126046A (ja) * 2010-12-16 2012-07-05 Konica Minolta Holdings Inc インクジェット記録装置及び駆動波形信号生成方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62159921A (ja) * 1986-01-08 1987-07-15 Sharp Corp デマルチプレクサ回路
JPH03153126A (ja) * 1989-11-09 1991-07-01 Nec Ic Microcomput Syst Ltd デコード回路
JP2004055939A (ja) * 2002-07-23 2004-02-19 Renesas Technology Corp 半導体集積回路装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62159921A (ja) * 1986-01-08 1987-07-15 Sharp Corp デマルチプレクサ回路
JPH03153126A (ja) * 1989-11-09 1991-07-01 Nec Ic Microcomput Syst Ltd デコード回路
JP2004055939A (ja) * 2002-07-23 2004-02-19 Renesas Technology Corp 半導体集積回路装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012126046A (ja) * 2010-12-16 2012-07-05 Konica Minolta Holdings Inc インクジェット記録装置及び駆動波形信号生成方法

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