WO2008006340A1 - Procédé de liaison résistant à la chaleur et aux impacts d'un semi-conducteur par pressage à chaud - Google Patents

Procédé de liaison résistant à la chaleur et aux impacts d'un semi-conducteur par pressage à chaud Download PDF

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Publication number
WO2008006340A1
WO2008006340A1 PCT/DE2007/001174 DE2007001174W WO2008006340A1 WO 2008006340 A1 WO2008006340 A1 WO 2008006340A1 DE 2007001174 W DE2007001174 W DE 2007001174W WO 2008006340 A1 WO2008006340 A1 WO 2008006340A1
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Prior art keywords
semiconductor
sintering
pressure
layer
connection
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PCT/DE2007/001174
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German (de)
English (en)
Inventor
Mathias Kock
Gerhard Palm
Ronald Eisele
Original Assignee
Danfoss Silicon Power Gmbh
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Application filed by Danfoss Silicon Power Gmbh filed Critical Danfoss Silicon Power Gmbh
Publication of WO2008006340A1 publication Critical patent/WO2008006340A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
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    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
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    • H01L2224/27505—Sintering
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    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
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    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
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    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/8382—Diffusion bonding
    • H01L2224/8383—Solid-solid interdiffusion
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    • H01L2224/838—Bonding techniques
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    • H01L2224/83905—Combinations of bonding methods provided for in at least two different groups from H01L2224/838 - H01L2224/83904
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    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
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    • H01L2924/1305—Bipolar Junction Transistor [BJT]
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    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Definitions

  • the invention relates to a method for heat and impact resistant connection of a semiconductor by pressure sintering according to the preamble of the main claim.
  • the increasingly high operating temperatures to which semiconductors are subjected in particular the operating temperatures which power semiconductors such as diodes, IGBTs or MOSFETs with a very high power loss, but also semiconductors and semiconductor sensors operating in very hot environments (eg an engine compartment of a motor vehicle) are calling for improved connection techniques.
  • connection in particular of the power semiconductor itself, is the low-temperature connection technique (NTV), as used e.g. in DE 34 14 065 C2 or EP 0 242 626 Bl.
  • NTV low-temperature connection technique
  • Another disadvantage is the additional cost of the film and the additional process steps ("stamping" the metal powder layer of the carrier film), and the metal powder residues on the carrier film, which can not be used.
  • the object of the invention has been found to eliminate the disadvantages of the individual methods represented in the prior art, in particular in the subsequent processing of a semiconductor wafer.
  • the application of the metal powder suspension consisting essentially of a metal powder and a solvent, to the wafer back can be applied by various methods, such as screen / stencil printing, spraying or spin coating known in the semiconductor field.
  • various methods such as screen / stencil printing, spraying or spin coating known in the semiconductor field.
  • only small parts on the edge of the wafer
  • metal powder suspension since the remainder of the wafer rear side simultaneously represents the connection of the individual semiconductors to be contacted. Therefore, a cost advantage over the method with the full-surface covered carrier film arises.
  • the drying of the now bare surface of the metal powder suspension is effected by heating and flashing off, preferably between 100 ° C and 150 0 C. Subsequently, the wafer with the dried metal powder suspension is pre-compressed to a pressure of only 5 MPa - 10 MPa and a temperature of 120 ° C - 180 ° C. A sintering of the metal powder layer does not take place yet. Due to the precompression, however, the metal powder layer previously applied as a suspension adheres so well to the wafer that the metal powder layer does not dissolve again in the following process steps, even as described in the following, "sawable", but still fully sinterable during pressure sintering.
  • the wafers Only after pre-compacting can the wafers be separated according to the usual methods known in semiconductor manufacturing by laminating the wafer with the back side onto a sawing foil, and separating the individual chips by a cut-off.
  • UV-curable sawing foils can be particularly advantageous with thin waveguides.
  • the coated grinding ("sawing") of the coated wafer is not possible in the previously existing methods since the metal powder layer would be detached from the wafer when the semiconductors were separated, and only the special method of precompression described here permits such a treatment.
  • the metal powder layer is additionally protected by the sawing foil until it is processed.
  • the placement of the components can also be carried out inexpensively without additional devices on standard "pick and place” machines, since the semiconductor brings with it the metal powder view on the rear side required for the printing sintering process, so it is not an additional process of "stamping" one Connection layer required.
  • the actual pressure sintering process takes place above 220 ° C. and with more than 30 MPa within a few seconds.
  • Fig. 3 the lifting of the sawing film.
  • the compaction shown in FIG. 1 takes place at a temperature which is the same or slightly higher (30-70 ° C.) than the drying temperature.
  • the electronic assembly to be formed, for example, a power module with a solid electrically and thermally well-conducting sintered compound of a semiconductor device on a connection partner, e.g. A substrate, further semiconductor or circuit carrier, is achieved by the sintering compound is carried out by pressure sintering as usual, but a sintered layer is previously generated as dried, at least on the wafer back side before the separation of the semiconductor devices and pre-compressed metal powder suspension 10, through the Pre-compaction step for sawing when singulating is mechanically immobilized.
  • the wafer 14 is preferably provided with a metallization 12 below the metal powder.
  • the chip Before the actual sintering of the dried suspension layer, the chip is usually singulated from a wafer for the connection process by sawing in the respective dimensions of the relevant semiconductor chip.
  • wafer-on-wafer applications are also conceivable in which, for example, sensors are used as stacked components in special products.
  • a tradable intermediate product has been created by the method according to the invention, which is characterized by the precompressed layer. Therefore, the use of such an intermediate product for a Drucksin- wrestle can be addressed.
  • the pre-compression leads on a microscopic level to a rounding of the grain boundaries, so it can be considered as the start phase of a sintering process, which leads to the diffusion of the metal atoms, so that grain boundaries are largely eliminated.
  • FIG. 2 shows the wafer after sawing with the sawing foil 24 still connecting the singulated semiconductors 22, the sawing frame 20 being shown at the edge, and FIG. 3 schematically showing the lifting off of the sawing foil 24.
  • the semiconductor prepared by the pre-compression according to the invention for a subsequent pressure sintering process is characterized in that prior to singulating a semiconductor wafer into individual building blocks, at least the areas of the individual sintered-to-be-connected individual semiconductor building blocks, a metal powder suspension was applied pasty, and the The suspension layer was dried with degassing of the volatile constituents and with the formation of a porous layer, after which the porous layer was precompacted with application of pressure and temperature for a wafer saw, and if this is not already done by the buyers of the intermediate product, the Semiconductor devices are separated with appropriately sized sintered material layers on top of them, the semiconductors are aligned on the connection pad, and finally the final sintering to form a solid connection by diffusion / introduction of sintered material To create atoms in the respective connection partners.
  • the precompacting step leads, under pressure and at temperatures below the sintering temperature, to a compressed, dried, firmly adhering layer, in particular on the rear side of the semiconductor.
  • a metal powder suspension and pre-compression with pressure and at temperature below the sintering temperature may also be the application of a metal powder suspension and pre-compression with pressure and at temperature below the sintering temperature to a compressed, dried layer on the front and back of a semiconductor for mounting contact terminals and / or heat sinks on the second side.
  • the suspension is gray and insoluble in water, has a low flash point, so that when drying a sudden increase in temperature is to be avoided.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)

Abstract

La présente invention concerne un procédé de fabrication d'une liaison par pressage à chaud d'un module semi-conducteur (22) sur un partenaire de liaison sélectionné parmi le groupe : substrat, autre semi-conducteur ou support de circuit, et de pressage à chaud du module semi-conducteur (22) préparé. Dans un tel procédé, une suspension de poudre métallique (10) est appliquée sous forme pâteuse avant la séparation d'une plaquette semi-conductrice (14) en modules semi-conducteurs (22) isolés sur au moins les zones des modules semi-conducteurs (22) isolés à lier par frittage ultérieurement ; la couche de suspension est séchée par les gaz extérieurs des éléments volatils et par production d'une couche poreuse ; la couche poreuse est pré-étanchéifiée avec une résistance au découpage par application de pression et de température pour une scie plaquette-silicium ; les modules semi-conducteurs (22) sont séparés avec les couches de matériau de frittage de taille adaptée qu'ils comportent ; les modules semi-conducteurs sont dirigés sur l'installation de liaison ; et le frittage final est réalisé par constitution d'une liaison solide par diffusion/introduction d'atomes de matériau de frittage dans les partenaires de liaison respectifs.
PCT/DE2007/001174 2006-07-14 2007-07-03 Procédé de liaison résistant à la chaleur et aux impacts d'un semi-conducteur par pressage à chaud WO2008006340A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102006033073.0 2006-07-14
DE102006033073A DE102006033073B3 (de) 2006-07-14 2006-07-14 Verfahren zur Schaffung einer hitze- und stoßfesten Verbindung des Baugruppen-Halbleiters und zur Drucksinterung vorbereiteter Halbleiterbaustein

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WO2008006340A1 true WO2008006340A1 (fr) 2008-01-17

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Cited By (6)

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Publication number Priority date Publication date Assignee Title
US20120037688A1 (en) * 2009-02-13 2012-02-16 Danfoss Silicon Power Gmbh Method for producing a high-temperature and temperature-change resistant connection between a semiconductor module and a connection partner
WO2017060140A3 (fr) * 2015-10-08 2017-06-01 Heraeus Deutschland GmbH & Co. KG Procédé de fabrication d'un ensemble substrat, ensemble substrat et procédé de liaison d'un ensemble substrat avec un composant électronique
DE102010000537C5 (de) * 2009-03-11 2019-03-14 Infineon Technologies Ag Halbleiteranordnung mit einem Abstandshalterelement und Verfahren zu deren und dessen Herstellung
US10607962B2 (en) 2015-08-14 2020-03-31 Danfoss Silicon Power Gmbh Method for manufacturing semiconductor chips
EP3792962A1 (fr) * 2019-09-12 2021-03-17 Infineon Technologies AG Méthode de contrôle d'un procédé de fabrication d'une couche frittable de connexion par mesures photométriques
US11488921B2 (en) 2019-10-01 2022-11-01 Infineon Technologies Ag Multi-chip device, method of manufacturing a multi-chip device, and method of forming a metal interconnect

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Publication number Priority date Publication date Assignee Title
US8828804B2 (en) * 2008-04-30 2014-09-09 Infineon Technologies Ag Semiconductor device and method
US7754533B2 (en) * 2008-08-28 2010-07-13 Infineon Technologies Ag Method of manufacturing a semiconductor device
DE102011005322B4 (de) * 2011-03-10 2017-04-06 Semikron Elektronik Gmbh & Co. Kg Verfahren zur Herstellung eines Leistungshalbleitersubstrates
EP3787012A4 (fr) * 2018-04-27 2022-05-11 Nitto Denko Corporation Procédé de fabrication pour dispositif à semi-conducteur
JP7143156B2 (ja) 2018-04-27 2022-09-28 日東電工株式会社 半導体装置製造方法

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EP0477600A1 (fr) * 1990-09-26 1992-04-01 Siemens Aktiengesellschaft Procédé pour attacher à un substrat un corps semi-conducteur comportant au moins un composant semi-conducteur
JPH0790317A (ja) * 1993-09-20 1995-04-04 Kubota Corp 熱間静水圧加圧焼結方法
EP0764978A2 (fr) * 1995-09-11 1997-03-26 Siemens Aktiengesellschaft Procédé pour la fixation de composants électroniques au dessus d'un substrat au moyen de frittage par pression

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US9287232B2 (en) * 2009-02-13 2016-03-15 Danfoss Silicon Power Gmbh Method for producing a high-temperature and temperature-change resistant connection between a semiconductor module and a connection partner
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KR20180059913A (ko) * 2015-10-08 2018-06-05 헤레우스 도이칠란트 게엠베하 운트 코. 카게 기판 배열체를 생산하는 방법, 기판 배열체, 및 기판 배열체를 전자 부품에 연결하는 방법
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CN108604555A (zh) * 2015-10-08 2018-09-28 贺利氏德国有限两合公司 用预固剂涂覆接触材料层以将衬底布置连接到电子组件的方法、相应的衬底布置及其制造方法
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WO2017060140A3 (fr) * 2015-10-08 2017-06-01 Heraeus Deutschland GmbH & Co. KG Procédé de fabrication d'un ensemble substrat, ensemble substrat et procédé de liaison d'un ensemble substrat avec un composant électronique
US10622331B2 (en) 2015-10-08 2020-04-14 Heraeus Deutschland GmbH & Co. KG Method for producing a substrate arrangement, substrate arrangement, and method for connecting a substrate arrangement to an electronic component
CN108604555B (zh) * 2015-10-08 2022-03-08 贺利氏德国有限两合公司 用预固剂涂覆接触材料层以将衬底布置连接到电子组件的方法、相应的衬底布置及其制造方法
EP3940758A3 (fr) * 2015-10-08 2022-08-10 Heraeus Deutschland GmbH & Co. KG Procédé de connexion par frittage d'un agencement de substrat avec un composant électronique utilisant un moyen de pré-fixation sur une couche de matériau de frittage de contact, agencement de substrat correspondant et procédé de sa fabrication
EP3792962A1 (fr) * 2019-09-12 2021-03-17 Infineon Technologies AG Méthode de contrôle d'un procédé de fabrication d'une couche frittable de connexion par mesures photométriques
US11749568B2 (en) 2019-09-12 2023-09-05 Infineon Technologies Ag Method for forming a pre-connection layer on a surface of a connection partner and method for monitoring a connection process
US11488921B2 (en) 2019-10-01 2022-11-01 Infineon Technologies Ag Multi-chip device, method of manufacturing a multi-chip device, and method of forming a metal interconnect

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