WO2007108129A1 - Capteur d'image a l'etat solide - Google Patents

Capteur d'image a l'etat solide Download PDF

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Publication number
WO2007108129A1
WO2007108129A1 PCT/JP2006/305861 JP2006305861W WO2007108129A1 WO 2007108129 A1 WO2007108129 A1 WO 2007108129A1 JP 2006305861 W JP2006305861 W JP 2006305861W WO 2007108129 A1 WO2007108129 A1 WO 2007108129A1
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WO
WIPO (PCT)
Prior art keywords
light receiving
shared
circuit
pixel
shared circuit
Prior art date
Application number
PCT/JP2006/305861
Other languages
English (en)
Japanese (ja)
Inventor
Tsuyoshi Higuchi
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2006/305861 priority Critical patent/WO2007108129A1/fr
Priority to JP2008506131A priority patent/JPWO2007108129A1/ja
Publication of WO2007108129A1 publication Critical patent/WO2007108129A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14641—Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof

Definitions

  • the present invention generally relates to a solid-state imaging device, and more particularly to a layout of a CMOS solid-state imaging device.
  • a pixel array is formed by arranging light receiving elements made of photodiodes vertically and horizontally, and a pixel in which charges accumulated by photoelectric conversion are selected by designating rows and columns Force can also be read.
  • each pixel is provided with, for example, a reading transistor (amplifier) and a transfer gate that constitute a source follower circuit. The transfer gate is opened by the selection signal, the pixel signal is amplified by the readout transistor, and the amplified pixel signal is read out through the output signal line extending in the column direction.
  • Each pixel is provided with a reset transistor for resetting the light receiving element.
  • the readout transistors and reset transistors are not provided on a one-to-one basis for each pixel, but for a pixel group having a plurality of pixel forces. It is preferable to provide a set of amplifiers and reset transistors.
  • a circuit portion shared by a plurality of pixels is called a shared circuit.
  • the transfer gate corresponding to each pixel is used to select one pixel in one pixel group, and shared to select one pixel group from a plurality of pixel groups.
  • a configuration in which a selection transistor is provided as part of the circuit.
  • FIG. 1 is a diagram showing an example of a conventional layout of a CMOS solid-state imaging device that shares a shared circuit with four pixels.
  • the solid-state imaging device in FIG. 1 includes a light receiving unit 10, a transfer gate 11, a shared circuit 12, a shared connection signal line 13, a control signal line 14, and an output signal line 15.
  • the light receiving unit 10 is formed of a photodiode, and has a charge according to input light by photoelectric conversion. Accumulate.
  • the light receiving unit 10 is coupled to the shared circuit 12 via the transfer gate 11 and the shared connection signal line 13.
  • four continuous light receiving units 10 arranged in a vertical line form one pixel group, and all the light receiving units 10 of one pixel group are coupled to one shared circuit 12.
  • the shared circuit 12 includes a read transistor, a reset transistor, a selection transistor, and the like.
  • the pixel signal read from the light receiving unit 10 via the transfer gate 11 and the shared connection signal line 13 is amplified by the read transistor of the shared circuit 12, and then output to the outside of the pixel array via the output signal line 15. Read out.
  • the control signal line 14 transmits a signal for selecting the transfer gate 11, a signal for selecting the shared circuit 12, a signal for resetting the light receiving unit 10 by the reset transistor of the shared circuit 12, and the like.
  • FIG. 2 is a diagram showing another example of a conventional layout of a CMOS type solid-state imaging device in which a shared circuit is shared by four pixels.
  • FIG. 2 the same components as those in FIG. 1 are referred to by the same numerals, and a description thereof will be omitted.
  • two vertically continuous pixels and two horizontally continuous pixels are combined to form one pixel group, and all the light receiving units 10 of one pixel group are combined into one shared circuit 12. Combined.
  • FIGS. 1 and 2 have a problem in that the arrangement in which the intervals in the vertical direction of the light receiving portions 10 are equally spaced is not spatially uniform. In general, incident light can be detected more efficiently when the pixels are uniformly arranged at equal intervals. When the pixel spacing is not equal and non-uniform as shown in FIGS. 1 and 2, the sensitivity for detecting incident light is degraded.
  • FIG. 3 is a diagram showing still another example of a conventional layout of a CMOS-type solid-state imaging device in which a shared circuit is shared by four pixels.
  • the same components as those in FIG. 1 are referred to by the same numerals, and a description thereof will be omitted.
  • FIG. 3 In the configuration of FIG. 3, four consecutive light receiving units 10 arranged in a vertical row form one pixel group, and all the light receiving units 10 of one pixel group are a pair of shared circuits 12-1 and 12. — Combined with 2. That is, one shared circuit 12 in the configuration of FIG. 1 is divided into two shared circuits 12-1 and 12-2 in the configuration of FIG. In this way, by dividing the circuit into two shared circuits 12-1 and 12-2 and distributing the space used for the shared circuit, the configuration of FIG. 3 is compared with the configuration of FIGS. 1 and 2. The intervals of the light receiving parts 10 are made closer to the same interval. [0011] With the layout of FIG. 3, the problem that the detection sensitivity of incident light is deteriorated can be avoided to some extent.
  • the dispersion power of the distance from the shared circuit 12-2 to the light receiving unit at the coupling destination is larger in the configuration of FIG. 3 than in the case of FIGS. If the distance to the light receiving part force sharing circuit varies in this way, the electrical characteristics of each pixel will be different! / ⁇ , and the image quality of the captured image will be adversely affected.
  • Patent Document 1 shows a configuration in which a transistor for amplifying and transferring a signal is shared by two pixels.
  • Patent Document 1 Japanese Unexamined Patent Application Publication No. 2004-14802
  • an object of the present invention is to provide a solid-state imaging device having a layout in which pixels are evenly arranged without adversely affecting the image quality of a captured image.
  • the solid-state imaging device includes a plurality of first light receiving units arranged in one or a plurality of columns, and a plurality of second light receiving units arranged in one or a plurality of columns different from the one or the plurality of columns.
  • a predetermined number of light receiving units and a plurality of first light receiving units are formed to form a plurality of pixel groups, and a first shared circuit coupled to each pixel group in a one-to-one relationship and a plurality of second light receiving units are provided.
  • a predetermined number of pixels are grouped together to form a plurality of pixel groups, and each pixel group includes a second shared circuit that is coupled on a one-to-one basis. Between the two adjacent pixel groups configured by the first light receiving unit. Is characterized in that a second shared circuit is arranged.
  • the shared circuit force is also received by each light receiving element while realizing uniform arrangement with pixel intervals approximately equal to each other.
  • the distance to the part can be made substantially constant.
  • FIG. 1 is a diagram showing an example of a conventional layout of a CMOS type solid-state imaging device that shares a shared circuit with four pixels.
  • FIG. 2 is a diagram showing another example of a conventional layout of a CMOS-type solid-state imaging device that shares a shared circuit with four pixels.
  • FIG. 3 is a diagram showing still another example of a conventional layout of a CMOS-type solid-state imaging device that shares a shared circuit with four pixels.
  • FIG. 4 is a diagram showing an example of a configuration of a solid-state imaging device to which the present invention is applied.
  • FIG. 5 is a diagram showing a first embodiment of a layout of a pixel array according to the present invention.
  • FIG. 6 is a view showing the same layout as the pixel array in FIG. 5 together with a cutting line for cross-sectional illustration.
  • FIG. 7 is a cross-sectional view of a pixel array cut along a cutting line AA ′ in FIG.
  • FIG. 8 is a cross-sectional view of a pixel array cut along a cutting line BB ′ in FIG.
  • FIG. 9 is a cross-sectional view of a pixel array cut along a cutting line CC ′ in FIG.
  • FIG. 10 is a cross-sectional view of a pixel array cut along a cutting line DD ′ in FIG.
  • FIG. 11 is a cross-sectional view of a pixel array cut along a cutting line EE ′ in FIG.
  • FIG. 12 is a diagram showing an example of an equivalent circuit of a circuit corresponding to one pixel group in the pixel array shown in FIG.
  • FIG. 13 is a diagram showing another example of an equivalent circuit of a circuit corresponding to one pixel group in the pixel array shown in FIG.
  • FIG. 14 is a diagram showing a second example of the layout of the pixel array according to the present invention.
  • FIG. 15 is a diagram showing an example of an equivalent circuit of a circuit corresponding to one pixel group in the pixel array shown in FIG.
  • FIG. 16 is a diagram showing another example of an equivalent circuit of a circuit corresponding to one pixel group in the pixel array shown in FIG.
  • FIG. 17 is a diagram showing a third embodiment of the layout of the pixel array according to the present invention.
  • FIG. 18A is a diagram showing a fourth example of the layout of the pixel array according to the present invention.
  • FIG. 18B is a diagram showing a fourth example of the layout of the pixel array according to the present invention. Explanation of symbols
  • FIG. 4 is a diagram showing an example of the configuration of a solid-state imaging device to which the present invention is applied. 4 includes a pixel array 20, a control circuit 21, a shift register 22, a pixel control signal driver 23, a control signal line 24, an output signal line 25, a pixel readout circuit 26, and a bus circuit 27.
  • the pixel array 20 is a pixel array formed by arranging light receiving elements made of photodiodes vertically and horizontally.
  • the pixel array 20 is provided with a transfer gate corresponding to each pixel on a one-to-one basis, and with a shared circuit including a readout transistor, a reset transistor, and the like shared among a plurality of pixels.
  • the control circuit 21 functions to read out image data from the pixel array 20 by controlling each part of the solid-state imaging device.
  • the shift register 22 includes a plurality of internal registers that correspond one-to-one to a plurality of rows of the pixel array 20, and the internal registers are connected in series to form a shift register. Is configured.
  • the shift register 22 operates under the control of the control circuit 21 and functions to sequentially select the rows of the pixel array 20 by sequentially shifting the register storage data.
  • the pixel control signal driver 23 drives the control signal line 24 corresponding to the row specified by the shift register 22, and outputs a pixel signal for one row from the pixel corresponding to the specified row in the pixel array 20. read out.
  • the read pixel signal is supplied to the pixel readout circuit 26 via the output signal line 25.
  • the pixel readout circuit 26 functions to read out an image signal while reducing noise by, for example, a noise cancellation circuit.
  • the image signal for one row read by the pixel reading circuit 26 is supplied to the control circuit 21 via the bus circuit 27 while sequentially selecting pixels in the horizontal direction.
  • FIG. 5 is a diagram showing a first example of the layout of the pixel array according to the present invention.
  • the pixel array 20 in FIG. 5 includes a light receiving unit 30, a transfer gate 31, a shared circuit 32, a shared connection signal line 33, a control signal line 34, and an output signal line 35.
  • the light receiving unit 30 includes a photodiode, and accumulates electric charge having a strength corresponding to input light by photoelectric conversion.
  • the light receiving unit 30 is coupled to the shared circuit 32 via the transfer gate 31 and the shared connection signal line 33.
  • four continuous light receiving units 30 arranged in a vertical line form one pixel group, and all the light receiving units 30 of one pixel group are coupled to one shared circuit 32.
  • the shared circuit 32 includes a read transistor and a reset transistor, and may further include a selection transistor.
  • the pixel signal read from the light receiving unit 30 via the transfer gate 31 and the shared connection signal line 33 is amplified by the read transistor of the shared circuit 32, and then output to the outside of the pixel array via the output signal line 35. Read out.
  • the control signal line 34 transmits a signal for selecting the transfer gate 31, a signal for selecting the shared circuit 32, a signal for resetting the light receiving unit 30 by the reset transistor of the shared circuit 32, and the like.
  • the pixel array 20 in FIG. 5 further includes a light receiving unit 40, a transfer gate 41, a shared circuit 42, and a shared connection signal line 43.
  • the light receiving unit 40, the transfer gate 41, the shared circuit 42, and the shared connection signal line 43 are circuit elements equivalent to the light receiving unit 30, the transfer gate 31, the shared circuit 32, and the shared connection signal line 33, respectively.
  • There are four receivers 40 One pixel group is formed and coupled to one shared circuit 42.
  • the pixel array 20 in FIG. 5 further includes a light receiving unit 50, a transfer gate 51, a shared circuit 52, and a shared connection signal line 53.
  • the light receiving unit 50, the transfer gate 51, the shared circuit 52, and the shared connection signal line 53 are circuit elements equivalent to the light receiving unit 30, the transfer gate 31, the shared circuit 32, and the shared connection signal line 33, respectively. .
  • Four light receiving portions 50 form one pixel group and are coupled to one shared circuit 52.
  • the light receiving units arranged in a predetermined row.
  • a predetermined number (4) of (30, 50) are grouped together to form a plurality of pixel groups, and each pixel group is coupled to a corresponding shared circuit (32, 52).
  • a predetermined number (4) of light receiving units (40) arranged in other rows are grouped between two adjacent pixel groups (that is, a pixel group including the light receiving unit 30 and a pixel group including the light receiving unit 50).
  • a shared circuit (42) coupled to the pixel group formed in this manner is disposed.
  • FIG. 6 is a diagram showing the same layout as the pixel array in FIG. 5 together with a cutting line for cross-sectional illustration.
  • the same elements as those of FIG. 5 are referred to by the same numerals, and a description thereof will be omitted.
  • each circuit element corresponding to an odd-numbered pixel column is shown as a light receiving unit 30, a transfer gate 31, a shared circuit 32, and a shared connection signal line 33, and each circuit element corresponding to an even-numbered pixel column Elements are shown as a light receiving unit 40, a transfer gate 41, a shared circuit 42, and a signal line 43 for shared connection.
  • FIG. 7 is a cross-sectional view of the pixel array cut along the cutting line AA ′ in FIG.
  • the same elements as those of FIG. 6 are referred to by the same numerals, and a description thereof will be omitted.
  • the light receiving unit 30 and the shared circuit 32 are formed in the diffusion layer of the semiconductor substrate 60.
  • a transfer gate 31 is formed in the polysilicon layer on the semiconductor substrate 60, and a control signal line 34 is formed in the first metal layer thereon.
  • FIG. 6 only shows the approximate position and direction of the control signal line 34; in practice, one transfer gate 31 (one on the drawing is shown) as shown in FIG. In reality, one control signal line is provided for a plurality of transfer gates 31) on the same row.
  • a shared connection signal line 33 is formed in the second metal layer on the first metal layer. Common with signal line 33 for shared connection The circuit 32 and the shared connection signal line 33 and the diffusion layer 62 of the transfer gate 31 (the drain end of the transistor constituting the transfer gate) are connected via the contact hole 61, respectively.
  • FIG. 8 is a cross-sectional view of the pixel array taken along the cutting line BB ′ of FIG.
  • the same components as those in FIGS. 6 and 7 are referred to by the same numerals, and a description thereof will be omitted.
  • control signal line 34 and the transfer gate 31 the gate end of the transistor constituting the transfer gate
  • control signal line 34 and the shared circuit 32 respectively.
  • a shared connection signal line 33 is formed on the second metal layer above the first metal layer.
  • FIG. 9 is a cross-sectional view of the pixel array taken along the cutting line CC ′ of FIG. 9, the same components as those in FIGS. 6 to 8 are referred to by the same numerals, and a description thereof will be omitted.
  • an output signal line 35 is formed in the second metal layer.
  • FIG. 10 is a cross-sectional view of the pixel array cut along the cutting line DD ′ in FIG. In Figure 10
  • the light receiving unit 30 and the light receiving unit 40 are formed on the semiconductor substrate 60.
  • an output signal line 35 and a shared connection signal line 43 for the light receiving unit 40 are formed.
  • FIG. 11 is a cross-sectional view of the pixel array cut along the cutting line EE ′ of FIG.
  • the same components as those in FIGS. 6 to 10 are referred to by the same numerals, and a description thereof will be omitted.
  • Transfer gates 31 and 41 are formed in the polysilicon layer. In this case, the cut surface and the extending direction of the transfer gates 31 and 41 are the same, and the transfer gates 31 and 41 are continuously provided as one polysilicon electrode from the end to the end of the drawing.
  • a control signal line 34 is formed in the first metal layer on the polysilicon layer. The control signal line 34 and the transfer gates 31 and 41 are coupled by a contact hole 65 at the position of each transfer gate.
  • FIG. 12 is a diagram showing an example of an equivalent circuit of a circuit corresponding to one pixel group in the pixel array shown in FIG.
  • the transfer gates 31 are provided in one-to-one correspondence with the light receiving units 30. Control signals TG1 to TG4 are supplied to the gate ends of the four transfer gates 31.
  • the shared circuit 32 includes a read transistor 71 and a reset transistor 72.
  • the read transistor 71 has a source terminal coupled to the reference potential VR and a drain terminal coupled to the output signal line 35.
  • the control signals TG 1 to TG 4 becomes HIGH
  • the corresponding transfer gate 31 becomes conductive, and the charge of the corresponding light receiving unit 30 is supplied to the gate terminal of the read transistor 71.
  • a voltage depending on the charge amount of the light receiving unit 30 appears on the output signal line 35. In this way, the pixel signal of the selected pixel can be read out.
  • the reset transistor 72 is turned on when the reset signal RST becomes HIGH, and resets the selected light receiving unit 30 to the reference voltage VR. By such a reset operation, each pixel of the pixel array 20 can be set to the same initial state.
  • FIG. 13 is a diagram showing another example of an equivalent circuit of a circuit corresponding to one pixel group in the pixel array shown in FIG.
  • the same elements as those of FIG. 12 are referred to by the same numerals, and a description thereof will be omitted.
  • the shared circuit 32 further includes a selection transistor 73 in addition to the read transistor 71 and the reset transistor 72.
  • the selection transistor 73 is inserted so as to be connected in series to the read transistor 71, and a selection signal SEL is applied to the gate terminal thereof.
  • the selection signal SEL becomes HIGH, the read pixel signal of the shared circuit 32 is supplied to the output signal line 35.
  • FIG. 14 is a diagram showing a second example of the layout of the pixel array according to the present invention. 14 includes a light receiving unit 130, a transfer gate 131, a shared circuit 132, a control signal line 134, and an output signal line 135.
  • the light receiving unit 130 includes a photodiode, and accumulates a charge having a strength corresponding to input light by photoelectric conversion.
  • the light receiving unit 130 is coupled to the shared circuit 132 via the transfer gate 131.
  • four light receiving units 130 force S are arranged side by side in the vertical direction and two in the horizontal direction.
  • One pixel group is formed.
  • the shared circuit 132 includes a read transistor and a reset transistor, and may further include a selection transistor.
  • the pixel signal read from the light receiving unit 130 via the transfer gate 131 is amplified by the reading transistor of the shared circuit 132 and then read out to the outside of the pixel array via the output signal line 135.
  • the control signal line 134 transmits a signal for selecting the transfer gate 131, a signal for selecting the shared circuit 132, a signal for resetting the light receiving unit 130 by the reset transistor of the shared circuit 132, and the like.
  • the pixel array in FIG. 14 further includes a light receiving unit 140, a transfer gate 141, and a shared circuit 142.
  • the light receiving unit 140, the transfer gate 141, and the shared circuit 142 are circuit elements equivalent to the light receiving unit 130, the transfer gate 131, and the shared circuit 132, respectively.
  • Four light receiving portions 140 form one pixel group and are coupled to one shared circuit 142.
  • the pixel array in FIG. 14 further includes a light receiving unit 150, a transfer gate 151, and a shared circuit 152.
  • the light receiving unit 150, the transfer gate 151, and the shared circuit 152 are circuit elements equivalent to the light receiving unit 130, the transfer gate 131, and the shared circuit 132, respectively.
  • Four light receiving portions 150 form one pixel group and are coupled to one shared circuit 152.
  • a predetermined number (four) of light receiving sections (130, 150) arranged in a predetermined row (predetermined two rows) are collected.
  • a plurality of pixel groups are formed, and each pixel group is coupled to a corresponding shared circuit (132, 152).
  • a predetermined number of light receiving units (140) arranged in other columns are provided.
  • a shared circuit (142) that is coupled to a pixel group formed by collecting (four) each is arranged.
  • FIG. 15 is a diagram illustrating an example of an equivalent circuit of a circuit corresponding to one pixel group in the pixel array illustrated in FIG.
  • four light receiving sections 130 that are photodiodes are coupled to a shared circuit 132 via a transfer gate 131 that is a transistor.
  • the transfer gates 131 are provided in one-to-one correspondence with the respective light receiving units 130.
  • Four Control signals TGI to TG4 are supplied to the gate end of the transfer gate 131.
  • the shared circuit 132 includes a read transistor 171 and a reset transistor 172.
  • Read transistor 171 has a source terminal coupled to reference potential VR and a drain terminal coupled to output signal line 135.
  • the control signals TG 1 to TG 4 becomes HIGH
  • the corresponding transfer gate 131 becomes conductive, and the charge of the corresponding light receiving unit 130 is supplied to the gate terminal of the reading transistor 171.
  • a voltage depending on the charge amount of the light receiving unit 130 appears on the output signal line 135. In this way, the pixel signal of the selected pixel can be read out.
  • each pixel in the pixel array can be set to the same initial state.
  • FIG. 16 is a diagram showing another example of an equivalent circuit of a circuit corresponding to one pixel group in the pixel array shown in FIG.
  • the same elements as those of FIG. 15 are referred to by the same numerals, and a description thereof will be omitted.
  • the shared circuit 132 further includes a selection transistor 173 in addition to the read transistor 171 and the reset transistor 172.
  • the selection transistor 173 is inserted so as to be connected in series with the readout transistor 171 and a selection signal SEL is applied to the gate end thereof.
  • the selection signal SEL becomes HIGH, the readout pixel signal of the shared circuit 132 is supplied to the output signal line 135.
  • FIG. 17 is a diagram showing a third example of the layout of the pixel array according to the present invention.
  • two pixels are combined into one pixel group, and one shared circuit is assigned to each pixel group one-on-one.
  • the pixel array in FIG. 17 includes a light receiving unit 230, a transfer gate 231, a shared circuit 232, a control signal line 234, and an output signal line 235.
  • the configuration and function of each circuit element are the same as those in the first and second embodiments, and a description thereof will be omitted.
  • the shared circuit 2 32 includes a read transistor and a reset transistor, and further includes a selection transistor. May include a transistor.
  • the pixel array in FIG. 17 further includes a light receiving unit 240, a transfer gate 241, and a shared circuit 242.
  • the light receiving unit 240, the transfer gate 241 and the shared circuit 242 are circuit elements equivalent to the light receiving unit 230, the transfer gate 231 and the shared circuit 232, respectively.
  • Two light receiving units 240 form one pixel group and are coupled to one shared circuit 242.
  • the pixel array in FIG. 17 further includes a light receiving unit 250, a transfer gate 251, and a shared circuit 252.
  • the light receiving unit 250, the transfer gate 251 and the shared circuit 252 are circuit elements equivalent to the light receiving unit 230, the transfer gate 231 and the shared circuit 232, respectively.
  • Two light receiving portions 250 form one pixel group and are coupled to one shared circuit 252.
  • a plurality of pixel groups are formed by collecting a predetermined number (two) of light receiving portions (230, 250) arranged in a predetermined row. Then, each pixel group is coupled to the corresponding shared circuit (232, 252). In addition, a predetermined number (two) of light receiving units (24 0) arranged in other rows are arranged between two adjacent pixel groups (that is, a pixel group including the light receiving unit 230 and a pixel group including the light receiving unit 250). A shared circuit (242) coupled to the pixel group formed together is arranged.
  • FIG. 18A and FIG. 18B are diagrams showing a fourth embodiment of the layout of the pixel array according to the present invention.
  • the pixel array layout shown in FIG. 18A and the pixel array layout shown in FIG. 18B are divided into two parts for the sake of illustration. Actually, the pixel array layout is shown in FIG. One pixel array layout is configured.
  • eight pixels are grouped into one pixel group, and one shared circuit is assigned to each pixel group on a one-to-one basis.
  • the pixel arrays in FIGS. 18A and 18B include a light receiving unit 330, a transfer gate 331, a shared circuit 332, a shared connection signal line 333, a control signal line 334, and an output signal line 335.
  • the configuration and function of each circuit element are the same as those in the first to third embodiments, and the description thereof is omitted.
  • the shared circuit 332 includes a read transistor and a reset transistor, and further includes a selection transistor. May include a transistor.
  • the pixel arrays in FIGS. 18A and 18B further include eight light receiving portions 340, a transfer gate 341, a shared circuit 342, and a shared connection signal line 343 that are continuously arranged in a vertical line.
  • the light receiving unit 340, the transfer gate 341, the shared circuit 342, and the shared connection signal line 343 are circuit elements equivalent to the light receiving unit 330, the transfer gate 331, the shared circuit 332, and the shared connection signal line 333, respectively.
  • These eight light receiving units 340 form one pixel group and are coupled to one shared circuit 342.
  • the pixel arrays in FIGS. 18A and 18B further include a light receiving unit 350, a transfer gate 351, a shared circuit 352, and a shared connection signal line 353 that are continuously arranged in a vertical line.
  • the light receiving unit 350, the transfer gate 351, the shared circuit 352, and the shared connection signal line 353 are circuit elements equivalent to the light receiving unit 330, the transfer gate 331, the shared circuit 332, and the shared connection signal line 333, respectively.
  • These eight light receiving parts 350 form one pixel group and are coupled to one shared circuit 352.
  • a plurality of pixels in which a predetermined number (eight) of light receiving portions (330, 350) arranged in a predetermined row are grouped.
  • a group is formed, and each pixel group is coupled to a corresponding shared circuit (332, 352).
  • a predetermined number (eight) of light receiving units (340) arranged in other rows are grouped between two adjacent pixel groups (that is, a pixel group including the light receiving unit 330 and a pixel group including the light receiving unit 350).
  • a shared circuit (342) coupled to the formed pixel group is disposed.

Abstract

La présente invention concerne un capteur d'image à l'état solide qui comprend : une pluralité de premières parties de réception de la lumière placées sur une ou plusieurs lignes, une pluralité de secondes parties de réception de la lumière placées sur une ou plusieurs lignes différentes de la ou des lignes susmentionnées, un premier circuit partagé raccordé en individuel à chaque groupe de pixels formé en combinant un nombre prédéterminé de premières parties de réception de la lumière, ainsi qu'un second circuit partagé relié en individuel à chaque groupe de pixels formé en associant un nombre prédéterminé de secondes parties de réception de la lumière. Le capteur d'image à l'état solide est caractérisé en ce que le second circuit partagé est placé entre les deux groupes de pixels adjacents composés des premières parties de réception de la lumière.
PCT/JP2006/305861 2006-03-23 2006-03-23 Capteur d'image a l'etat solide WO2007108129A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/JP2006/305861 WO2007108129A1 (fr) 2006-03-23 2006-03-23 Capteur d'image a l'etat solide
JP2008506131A JPWO2007108129A1 (ja) 2006-03-23 2006-03-23 固体撮像素子

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2006/305861 WO2007108129A1 (fr) 2006-03-23 2006-03-23 Capteur d'image a l'etat solide

Publications (1)

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WO2007108129A1 true WO2007108129A1 (fr) 2007-09-27

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JP2012216192A (ja) * 2011-03-25 2012-11-08 Japan Display Central Co Ltd 表示装置及び表示装置の駆動方法
US8350939B2 (en) 2008-10-01 2013-01-08 Micron Technology, Inc. Vertical 4-way shared pixel in a single column with internal reset and no row select
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JP2006073733A (ja) * 2004-09-01 2006-03-16 Canon Inc 固体撮像装置及び固体撮像システム

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US8077236B2 (en) 2008-03-20 2011-12-13 Aptina Imaging Corporation Method and apparatus providing reduced metal routing in imagers
US8350939B2 (en) 2008-10-01 2013-01-08 Micron Technology, Inc. Vertical 4-way shared pixel in a single column with internal reset and no row select
US9210347B2 (en) 2008-10-01 2015-12-08 Micron Technology, Inc. Vertical 4-way shared pixel in a single column with internal reset and no row select
US9756269B2 (en) 2008-10-01 2017-09-05 Micron Technology, Inc. Pixel array with shared pixels in a single column and associated devices, systems, and methods
US9979915B2 (en) 2008-10-01 2018-05-22 Micron Technology, Inc. Pixel array with shared pixels in a single column and associated devices, systems, and methods
JP2011199196A (ja) * 2010-03-23 2011-10-06 Toshiba Corp 固体撮像装置
US8542304B2 (en) 2010-03-23 2013-09-24 Kabushiki Kaisha Toshiba Solid-state imaging device
JP2012216192A (ja) * 2011-03-25 2012-11-08 Japan Display Central Co Ltd 表示装置及び表示装置の駆動方法
US10456023B2 (en) 2015-10-02 2019-10-29 Olympus Corporation Image sensor, endoscope, and endoscope system

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