WO2009148055A1 - Dispositif de prise d'images à semi-conducteur - Google Patents

Dispositif de prise d'images à semi-conducteur Download PDF

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Publication number
WO2009148055A1
WO2009148055A1 PCT/JP2009/060070 JP2009060070W WO2009148055A1 WO 2009148055 A1 WO2009148055 A1 WO 2009148055A1 JP 2009060070 W JP2009060070 W JP 2009060070W WO 2009148055 A1 WO2009148055 A1 WO 2009148055A1
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WIPO (PCT)
Prior art keywords
pixel
unit
signal
signal output
pixel portion
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PCT/JP2009/060070
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English (en)
Japanese (ja)
Inventor
行信 杉山
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浜松ホトニクス株式会社
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Publication of WO2009148055A1 publication Critical patent/WO2009148055A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers

Definitions

  • the present invention relates to a solid-state imaging device.
  • a solid-state imaging device includes a light receiving unit in which a plurality of pixel units each including a photodiode are two-dimensionally arranged, a signal output unit that outputs an electric signal having a value corresponding to the amount of electric charge generated in the photodiode of each pixel unit, And a control unit for controlling the output of an electrical signal by the signal output unit for each pixel unit.
  • the solid-state imaging device can obtain an image of the intensity distribution of the light input to the light receiving unit based on the electrical signal output from the signal output unit.
  • Patent Document 1 discloses a solid-state imaging device capable of performing high-resolution imaging and low-resolution imaging.
  • the solid-state imaging device disclosed in Patent Document 1 performs high-resolution imaging by individually outputting an electrical signal for each of a plurality of pixel units included in a light receiving unit.
  • this solid-state imaging device performs low-resolution imaging by adding electrical signals for a certain number of pixel units among a plurality of pixel units included in the light receiving unit. Such a low-resolution imaging operation is called a binning operation.
  • the solid-state imaging device disclosed in Patent Document 1 cannot perform high-speed imaging when switching between high-resolution imaging and low-resolution imaging, for example.
  • the present invention has been made to solve the above-described problems, and an object thereof is to provide a solid-state imaging device capable of performing high-resolution imaging and low-resolution imaging at high speed.
  • the solid-state imaging device includes (1) I ⁇ J unit regions A 1,1 to A I, J that are two-dimensionally arranged in I rows and J columns, and the light receiving surfaces are M rows.
  • the M ⁇ n pixel regions are two-dimensionally arrayed in n rows a 1,1 ⁇ a M, consist n, each unit region a i, each pixel area in the j a m, n is the first group and the second 1st pixel part Pm, n which is divided into any of a group and contains the photodiode formed in each pixel area am , n included in the 1st group in each unit area Ai, j comprises The photodiodes formed in each pixel region am , n included in the second group in each unit region A i, j are connected to each other in parallel, so that the second pixel portion Q i, j is substantially
  • configured light receiving unit outputs a first electrical signal having a value corresponding to the amount of charges generated in the (2) each
  • M and N are integers of 2 or more, I is an integer of 2 or more and less than M, J is an integer of 2 or more and less than N, m is an integer of 1 or more and M or less, and n is 1 These are integers of N or less, i is an integer of 1 or more and I or less, and j is an integer of 1 or more and J or less.
  • the rows and columns for the M ⁇ N pixel regions a 1,1 to a M, N and the rows and columns for the I ⁇ J unit regions A 1,1 to A I, J are different. To do.
  • the light receiving surface of the light receiving unit includes I ⁇ J unit regions A 1,1 to A I, J that are two-dimensionally arranged in I rows and J columns, and M rows and N columns.
  • Each unit region A i, each pixel region a m in j, n is divided into either of the first group and second group, each unit region A i, each pixel region a included in the first group in the j
  • a first pixel portion P m, n including photodiodes individually formed in m, n is configured and formed in each pixel region am , n included in the second group in each unit region A i, j .
  • the photodiodes are connected to each other in parallel to substantially constitute the second pixel portion Q i, j .
  • a first electric signal having a value corresponding to the amount of electric charge generated in the photodiode of each first pixel unit P m, n is output, and the photodiode of each second pixel unit Q i, j
  • the second electric signal having a value corresponding to the amount of electric charge generated in the step is output.
  • the control unit controls the output of the first electric signal by the signal output unit for each first pixel unit P m, n and outputs the second electric signal by the signal output unit for each second pixel unit Q i, j Is controlled.
  • High-speed high-resolution imaging can be performed using the first pixel portion P m, n
  • high-speed low-resolution imaging can be performed using the second pixel portion Q i, j .
  • the solid-state imaging device can perform high-resolution imaging and low-resolution imaging at high speed.
  • FIG. 1 is a diagram illustrating a schematic configuration of a solid-state imaging device 1 according to the present embodiment.
  • FIG. 2 is a diagram illustrating a configuration of the solid-state imaging device 1 according to the present embodiment.
  • FIG. 3 is a diagram illustrating a circuit configuration of each of the first pixel unit P m, n and the holding circuit 23 n included in the solid-state imaging device 1 according to the present embodiment.
  • FIG. 4 is a diagram illustrating a circuit configuration of the difference calculation circuit 25 included in the solid-state imaging device 1 according to the present embodiment.
  • FIG. 5 is a diagram illustrating a circuit configuration of each of the second pixel unit Q i, j and the holding circuit 24 j included in the solid-state imaging device 1 according to the present embodiment.
  • FIG. 1 is a diagram illustrating a schematic configuration of a solid-state imaging device 1 according to the present embodiment.
  • FIG. 2 is a diagram illustrating a configuration of the solid-state imaging device 1 according to the present embodiment.
  • FIG. 6 is a diagram illustrating a circuit configuration of the difference calculation circuit 26 included in the solid-state imaging device 1 according to the present embodiment.
  • FIG. 7 is a diagram illustrating a configuration example of the light receiving unit 10 of the solid-state imaging device 1 according to the present embodiment.
  • FIG. 8 is a diagram illustrating a first arrangement example of the first pixel unit P m, n and the second pixel unit Q i, j in the light receiving unit 10 included in the solid-state imaging device 1 according to the present embodiment.
  • Figure 9 is a diagram showing a second arrangement example of the first pixel portion P m in the photodetecting section 10 of embodiment included in the solid-state imaging device 1 according to the embodiment, n and the second pixel unit Q i, j.
  • FIG. 8 is a diagram illustrating a circuit configuration of the difference calculation circuit 26 included in the solid-state imaging device 1 according to the present embodiment.
  • FIG. 7 is a diagram illustrating a configuration example of the light receiving unit 10 of the solid-state imaging device
  • FIG. 10 is a diagram illustrating a third arrangement example of the first pixel unit P m, n and the second pixel unit Q i, j in the light receiving unit 10 included in the solid-state imaging device 1 according to the present embodiment.
  • FIG. 11 is a diagram illustrating a layout example of the light receiving unit 10 included in the solid-state imaging device 1 according to the present embodiment.
  • 12 is a cross-sectional view taken along the line A-A ′ in the layout example shown in FIG. 11.
  • FIG. 13 is a configuration diagram of a solid-state imaging device 2 according to another embodiment.
  • FIG. 14 shows a fourth arrangement example of the first pixel unit P m, n , the second pixel unit Q i, j, and the third pixel unit R m, n in the light receiving unit 10 included in the solid-state imaging device of the modification.
  • FIG. 15 shows a fifth arrangement example of the first pixel unit P m, n , the second pixel unit Q i, j, and the third pixel unit R m, n in the light receiving unit 10 included in the solid-state imaging device of the modification.
  • FIG. 1 is a diagram showing a schematic configuration of a solid-state imaging device 1 according to the present embodiment.
  • the solid-state imaging device 1 shown in this figure includes a light receiving unit 10, a first signal output circuit 21, a second signal output circuit 22, a first control circuit 31, and a second control circuit 32.
  • the light receiving surface of the light receiving unit 10 includes I ⁇ J unit regions A 1,1 to A I, J that are two-dimensionally arranged in I rows and J columns, and M ⁇ N that is two-dimensionally arranged in M rows and N columns. It consists of N pixel areas a 1,1 to a M, N.
  • the unit area A i, j is located in the i-th row and j-th column, and the pixel area am , n is located in the m-th row and n-th column.
  • Each unit region A i, each pixel region a m in j, n is divided into either of the first group and second group, each unit region A i, each pixel region a included in the first group in the j
  • a first pixel portion P m, n including photodiodes individually formed in m, n is configured and formed in each pixel region am , n included in the second group in each unit region A i, j .
  • the photodiodes are connected to each other in parallel to substantially constitute the second pixel portion Q i, j .
  • Each first pixel unit P m, n has a common configuration, and includes a photodiode that generates an amount of charge corresponding to the amount of incident light.
  • Each of the second pixel portions Q i, j preferably has a common configuration, and includes a photodiode that generates an amount of charge corresponding to the amount of incident light. Details of the light receiving unit 10 will be described later.
  • M and N are integers of 2 or more.
  • I is an integer of 2 or more and less than M
  • J is an integer of 2 or more and less than N
  • m is an integer from 1 to M
  • n is an integer from 1 to N
  • i is an integer from 1 to I
  • j is an integer from 1 to J.
  • I is preferably a divisor of M
  • J is preferably a divisor of N.
  • M and N are 1024
  • I and J are 128.
  • one second pixel portion Q is provided for 8 ⁇ 8 first pixel portions P.
  • the rows and columns for the M ⁇ N pixel regions a 1,1 to a M, N and the rows and columns for the I ⁇ J unit regions A 1,1 to A I, J are different. To do.
  • Each first pixel portion P m, n and each second pixel portion Q i, j may be of the PPS (Passive Pixel Sensor) type, but of the APS (Active Pixel Sensor) type. preferable. That is, each first pixel portion P m, n and each second pixel portion Q i, j include an amplification MOS transistor for inputting the charge generated by the photodiode, and the amplification MOS transistor according to the input charge amount. It is preferable to output an electrical signal.
  • Each first pixel unit P m, n included in the light receiving unit 10 is connected to the first signal output circuit 21.
  • the first signal output circuit 21 outputs a first electric signal having a value corresponding to the amount of charge generated in the photodiode of each first pixel unit P m, n . More specifically, the output terminal of each first pixel unit P m, n in the n-th column is connected to the first signal output circuit 21 by a common readout wiring.
  • the first signal output circuit 21 sequentially inputs data from the first pixel portions P m, n in the m-th row in order from the first row to the M-th row and serially inputs these data to the first row. Output as an electrical signal.
  • the first control circuit 31 controls the output of the first electric signal by the first signal output circuit 21 for each first pixel unit P m, n , and includes a first timing control circuit 41, a first row selection circuit, and so on. 51 and a first column selection circuit 61.
  • the first timing control circuit 41 controls the operation timings of the first signal output circuit 21, the first row selection circuit 51, and the first column selection circuit 61.
  • the first row selection circuit 51 sequentially designates each row in the two-dimensional array of the first pixel portions P 1,1 to P M, N of the light receiving unit 10 under the timing control by the first timing control circuit 41, A predetermined control signal is applied to each designated first pixel portion P m, n in the m-th row , and data is output from each first pixel portion P m, n in the m-th row to the first signal output circuit 21.
  • the first row selection circuit 51 includes an M-stage shift register circuit, and each row can be sequentially designated by an output bit of each stage of the shift register circuit.
  • the first column selection circuit 61 sequentially designates each column in the two-dimensional array of the first pixel portions P 1,1 to P M, N of the light receiving unit 10 under the timing control by the first timing control circuit 41. Then, a control signal indicating the designated nth column is given to the first signal output circuit 21, and data from each of the first pixel portions Pm, n in the mth row is sequentially sent from the first signal output circuit 21 to the first signal output circuit 21. One electrical signal is output.
  • the first column selection circuit 61 includes an N-stage shift register circuit, and each column can be sequentially designated by an output bit of each stage of the shift register circuit.
  • Each second pixel unit Q i, j included in the light receiving unit 10 is connected to the second signal output circuit 22.
  • the second signal output circuit 22 outputs a second electric signal having a value corresponding to the amount of charge generated in the photodiode of each second pixel portion Q i, j . More specifically, the output terminal of each second pixel portion Q i, j in the j-th column is connected to the second signal output circuit 22 by a common readout wiring.
  • the second signal output circuit 22 inputs data from the second pixel portions Q i, j in the i-th row in parallel for the first row to the I-th row in parallel and serially inputs these data to the second row. Output as an electrical signal.
  • the second control circuit 32 controls the output of the second electric signal by the second signal output circuit 22 for each second pixel portion Q i, j , and includes a second timing control circuit 42, a second row selection circuit, and the like. 52 and a second column selection circuit 62.
  • the second timing control circuit 42 controls operation timings of the second signal output circuit 22, the second row selection circuit 52, and the second column selection circuit 62.
  • the second row selection circuit 52 sequentially designates each row in the two-dimensional array of the second pixel portions Q 1,1 to Q I, J of the light receiving unit 10, the i each second pixel portion Q i of rows that specified by giving a predetermined control signal to j, and outputs the second pixel portion Q i of the i-th row, the data from the j to the second signal output circuit 22 .
  • the second row selection circuit 52 includes an I-stage shift register circuit, and each row can be sequentially designated by an output bit of each stage of the shift register circuit.
  • the second column selection circuit 62 sequentially designates each column in the two-dimensional array of the second pixel portions Q 1,1 to Q I, J of the light receiving unit 10 under the timing control by the second timing control circuit 42. Then, a control signal indicating the designated j-th column is given to the second signal output circuit 22, and data from each second pixel portion Q i, j in the i-th row is sequentially sent from the second signal output circuit 22 to the second signal output circuit 22. Two electrical signals are output.
  • the second column selection circuit 62 includes a J-stage shift register circuit, and each column can be sequentially designated by the output bit of each stage of the shift register circuit.
  • the first signal output circuit 21 and the second signal output circuit 22 output a first electric signal having a value corresponding to the amount of charge generated in the photodiode PD of each first pixel unit P m, n , and A signal output unit configured to output a second electric signal having a value corresponding to the amount of charge generated in the photodiode PD of the two-pixel unit Q i, j is configured.
  • the first control circuit 31 and the second control circuit 32 control the output of the first electric signal by the signal output unit for each first pixel unit P m, n and output the signal for each second pixel unit Q i, j.
  • the control part which controls the output of the 2nd electric signal by a part is comprised.
  • the first signal output circuit 21 and the second signal output circuit 22 may have the same configuration except for the difference in the number of data that are input in parallel for each row and output serially.
  • the first row selection circuit 51 and the second row selection circuit 52 may have the same configuration except for the point related to the difference in the number of designated rows.
  • the first column selection circuit 61 and the second column selection circuit 62 may have the same configuration except for the point relating to the difference in the number of designated columns.
  • FIG. 2 is a diagram illustrating a configuration of the solid-state imaging device 1 according to the present embodiment.
  • the first pixel portion P m, n located in the m-th row and the n-th column is representatively shown, and the second pixel located in the i-th row and the j-th column is shown.
  • Part Q i, j is shown representatively.
  • the connection relationship between the light receiving unit 10 and the first signal output circuit 21 and the connection relationship between the light receiving unit 10 and the first row selection circuit 51 are related to the first pixel unit P m, n. It is shown.
  • connection relationship between the light receiving unit 10 and the second signal output circuit 22 and the connection relationship between the light receiving unit 10 and the second row selection circuit 52 are related to the second pixel unit Q i, j. It is shown.
  • first signal output circuit 21 components related to the first pixel portion P m, n are shown.
  • second signal output circuit 22 components related to the second pixel portion Q i, j are shown.
  • the first signal output circuit 21 includes N holding circuits 23 1 to 23 N , a difference calculation circuit 25 and an AD conversion circuit 27.
  • the N holding circuits 23 1 to 23 N have a common configuration.
  • Each holding circuit 23 n is connected to the output terminal of each first pixel unit P m, n in the n-th column by a common readout wiring Vline1 (n), and any one of these first pixel units Data output from P m, n and input via the read wiring Vline1 (n) is held, and the held data is output to the wirings Hline_s1 and Hline_n1.
  • the difference calculation circuit 25 inputs two data that arrive via the wirings Hline_s1 and Hline_n1, and outputs data corresponding to the difference between the two data to the AD conversion circuit 27.
  • the AD conversion circuit 27 receives the analog data output from the difference calculation circuit 25 and outputs digital data corresponding to the analog data as a first electric signal.
  • the second signal output circuit 22 includes J holding circuits 24 1 to 24 J , a difference calculation circuit 26, and an AD conversion circuit 28.
  • the J holding circuits 24 1 to 24 J have a common configuration.
  • Each holding circuit 24 j is connected to the output terminal of each second pixel portion Q i, j in the j-th column by a common readout wiring Vline2 (j), and any one of these second pixel portions
  • the data output from Q i, j and input via the read wiring Vline2 (j) is held, and the held data is output to the wirings Hline_s2 and Hline_n2.
  • the difference calculation circuit 26 inputs two data arrived via the wirings Hline_s2 and Hline_n2, and outputs data corresponding to the difference between the two data to the AD conversion circuit 28.
  • the AD conversion circuit 28 receives the analog data output from the difference calculation circuit 26, and outputs digital data corresponding to the analog data as a second electric signal.
  • FIG. 3 is a diagram illustrating a circuit configuration of each of the first pixel unit P m, n and the holding circuit 23 n included in the solid-state imaging device 1 according to the present embodiment.
  • the first pixel portion P m, n is shown as a representative
  • the holding circuit 23 n is shown as a representative.
  • Each first pixel portion P m, n is of the APS type, and includes a photodiode PD and five MOS transistors T1 to T5. As shown in this figure, the transistor T1, the transistor T2, and the photodiode PD are connected in series in order, the reference voltage Vb1 is input to the drain terminal of the transistor T1, and the anode terminal of the photodiode PD is grounded. Has been.
  • the transistor T3 and the transistor T4 are connected in series, the reference voltage Vb2 is input to the drain terminal of the transistor T3, and the source terminal of the transistor T4 is connected to the wiring Vline1 (n).
  • a connection point between the transistor T1 and the transistor T2 is connected to the gate terminal of the transistor T3 through the transistor T5.
  • a constant current source is connected to the wiring Vline1 (n).
  • the amplifying transistor T3 outputs an electric signal having a value corresponding to the amount of charge input to the gate terminal.
  • the Reset1 (m) signal is input to the gate terminal of the reset transistor T1, the Trans1 (m) signal is input to the gate terminal of the transfer transistor T2, and the Address1 (m) signal is input to the gate of the output selection transistor T4.
  • the Hold1 (m) signal is input to the terminal of the transistor T5.
  • the Reset1 (m) signal, Trans1 (m) signal, Address1 (m) signal, and Hold1 (m) signal are output from the first row selection circuit 51 under the control of the first timing control circuit 41, and the mth row. Are commonly input to the first pixel portions Pm, n .
  • the Reset1 (m) signal and the Trans1 (m) signal are at a high level, the junction capacitance portion (charge storage portion) of the photodiode PD is discharged, and when the Hold1 (m) signal is also at a high level, the transistor T3 The potential of the gate terminal is reset. After that, when the Reset1 (m) signal, Trans1 (m) signal, and Hold1 (m) signal become low level, the charge generated in the photodiode is accumulated in the junction capacitor.
  • the Hold1 (m) signal is at a low level and the Address1 (m) signal is at a high level, a noise component is output from the first pixel unit Pm , n to the wiring Vline1 (n).
  • Each holding circuit 23 n includes two capacitive elements C 1 , C 2 and four switches SW 11 , SW 12 , SW 21 , SW 22 .
  • the switch SW 11 and the switch SW 12 is provided between the serially connected to the wiring Vline1 (n) and the wiring Hline_s1, one terminal of the capacitance C 1, the switch SW 11 and the switch is connected to the connection point between the SW 12, the other end of the capacitive element C 1 is grounded.
  • the switch SW 21 and the switch SW 22 is provided between the serially connected to the wiring Vline1 (n) and the wiring Hline_n1, one terminal of the capacitance C 2 is between the switch SW 21 and the switch SW 22 is connected to the connection point, the other end of the capacitive element C 2 is grounded.
  • the switch SW 11 opens and closes according to the level of the set_s1 signal supplied from the first column selection circuit 61.
  • the switch SW 21 opens and closes according to the level of the set_n1 signal supplied from the first column selection circuit 61.
  • the set_s1 signal and the set_n1 signal are input in common to the N holding circuits 23 1 to 23 N.
  • the switches SW 12 and SW 22 open and close according to the level of the hshift1 (n) signal supplied from the first column selection circuit 61.
  • the noise component output from the first pixel unit P m, n to the wiring Vline1 (n) when the set_n1 signal changes from the high level to the low level and the switch SW 21 is opened is thereafter It is held as a voltage value out_n1 (n) by the capacitance element C 2.
  • set_s1 signal is first pixel unit P m, the signal component being output from the n wiring Vline1 to (n) when the switch SW 11 is opened in turn from a high level to a low level, thereafter, the voltage by the capacitive element C 1 Stored as value out_s1 (n).
  • the switch SW 12 When hshift1 (n) signal becomes a high level, the switch SW 12 is closed, is output to the voltage value out_s1 (n) is the wiring Hline_s1 that has been held by the capacitor element C 1, The switch SW 22 is closed , voltage value out_n1 that has been held by the capacitor element C 2 (n) is output to the wiring Hline_n1.
  • the difference between the voltage value out_s1 (n) and the voltage value out_n1 (n) represents a voltage value corresponding to the amount of charge generated in the photodiode PD of the first pixel unit Pm , n .
  • FIG. 4 is a diagram illustrating a circuit configuration of the difference calculation circuit 25 included in the solid-state imaging device 1 according to the present embodiment.
  • the difference calculation circuit 25 includes amplifiers A 1 to A 3 , switches SW 1 and SW 2 , and resistors R 1 to R 4 .
  • Inverting input terminal of the amplifier A 3 is connected to the output terminal of the buffer amplifier A 1 via a resistor R 1, and is connected to its own output terminal via the resistor R 3.
  • the non-inverting input terminal of the amplifier A 3 is connected to the output terminal of the buffer amplifier A 2 via the resistor R 2, and is connected to the ground potential via the resistor R 4.
  • the output terminal of the amplifier A 3 is connected to the input terminal of the AD conversion circuit 27.
  • Input terminal of the buffer amplifier A 1 is connected to the N holding circuits 23 1 ⁇ 23 N via the wiring Hline_s1, it is connected to the ground potential via the switch SW 1.
  • the input terminal of the buffer amplifier A 2 is connected to the N holding circuits 23 1 to 23 N through the wiring Hline_n 1 and is connected to the ground potential through the switch SW 2 .
  • the switches SW 1 and SW 2 of the difference calculation circuit 25 are controlled by the hreset1 signal supplied from the first column selection circuit 61 to open and close.
  • the switch SW 1 When the switch SW 1 is closed, the voltage value input to the input terminal of the buffer amplifier A 1 is reset.
  • the switch SW 2 is closed, the voltage value input to the input terminal of the buffer amplifier A 2 is reset.
  • the switch SW 1, SW 2 When the switch SW 1, SW 2 is open, the wiring from one of the holding circuit 23 n of the N holding circuits 23 1 ⁇ 23 N Hline_s1, the voltage value outputted to the Hline_n1 out_s1 (n), out_n1 (n) is input to the input terminals of the buffer amplifiers A 1 and A 2 .
  • the voltage value output from the output terminal of the difference calculation circuit 25 is The difference between the voltage values input through the wiring Hline_s1 and the wiring Hline_n1 is represented, and the noise component is removed.
  • FIG. 5 is a diagram illustrating a circuit configuration of each of the second pixel unit Q i, j and the holding circuit 24 j included in the solid-state imaging device 1 according to the present embodiment.
  • the second pixel portion Q i, j is shown as a representative
  • the holding circuit 24 j is shown as a representative.
  • Each second pixel portion Q i, j has the same configuration as the first pixel portion P m, n and is of the APS system, and includes a photodiode PD and five MOS transistors T1 to T5.
  • the connection relationship between these elements in the second pixel portion Q i, j is the same as the connection relationship in the first pixel portion P m, n .
  • the source terminal of the transistor T4 is connected to the wiring Vline2 (j).
  • a constant current source is connected to the wiring Vline2 (j).
  • the amplifying transistor T3 outputs an electric signal having a value corresponding to the amount of charge input to the gate terminal.
  • the Reset2 (i) signal is input to the gate terminal of the reset transistor T1, the Trans2 (i) signal is input to the gate terminal of the transfer transistor T2, and the Address2 (i) signal is input to the gate of the output selection transistor T4.
  • the Hold2 (i) signal is input to the terminal of the transistor T5.
  • the Reset2 (i) signal, Trans2 (i) signal, Address2 (i) signal, and Hold2 (i) signal are output from the second row selection circuit 52 under the control of the second timing control circuit 42, and the i-th row. Are input in common to each of the second pixel portions Q i, j .
  • the operation of the second pixel unit Q i, j is the same as the operation of the first pixel unit P m, n .
  • Each holding circuit 24 j has the same configuration as the holding circuit 23 n and includes two capacitive elements C 1 and C 2 and four switches SW 11 , SW 12 , SW 21 , and SW 22 .
  • the connection relationship between these elements in the holding circuit 24 j is the same as the connection relationship in the holding circuit 23 n .
  • the switches SW 11 and SW 21 are connected to the wiring Vline2 (j).
  • Switch SW 12 is connected to the wiring Hline_s2.
  • the switch SW 22 is connected to the wiring Hline_n2.
  • the switch SW 11 opens and closes according to the level of the set_s2 signal supplied from the second column selection circuit 62.
  • the switch SW 21 opens and closes according to the level of the set_n2 signal supplied from the second column selection circuit 62.
  • the set_s2 signal and the set_n2 signal are input in common to the J holding circuits 24 1 to 24 J.
  • the switches SW 12 and SW 22 open and close according to the level of the hshift2 (j) signal supplied from the second column selection circuit 62.
  • the operation of the holding circuit 24 j is the same as the operation of the holding circuit 23 n .
  • hshift2 (j) signal becomes a high level
  • the switch SW 12 is closed, the voltage value out_s2 that has been held by the capacitor element C 1 (j) is output to the wiring Hline_s2,
  • the switch SW 22 is closed, capacitor voltage out_n2 which has been held by the element C 2 (j) is output to the wiring Hline_n2.
  • the difference between the voltage value out_s2 (j) and the voltage value out_n2 (j) represents a voltage value corresponding to the amount of charge generated in the photodiode PD of the second pixel unit Q i, j .
  • FIG. 6 is a diagram illustrating a circuit configuration of the difference calculation circuit 26 included in the solid-state imaging device 1 according to the present embodiment.
  • the difference calculation circuit 26 has the same configuration as the difference calculation circuit 25, and includes amplifiers A 1 to A 3 , switches SW 1 and SW 2 , and resistors R 1 to R 4 .
  • the connection relationship between these elements in the difference calculation circuit 26 is the same as the connection relationship in the difference calculation circuit 25.
  • Input terminal of the buffer amplifier A 1 is connected to the J hold circuits 24 1 ⁇ 24 J through the wire Hline_s2, is connected to the ground potential via the switch SW 1.
  • Input terminal of the buffer amplifier A 2 is connected to the J hold circuits 24 1 ⁇ 24 J through the wire Hline_n2, is connected to the ground potential via the switch SW 2.
  • the switches SW 1 and SW 2 of the difference calculation circuit 26 are controlled by the hreset2 signal supplied from the second column selection circuit 62 to open and close.
  • the switch SW 1 When the switch SW 1 is closed, the voltage value input to the input terminal of the buffer amplifier A 1 is reset.
  • the switch SW 2 is closed, the voltage value input to the input terminal of the buffer amplifier A 2 is reset.
  • the switch SW 1, SW 2 When the switch SW 1, SW 2 is open, the wiring from any holding circuit 24 j of the J holding circuits 24 1 ⁇ 24 J Hline_s2, the voltage value outputted to the Hline_n2 out_s2 (j), out_n2 (j) is input to the input terminals of the buffer amplifiers A 1 and A 2 .
  • the voltage value output from the output terminal of the difference calculation circuit 26 is The difference between the voltage values input through the wiring Hline_s2 and the wiring Hline_n2 is represented, and the noise component is removed.
  • FIG. 7 is a diagram illustrating a configuration example of the light receiving unit 10 of the solid-state imaging device 1 according to the present embodiment. This figure explains the positional relationship between the unit areas A i, j and the pixel areas am , n on the light receiving surface of the light receiving unit 10. This figure does not explain the shape of each unit area A i, j and each pixel area am , n .
  • the shape of each region is preferably common, but is not necessarily rectangular. First row, second row, third row,... From the bottom, first column, second column, third column,.
  • the light receiving surface of the light receiving unit 10 includes I ⁇ J unit regions A 1,1 to A I, J that are two-dimensionally arranged in I rows and J columns, and M ⁇ N that is two-dimensionally arranged in M rows and N columns. It consists of N pixel areas a 1,1 to a M, N.
  • each unit area A i, j is an area surrounded by a thick line
  • each pixel area am , n is an area surrounded by a thick line or a thin line.
  • the unit area A i, j is located in the i-th row and the j-th column
  • the pixel area am , n is located in the m-th row and the n-th column.
  • each unit region includes 8 ⁇ 8 pixel regions. That is, each unit area A i, j includes 8 ⁇ 8 pixel areas a 8i-7,8j-7 to a 8i, 8j .
  • Each pixel area am , n in each unit area A i, j is divided into either the first group or the second group.
  • pixel areas am , n included in the second group are indicated by hatching.
  • pixel region m is an odd number n is even a m, n is included in the second group.
  • Other pixel regions am , n are included in the first group.
  • the first pixel unit P m, n is configured to include photodiodes individually formed in the pixel regions a m, n included in the first group.
  • photodiodes formed in each pixel area a m, n (16 pixel areas in this example) included in the second group in the unit area A i, j are arranged in parallel. Connected to each other.
  • the second pixel portion Q i, j is configured. includes the case where these pixel areas a m, a photodiode which is formed separately n can be treated in parallel are connected to each other as a substantially single photodiode by a metal wire or the like, the pixel regions a m, The case where the photodiode formed in n is a part of one continuous photodiode and the case where both of these two cases are included are included.
  • the unit regions A i, j preferably have a common configuration.
  • Each first pixel portion P m, n preferably has a common configuration.
  • the second pixel portions Q i, j preferably have a common configuration.
  • FIGS. 8 to 10 are diagrams illustrating examples of the arrangement of the first pixel unit P m, n and the second pixel unit Q i, j in the light receiving unit 10.
  • each unit region A i, j includes 8 ⁇ 8 pixel regions a 8i-7,8j-7 to a 8i, 8j , and 2 ⁇ 2 units.
  • the range of the region is shown, and the arrangement of the photodiodes PD of the first pixel portion P m, n and the second pixel portion Q i, j in the range is shown.
  • Figure 8 is a diagram showing a first arrangement example of the first pixel portion P m in the photodetecting section 10 of embodiment included in the solid-state imaging device 1 according to the embodiment, n and the second pixel unit Q i, j.
  • the photodiodes of the second pixel portions Q i, j are each of the pixel areas a m, n (m is an odd number) included in the second group in the unit area A i, j .
  • n is an even number (hatched region in the figure)
  • photodiodes individually formed are connected to each other in parallel by the metal wiring L i, j to be substantially configured as one photodiode.
  • a first pixel portion P m, n including a photodiode formed individually is configured.
  • FIG. 9 is a diagram illustrating a second arrangement example of the first pixel unit P m, n and the second pixel unit Q i, j in the light receiving unit 10 included in the solid-state imaging device 1 according to the present embodiment.
  • the photodiodes of each second pixel portion Q i, j are connected to each pixel area a m, n (in the figure) included in the second group in the unit area A i, j .
  • the photodiodes individually formed in the hatching region) are connected to each other in parallel by the metal wiring L i, j so as to be substantially configured as one photodiode.
  • a first pixel portion Pm, n including photodiodes formed individually is configured in the pixel region am , n included in the other first group.
  • the second pixel unit Q i, the pixel regions included in the second group constituting the j a m, n is a two by two in each row is two by two in each row.
  • FIG. 10 is a diagram illustrating a third arrangement example of the first pixel unit P m, n and the second pixel unit Q i, j in the light receiving unit 10 included in the solid-state imaging device 1 according to the present embodiment.
  • the photodiodes of the second pixel portions Q i, j are each of the pixel areas a m, n (m is an odd number) included in the second group in the unit area A i, j .
  • n is an even number (hatched region in the figure)
  • photodiodes individually formed are connected to each other in parallel by the metal wiring L i, j to be substantially configured as one photodiode.
  • a first pixel portion P m, n including a photodiode formed individually is configured.
  • the first arrangement example shown in FIG. 8 is the same.
  • a color filter is attached to the photodiode PD in the pixel region a m, n (m is an even number or n is an odd number) included in the first group. More specifically, the photodiode PD in the pixel region a m, n (m is an even number and n is an odd number) is provided with a red filter whose center wavelength in the transmission band is in the red wavelength band. The photodiode PD in the pixel region a m, n (m is an even number and n is an even number) is provided with a green filter having a center wavelength of the transmission band in the green wavelength band.
  • the pixel area a m, n (m is an odd number and n odd) in the photodiode PD of the center wavelength of the transmission band is provided with a blue filter on the blue wavelength band. In this way, high-resolution color imaging can be performed using the first pixel portion P m, n configured in the pixel region am , n included in the first group.
  • the arrangement of the first pixel unit P m, n and the second pixel unit Q i, j in the light receiving unit 10 is not limited to these design examples.
  • the photodiodes of the respective second pixel portions Q i, j are configured by connecting photodiodes formed in the respective pixel regions am , n included in the second group in the unit region A i, j to each other in parallel. It only has to be done.
  • the solid-state imaging device 1 according to the present embodiment can perform high-resolution imaging at high speed using the first pixel unit P m, n , and low resolution using the second pixel unit Q i, j. Imaging can be performed at high speed.
  • each first pixel portion P m, n and each second pixel portion Q i, j is of the APS system, high-speed imaging can be performed with high sensitivity and low noise.
  • a first signal output circuit 21 that outputs a first electric signal for each first pixel portion P m, n and a second signal output circuit 22 that outputs a second electric signal for each second pixel portion Q i, j . Since the high-resolution imaging using the first pixel portion P m, n and the low-resolution imaging using the second pixel portion Q i, j can be performed in parallel, High-speed imaging is possible.
  • the first control circuit 31 controls the output of the first electric signal by the first signal output circuit 21 for each first pixel portion P m, n , and the second signal output circuit for each second pixel portion Q i, j .
  • a second control circuit 32 for controlling the output of the second electric signal by 22 separately, so that high-resolution imaging using the first pixel portion P m, n and the second pixel portion Q i, j are used. It becomes easy to perform the low-resolution imaging that has been performed independently of each other.
  • FIG. 11 and FIG. 12 are diagrams showing a layout example of the light receiving unit 10 included in the solid-state imaging device 1 according to the present embodiment.
  • the solid-state imaging device 1 according to this embodiment is preferably integrated on a semiconductor substrate, and in that case, for example, has a structure as shown in FIGS.
  • FIG. 11 is a diagram illustrating a layout example of the light receiving unit 10 included in the solid-state imaging device 1 according to the present embodiment.
  • 12 is a cross-sectional view taken along the line A-A ′ in the layout example shown in FIG. 11.
  • the diffusion layer 1 is a region of the photodiode PD of each first pixel portion P m, n and a region of the photodiode PD of each second pixel portion Q i, j .
  • the diffusion layer 2 is a source and drain region of the transistors T1 to T5 of each first pixel portion Pm, n and a source and drain region of the transistors T1 to T5 of each second pixel portion Q i, j .
  • the polysilicon is the gate of each of the transistors T1 to T5 of each first pixel portion Pm, n and each second pixel portion Qi , j .
  • the metal wiring is a wiring for connecting the reading wiring Vline1 (n) and the reading wiring Vline2 (j), and the transistor T3 and the transistor T5.
  • the upper layer metal is a wiring L i, j that interconnects a plurality of photosensitive regions in each second pixel portion Q i, j .
  • FIG. 11 illustration of other metal wirings is omitted. Further, in FIG. 12 showing an A-A ′ section in the layout example shown in FIG. 11, illustration of an insulating layer and the like is omitted.
  • the first signal output circuit 21 and the second signal output circuit 22 are provided separately, and the first column selection circuit 61 and the second column selection circuit 62 are provided separately.
  • the signal output unit 20 may be provided instead of the first signal output circuit 21 and the second signal output circuit 22, or the first column selection circuit 61 and the second column A column selection circuit 60 may be provided instead of the selection circuit 62.
  • FIG. 13 is a configuration diagram of a solid-state imaging device 2 according to another embodiment.
  • the solid-state imaging device 2 shown in this figure includes a light receiving unit 10, a signal output unit 20, and a control unit 30.
  • the light receiving unit 10 is the same as described above.
  • the signal output unit 20 has the same configuration as that of the first signal output circuit 21, but the operation differs depending on whether high-resolution imaging is performed or low-resolution imaging.
  • the control unit 30 includes a timing control circuit 40, a first row selection circuit 51, a second row selection circuit 52, and a column selection circuit 60.
  • the timing control circuit 40 controls operation timings of the signal output unit 20, the first row selection circuit 51, the second row selection circuit 52, and the column selection circuit 60.
  • the column selection circuit 60 When high-resolution imaging is performed using the first pixel unit P m, n , the column selection circuit 60 operates in the same manner as the first column selection circuit 61, and the signal output unit 20 is connected to the first signal output circuit 21. The same operation is performed. On the other hand, when low-resolution imaging is performed using the second pixel unit Q i, j , the signal output unit 20 outputs the second electric signal using J holding circuits among the N holding circuits. The column selection circuit 60 controls the signal output unit 20 to perform such an operation.
  • a third pixel unit R m, n including photodiodes individually formed in each pixel region am , n included in the second group in each unit region A i, j is configured. May be.
  • a part of the photodiode of the second pixel portion Q i, j is formed in each pixel region am , n included in the second group in each unit region A i, j , and the third region A photodiode of the pixel portion R m, n is formed.
  • a third electric signal having a value corresponding to the amount of charge generated in the photodiode of each third pixel portion R m, n is output by the signal output portion. Further, the output of the third electric signal by the signal output unit for each third pixel unit R m, n is controlled by the control unit.
  • the output of the third electric signal may be performed by a dedicated third signal output circuit provided separately from the first signal output circuit 21 and the second signal output circuit 22 shown in FIG. May be performed by the first signal output circuit 21 shown in FIG. 13 or may be performed by the signal output unit 20 shown in FIG.
  • the control of the output of the third electric signal may be performed by a dedicated third row selection circuit provided separately from the first row selection circuit 51 and the second row selection circuit 52 shown in FIG. Further, it may be performed by the first row selection circuit 51 shown in FIG.
  • each third pixel portion R m, n also has an amplifying MOS transistor that inputs charges generated by the photodiode to the gate terminal. In addition, it is preferable to output an electrical signal corresponding to the input charge amount from the amplification MOS transistor to the signal output unit.
  • FIG. 14 and FIG. 15 are diagrams showing an arrangement example corresponding to a modification of the third arrangement example shown in FIG. 10, and the first pixel unit P m, n and the second pixel unit in the light receiving unit 10.
  • FIG. 14 and FIG. 15 are diagrams showing an arrangement example corresponding to a modification of the third arrangement example shown in FIG. 10, and the first pixel unit P m, n and the second pixel unit in the light receiving unit 10.
  • An arrangement example in which a third pixel portion R m, n is provided in addition to Q i, j is shown.
  • only one basic region A 1,1 is shown, and the photodiodes of the first pixel portion P m, n , second pixel portion Q i, j and third pixel portion R m, n in that region are shown.
  • the arrangement of the PD is shown.
  • the MOS regions in which the transistors T1 to T5 of the first pixel portion P m, n , the second pixel portion Q i, j and the third pixel portion R m, n are formed are also schematically shown. Show.
  • FIG. 14 shows a fourth arrangement example of the first pixel unit P m, n , the second pixel unit Q i, j, and the third pixel unit R m, n in the light receiving unit 10 included in the solid-state imaging device of the modification.
  • FIG. FIG. 15 shows a fifth arrangement example of the first pixel unit P m, n , the second pixel unit Q i, j and the third pixel unit R m, n in the light receiving unit 10 included in the solid-state imaging device of the modification.
  • FIG. in any of the fourth arrangement example (Fig. 14) and the fifth arrangement example (Fig. 15) the first pixel unit P m, the arrangement and installation of the color filter of n is the same as the third arrangement example (Fig. 10) is there.
  • the photodiodes of the second pixel portion Q1,1 are individually arranged in 16 pixel regions am , n (m is an odd number and n is an even number) included in the second group.
  • the formed photodiodes are connected to each other in parallel by the metal wiring L i, j and are configured substantially as one photodiode.
  • 15 pixel regions excluding the pixel region a 1 , 8 in the lower right corner include a photodiode and transistors T1 to T5 that are individually formed.
  • R m, n is configured.
  • the pixel region a 1, 2 is partially in addition to the third pixel unit R 1, 2 constituting the photodiode of the second pixel portion Q 1, 1, the second pixel in the pixel area a l, 4
  • a third pixel part R 1, 4 is configured, and in the pixel region a 1 , 6 , in addition to a part of the photodiodes of the second pixel part Q 1 , 1
  • the third pixel portion R1,6 is configured.
  • the pixel region a 3 , 2 includes a third pixel portion R 3, 2
  • the pixel region a 3 , 4 includes the second pixel portion Q
  • third pixel portions R 3 and 4 are formed, and the pixel regions a 3 and 6 have a second pixel portion Q 1,1 in addition to a part of the photodiodes. It consists three pixel portion R 3, 6 is the third pixel unit R 3, 8 is formed in addition to a portion of the photodiode of the second pixel portion Q 1, 1 in the pixel region a 3, 8.
  • the pixel region a 5,2 is the third pixel unit R 5,2 in addition to a portion of the photodiode arrangement of the second pixel portion Q 1, 1, the second pixel in the pixel region a 5,4
  • third pixel parts R 5, 4 are configured, and in the pixel regions a 5 , 6 , in addition to a part of the photodiodes of the second pixel part Q 1 , 1
  • the third pixel portion R 5,6 is configured, and the pixel region a 5,8 includes the third pixel portion R 5,8 in addition to a part of the photodiode of the second pixel portion Q 1,1. .
  • the pixel region a 7,2 includes a third pixel portion R 7,2 in addition to a part of the photodiode of the second pixel portion Q 1,1 , and the pixel region a 7,4 includes the second pixel portion Q.
  • a third pixel part R 7,4 is formed, and in the pixel region a 7,6 a second part of the photodiode of the second pixel part Q 1,1 is added.
  • three pixel portion R 7, 6 is configured, the third pixel unit R 7, 8 in addition to a portion of the photodiode of the second pixel portion Q 1, 1 is constructed in the pixel region a 7, 8.
  • the photodiodes of the second pixel portion Q 1,1 are formed in 16 pixel regions a m, n (m is an odd number and n is an even number) included in the second group.
  • the photodiodes are continuous in the inter-column region, and are further connected to each other in parallel by the metal wiring L i, j, so that it is substantially configured as one photodiode.
  • 15 pixel regions excluding the pixel region a 1 , 8 in the lower right corner include a photodiode and transistors T1 to T5 that are individually formed.
  • R m, n is configured.
  • the third pixel portion R m, n is the same as the fourth arrangement example (FIG. 14).
  • the first pixel portion P m, n is included in all the pixel areas a m, n in each basic area A i, j .
  • Any MOS region (transistors T1 to T5) of n , second pixel portion Q i, j and third pixel portion R m, n is provided. Therefore, the MOS regions can be regularly arranged, and the uniformity of the sensitivity of the photodiode can be improved.
  • the first pixel unit P m, n, the second pixel unit Q i, j and the third pixel unit R m by adjusting the n area of the photosensitive region of each photodiode, the first pixel unit P m , n , the sensitivity of the second pixel part Q i, j and the third pixel part R m, n can be adjusted.
  • a plurality of photosensitive regions are connected to each other by wiring L i, j in each second pixel portion Q i, j , but each second pixel portion Q i , j also has one photodiode, the photo-sensitive region of the photo-diode (the region of the diffusion layer 1) is wide, so contact holes are provided at various locations in the photo-sensitive region in order to reduce the resistance. It is preferable to connect with metal wiring.
  • the solid-state imaging device according to the present invention is not limited to the above-described embodiments and configuration examples, and various modifications are possible.
  • the light receiving surface includes I ⁇ J unit areas A 1,1 to A I, J that are two-dimensionally arranged in I rows and J columns, and the light receiving surface.
  • a first pixel unit P m which is divided into any one of the second groups and includes photodiodes individually formed in each pixel region am , n included in the first group in each unit region A i, j .
  • n is configured, and photodiodes formed in each pixel region am , n included in the second group in each unit region A i, j are connected to each other in parallel to substantially form the second pixel portion Q i.
  • j is configured receiving portion, a first electrical signal having a value corresponding to the amount of charges generated in the (2) each of the first pixel unit P m, n photodiode output Rutotomoni, the second pixel unit Q i, a signal output section for outputting a second electrical signal having a value corresponding to the amount of charges generated in the photodiodes of j, (3) each first pixel unit P m, n And a control unit that controls the output of the first electric signal by the signal output unit and controls the output of the second electric signal by the signal output unit for each second pixel unit Q i, j . .
  • M and N are integers of 2 or more, I is an integer of 2 or more and less than M, J is an integer of 2 or more and less than N, m is an integer of 1 or more and M or less, and n is 1 These are integers of N or less, i is an integer of 1 or more and I or less, and j is an integer of 1 or more and J or less.
  • M ⁇ N pixels regions a 1,1 ⁇ a M, the rows and columns of the N, I ⁇ J number of unit regions A 1,1 ⁇ A I, the rows and columns of J is different To do.
  • contact holes are provided at various locations in the photosensitive regions of the photodiodes of the second pixel portions Q i, j and these are connected by metal wiring. In this case, even if the photosensitive region of the photodiode of each second pixel portion Q i, j is wide, the resistance can be reduced.
  • each first pixel portion P m, n and each second pixel portion Q i, j include an amplification MOS transistor that inputs charges generated by the photodiode to the gate terminal. It is preferable to output an electric signal corresponding to the input charge amount from the MOS transistor to the signal output unit. In this way, when each first pixel portion P m, n and each second pixel portion Q i, j are of the APS system, high-speed imaging can be performed with high sensitivity and low noise.
  • the signal output unit includes a first signal output circuit that outputs a first electric signal for each first pixel unit P m, n and a second electric signal for each second pixel unit Q i, j . It is preferable to separately have a second signal output circuit that outputs. In this case, since high-resolution imaging using the first pixel unit P m, n and low-resolution imaging using the second pixel unit Q i, j can be performed in parallel, higher-speed imaging is possible. It is.
  • the control unit controls the first control circuit that controls the output of the first electric signal by the signal output unit for each first pixel unit P m, n , and each second pixel unit Q i, j . It is preferable to separately have a second control circuit that controls the output of the second electric signal by the signal output unit. In this case, it becomes easy to perform high-resolution imaging using the first pixel portion P m, n and low-resolution imaging using the second pixel portion Q i, j independently of each other.
  • a color filter is provided in the photodiode of each first pixel unit Pm, n . In this case, high-resolution color imaging can be performed.
  • a third pixel unit R m, n including photodiodes individually formed in each pixel area am , n included in the second group in each unit area A i, j .
  • signal output section the third pixel unit R m, and outputs a third electrical signal having a value corresponding to the amount of charges generated in the n photodiode
  • control unit It is preferable to control the output of the third electric signal by the signal output unit for each third pixel unit R m, n .
  • each pixel area am , n included in the second group in each unit area A i, j is individually added to a part of the photodiode of the second pixel portion Q i, j.
  • a third pixel portion R m, n including the formed photodiode is configured. From the signal output unit, a third electric signal having a value corresponding to the amount of electric charge generated in the photodiode of each third pixel unit R m, n is output.
  • the control unit controls the output of the third electric signal by the signal output unit for each third pixel unit R m, n .
  • each first pixel portion P m, n , each second pixel portion Q i, j, and each third pixel portion R m, n has an amplifying MOS that inputs charges generated in the photodiode to the gate terminal. It is preferable that an electric signal corresponding to the input charge amount is output from the amplifying MOS transistor to the signal output unit.
  • each first pixel portion P m, n , each second pixel portion Q i, j and each third pixel portion R m, n are of the APS system, high sensitivity, low noise, and high speed Imaging can be performed.
  • the present invention can be used as a solid-state imaging device capable of performing high-resolution imaging and low-resolution imaging at high speed.
  • 1,2 ... solid-state imaging device 10 ... receiving unit, 20 ... signal output section, 21 ... first signal output circuit, 22 ... second signal output circuit, 23 n ... holding circuit, 24 j ... holding circuit, 25 and 26 ... difference calculation circuit, 27, 28 ... AD conversion circuit, 30 ... control unit, 31 ... first control circuit, 32 ... second control circuit, 40 ... timing control circuit, 41 ... first timing control circuit, 42 ... second Timing control circuit 51 ... first row selection circuit 52 ... second row selection circuit 60 ... column selection circuit 61 ... first column selection circuit 62 ... second column selection circuit A i, j unit region a m, n ... pixel region, P m, n ... first pixel unit, Q i, j ... second pixel unit, R m, n ... third pixel unit.

Abstract

L'invention concerne un dispositif (1) de prise d'images à semi-conducteur, qui comprend une unité photodétection (10), un premier circuit (21) de sortie de signal, un second circuit (22) de sortie de signal, un premier circuit de commande (31) et un second circuit de commande (32). La surface de photodétection de l'unité photodétection (10) comprend I × J régions unitaires A1,1-AI,J placées bidimensionnellement en I rangées et J colonnes, M × N régions de pixels a1,1-aM,N placées bidimensionnellement en M rangées et N colonnes, les régions de pixels am,n de chacune des régions unitaires ai,j étant classées dans un premier ou un deuxième groupe. Une première unité de pixels Pm,n constituée contient des photodiodes formées individuellement dans chaque région de pixels am,n contenue dans le premier groupe de chacune des régions unitaires AI,J. Une deuxième unité de pixels Qi,j est sensiblement constituée par la connexion en parallèle des photodiodes formées dans chacune des régions de pixels am,n contenue dans le deuxième groupe de chacune des régions unitaires Ai,j. On obtient de cette manière un dispositif de prise d'images à semi-conducteur pouvant mettre en œuvre rapidement une prise d'images à haute résolution et une prise d'images à basse résolution.
PCT/JP2009/060070 2008-06-06 2009-06-02 Dispositif de prise d'images à semi-conducteur WO2009148055A1 (fr)

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Publication number Priority date Publication date Assignee Title
JPH11243553A (ja) * 1997-12-26 1999-09-07 Canon Inc カラー撮像装置、画像信号読み出し方法、撮像素子、画像処理装置、画像処理システム、及び記憶媒体
JP2005039742A (ja) * 2003-07-18 2005-02-10 Matsushita Electric Ind Co Ltd 固体撮像装置
JP2007281995A (ja) * 2006-04-10 2007-10-25 Matsushita Electric Ind Co Ltd 固体撮像装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11243553A (ja) * 1997-12-26 1999-09-07 Canon Inc カラー撮像装置、画像信号読み出し方法、撮像素子、画像処理装置、画像処理システム、及び記憶媒体
JP2005039742A (ja) * 2003-07-18 2005-02-10 Matsushita Electric Ind Co Ltd 固体撮像装置
JP2007281995A (ja) * 2006-04-10 2007-10-25 Matsushita Electric Ind Co Ltd 固体撮像装置

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