WO2007053606A2 - Boitier de circuit integre constitue de puces multiples - Google Patents

Boitier de circuit integre constitue de puces multiples Download PDF

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Publication number
WO2007053606A2
WO2007053606A2 PCT/US2006/042450 US2006042450W WO2007053606A2 WO 2007053606 A2 WO2007053606 A2 WO 2007053606A2 US 2006042450 W US2006042450 W US 2006042450W WO 2007053606 A2 WO2007053606 A2 WO 2007053606A2
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
leadframe
package
leadframes
leads
Prior art date
Application number
PCT/US2006/042450
Other languages
English (en)
Other versions
WO2007053606A3 (fr
Inventor
Robert F. Wallace
Original Assignee
Sandisk Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/264,556 external-priority patent/US7352058B2/en
Priority claimed from US11/264,112 external-priority patent/US7511371B2/en
Application filed by Sandisk Corporation filed Critical Sandisk Corporation
Priority to EP06827158A priority Critical patent/EP1949440A2/fr
Priority to CN2006800450011A priority patent/CN101341593B/zh
Publication of WO2007053606A2 publication Critical patent/WO2007053606A2/fr
Publication of WO2007053606A3 publication Critical patent/WO2007053606A3/fr

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Definitions

  • the present invention and the various embodiments described generally relate to the fabrication of packaged semiconductor devices including more than one integrated circuit device, and more particularly to fabricating packages with multiple " integrated devices to form a packaged system, memory or memory card storage device.
  • semiconductor devices are provided in packages that protect and provide external connections to the integrated circuits.
  • the need for integration and advanced functionality of the devices has resulted in multiple integrated circuits, sometimes called chips or dies, being provided in a single package.
  • the package can be formed in various ways and of various materials, including molded packages formed from thermosetting or thermally- cured material, e.g., "glob top” or epoxy packages, pre-formed plastic or ceramic or metallic bodies and the like.
  • the materials used protect the small and brittle semiconductor integrated circuits, or "dies", from physical and some degree of moisture damage, and provide protections for the conductive leads or wires used to couple the external terminals, typically metallic or other conductive contacts, to the conductive bond pads on the integrated circuits, which are the external electrical connections of the integrated circuits.
  • leadframes are used in the semiconductor packaging art, to provide mechanical support and to make electrical connections between the integrated circuits and the exterior electrical contacts or leads of the packaged device.
  • Leadframes consist of conductive material, often copper or an alloy, or an iron nickel alloy such as Alloy 42, which are often coated to increase conductivity and solderability with materials such as gold, ruthenium, palladium, and the like, and additional coatings or alloys of nickel, copper, or other materials may be used to improve solderability and the manufacturability of connections. Plastic coatings over conductive material may be used to form a leadframe. Leads may be soldered or plated for soldering prior to assembly, or after assembly of the completed package. The leadframes are usually provided in an integrated strip form, and may be etched or stamped out, the leadframe strips are several leadframes connected in a strip form for ease of assembly and manufacture, and are then separated at a later stage of manufacture.
  • the leadframe typically provides a plurality of leads, often finger- shaped, although other shapes are used, which extend from outside an area that will be the exterior boundary of the desired finished package to an interior area arranged to receive an integrated circuit.
  • leads often finger- shaped, although other shapes are used, which extend from outside an area that will be the exterior boundary of the desired finished package to an interior area arranged to receive an integrated circuit.
  • a die pad for receiving the rectangular or square semiconductor die
  • the lead fingers extend on one or more sides of the die pad to an area proximate to the outside edges of the integrated circuit die.
  • the leadframe fingers are positioned extending away from the die and through the planned exterior boundary of the encapsulated package.
  • the lead fingers may extend over the die (lead on chip or "LOC” type leadframes) or under the die (lead under chip or “LUC” type leadframes) with the leads providing mechanical support, as well as electrical paths.
  • Insulator adhesive in the form of coatings or tapes can be used to secure the die to the leads, or to stabilize the leads by securing the leads together and maintaining their position during the assembly process.
  • the die may be adhered to a die pad using a die attach adhesive, which may be conductive or insulating material and may be a resin or thermosetting material.
  • bond wires are used. These miniature wires are applied to the semiconductor device by a wire bonding process; the wire is typically dispensed as it is applied through a capillary.
  • the wire bonding process uses heat and pressure and sometimes other energies, such as ultrasonic energy, to form a bond by attaching a wire to the integrated circuit bond pad, and then extends the bond wire above and away from the integrated circuit and to an area above the end of a lead finger of the leadframe, then the capillary again uses heat and pressure to form a second connection of the bond wire to the leadframe.
  • the bond wire could be formed in a vice versa direction, attaching first to the leadframe finger and extending up to and above the integrated circuit and attaching to a bond pad.
  • the cut wire is often heated to form a ball on the end of the bond wire, which is then used for the next bond to the integrated circuit die ("ball" bonding), the end of the bond wire which is attached to the lead frame without a ball may be called the "stitch".
  • multiple bond wires can extend from different pads of the integrated circuit to a single lead of the leadframe, for example, power or ground connections for the integrated circuit may be made in this manner.
  • the bond wire may be a gold or other known conductor material that is malleable and flexible enough to allow for this type of handling and which is useful for the ball and stitch bonding steps without unwanted breakage.
  • the wire bonding process may be highly automated, and is typically performed at a very high rate of speed.
  • the leadframe and die may be placed in molding equipment, for example in a transfer molding machine, where liquid or molten mold compound material is dispensed to encapsulate the leadframe and integrated circuit together, so as to provide mechanical protection and some degree of moisture resistance to the die as described above.
  • molding equipment for example in a transfer molding machine, where liquid or molten mold compound material is dispensed to encapsulate the leadframe and integrated circuit together, so as to provide mechanical protection and some degree of moisture resistance to the die as described above.
  • Other alternatives include using injection molding, epoxies and resins, such as "glob top" materials and other known materials for integrated circuit encapsulation may be used.
  • the leadframe and die assembly may instead be installed into a ceramic, metallic or plastic body which may then be subsequently sealed by encapsulant, using lids and adhesives, or otherwise.
  • the external ends of the leads of the leadframe may themselves form the external contacts of the packaged device, such as in a DIP, quad flat pack, SOP, or other leaded package, or additional connectivity technologies may be used, such as in a ball grid array ("BGA”) or pin grid array (“PGA”) package and the like.
  • Leadframes may be used in combination with other intercomiection interposer technologies, such as printed circuit boards, flexible circuits based on film based materials, commercially available films used in semiconductor manufacture, such as Kapton, Upilex, Mylar and the like, or ceramic substrate materials may be used.
  • intercomiection interposer technologies such as printed circuit boards, flexible circuits based on film based materials, commercially available films used in semiconductor manufacture, such as Kapton, Upilex, Mylar and the like, or ceramic substrate materials may be used.
  • multiple layer interposers are often used with metal layers formed coupling external connectors to the integrated circuits.
  • a terminal on the bottom surface may be coupled to the leadframe or wire bonding land terminals on the upper surface of the interposer through multiple layers and vias in the substrate or interposers.
  • These interposers or substrates are typically laminated structures with insulator layers formed over various conductive layers. Once the assembly is completed, these laminates may be overmolded to provide a hermetically sealed packaged device or the assembly may be placed in a body that is sealed.
  • MCM multiple chip module
  • a memory device and a controller may be packaged together to form such a module.
  • a processor and memory may form a module as well.
  • These devices may alternatively be identical devices, for example to form a large memory integrated circuit such as commodity DRAM or nonvolatile memory device, multiple identical dies may be placed in one package, with the common terminals of such devices coupled together in parallel to external contacts of the package.
  • Flex circuits may be formed, which have metallization patterns provided on one or both sides of a flexible substrate, these then act as interconnect levels for connecting the two integrated circuits together.
  • Laminates such as FR-4 or BT resin cards, can be formed with multiple metal layers and interlevel via technology, these laminate interposers again act as a miniature circuit board for connecting the integrated circuits together and provide traces for external connectivity, such as terminals.
  • die stacking may be used. Bond wires may be extended from the leads of a leadframe to several dies, for example the address leads of a DRAM package may be wired to several DRAM integrated circuits that are stacked. Stacking of dies may include spacers between the dies to enable the wire bonding equipment to access the die pads of the individual stacked integrated dies.
  • die stacking may be employed.
  • Various methods can be used such as providing multiple dies in a "face up" arrangement, and wire bonding may be formed to couple each die to a common leadframe using bond wires to couple them in parallel. It is known to place the dies in a back-to-back relation on leadframe, however, in order to maintain a common bond pad footprint, when a back-to-back relation is used, a "mirror die” is often required, so that the terminals on one side of the die facing upwards will be located in the same position and order as on the corresponding die facing downwards. The need for a "mirror die.” greatly increases the 2
  • an interposer or laminate circuit could be used to enable the back- to-back positioning of two identical functional die, this laminate interposer also adds cost and complexity to the finished device.
  • a particular packaged device type of increasing commercial importance in recent years is the removable non- volatile storage card, allowing transfer of data between a variety of electronic devices.
  • This nonvolatile memory or storage card is available in a variety of formats, including Compact FLASH, Secure Digital or SD, mini-SD, Memoiy Stick, USB drives, Multimedia Card or MMC, and other formats.
  • nonvolatile EEPROM or FLASH memory devices are provided along with an intelligent controller in a single packaged device.
  • the intelligent controller provides data error correction and detection, test, cache and redundancy support function so that even though some storage locations within the nonvolatile memory device are expected to fail and do fail during the useful life of the product, the user data is stored and retrieved correctly and the user or system is unaware that some locations within the memory array are no longer used; the intelligent controller replaces these locations with redundant memory locations and maintains a map of the available locations which is used to maintain the proper storage and consistency of the data.
  • the device looks like a large memory array, the controller and the automatic error correction features and redundancy support provide user transparent automatic memory control operations which does not affect the use of the device.
  • Figure 1 depicts the exterior surfaces of a typical removable storage card package.
  • This card may be of the type, for example, as described in U.S. Patent No. 6,410,355 to Wallace, the inventor of the present application, which is incorporated herein by reference.
  • a contact side of the card for example a secure digital or SD format card, is depicted with conductive terminals 101 arranged for contacting the integrated circuits within package 100.
  • Figure Ib depicts the opposing side of the package 100, which has no electrical contacts, but typically carries a label with information, brand name, size of media, and the like for the user's visual inspection and reference.
  • the number of terminals, and the type of connections used varies with the format, for example for secure digital or SD, the terminals shown in Figure Ia are typical, and only a few external terminals are used. " For compact flash or "CF" cards often used with digital cameras the number of terminals is greater, and the terminals are female receptacles located on one end of the side of the package.
  • the camera or card reader has a socket for receiving the same end of the CF package with male terminals or pins within the socket that enter the corresponding female receptacle when the compact flash card is inserted into the socket, thereby completing the connection.
  • Other connections may be used, for example a USB port may be used as the connection.
  • the prior art packages for removable storage card devices typically include a complex interposer or substrate in the form of a multiple layer laminate printed circuit board or "PC board," which provides physical support and device-to-device connectivity for the controller integrated circuit and the memory device or devices.
  • the board which may be of BT resin, FR4, or fiberglass or similar, usually is a laminate structure that incorporates metal layers which are patterned to form conductor traces, vias coupling the various layers for making electrical connections, and lands for wire bonds to couple traces on the surface of the board to integrated circuit dies or other components, packaged or bare die components, which are mounted to the board.
  • FIG. 2 depicts a typical arrangement in a cross sectional view.
  • a storage card 200 of the prior art is illustrated having integrated circuit dies 204 and 205 mounted on the same surface of laminated substrate 208.
  • Bond wires 203 connect bond pads 204 on the active surface, or face, of the integrated circuit dies to conductive areas, or lands 206 on the upper surface of the substrate.
  • encapsulant 211 which may be thermosetting or room temperature mold compounds or other encapsulating material.
  • shell 201 which may be plastic, covering the substrate and molded materials.
  • the integrated circuit dies and their respective leadframes are arranged in back-to-back relation and each die is coupled to the respective leadframe by the use of bond wires, or alternatively, the integrated circuits are arranged in a face-to-face relation on opposing sides of an interposer and coupled to their respective leadframe in a flip-chip arrangement, the two integrated circuits are independently coupled to external leads arranged on opposing sides of the packaged device and are not in electrical communication with each other.
  • 6,316,825 to Park et al. also incorporated herein by reference, provides a stacked package for stacking two identical integrated circuit devices, such as memory devices, in a molded package with two leadframes, which are physically coupled at the exterior of the package, such that each signal coupled to the external leads is physically and electrically coupled to each of the two identical memory devices, which are connected in parallel fashion.
  • Various preferred embodiments of the present invention provide a package for multiple semiconductor integrated circuits or dies, which connects two or more of the integrated circuits electrically, provides mechanical support for the integrated circuits, provides the facility to make arbitrary connections between the integrated circuits, and provides electrical connectivity to external connections of a packaged device.
  • the packages of the invention do not require an interposer or substrate of type used in the prior art, and the materials use conventional wire bonding and leadframe technologies compatible with existing equipment and automated factory machines known in the semiconductor processing industry; such that no retooling or specialized equipment are required to use and implement the invention.
  • a first leadframe is provided and positioned overlying a simple insulator layer.
  • the insulator layer has vias that are openings formed in certain locations and some leads of the leadframe overlie the vias.
  • Other leads of the leadframe may extend to the external boundary of the insulator or beyond the edge of the insulator. Some leads of the leadframe may not be extended to the external connectors.
  • a first integrated circuit die is provided and positioned in proximity to the interior ends of the leadframes, in some embodiments the leadframe may have an opening provided in the interior and the die may be placed in the interior opening. In other embodiments, the die may rest over the leads of the leadframe, or under the leads of the leadframe.
  • the die is wire bonded to the leadframe to electrically connect one or more of the leads of the integrated circuit to the leads of the leadframe.
  • the leads of the leadframe may be connected to the die using flip chip technology as is known in the art.
  • a second leadframe is then placed overlying the second and opposing surface of the insulator.
  • Certain leads of the second leadframe are positioned overlying the through-hole vias of the insulator as for, and in correspondence with, certain leads of the first leadframe.
  • Other leads of the second leadframe may extend to the exterior of the insulator layer for making external electrical connections to the completed device, and may extend beyond the exterior boundary of the insulator.
  • a second integrated circuit die is placed in proximity to the interior leads of the second leadframe.
  • the second leadframe may have a space in the central portion adjacent the interior ends of the leads of the leadframe for receiving the die, or a lead under chip or lead over chip leadframe arrangement may be used.
  • An electrical connection such as a bond wire connection or flip chip connection, is made from a die pad terminal on the second integrated circuit to at least one of the leads of the second leadframe.
  • a bond wire connection or flip chip connection is made from a die pad terminal on the second integrated circuit to at least one of the leads of the second leadframe.
  • the first and second leadframe may be attached to each other prior to either die being attached to its corresponding leadframe.
  • certain leads of the first and second leadframe are electrically coupled through the vias in the insulator.
  • This aspect of the invention makes it possible to electrically couple the first and second integrated circuit dies in an arbitrary location through the facility of making an electrical connection between the two leadframes through the insulator.
  • the connection may be made by physically deforming the leadframe leads of the first and second leads into the space within the via in the insulator, and then making a physical contact between the two leads within the via.
  • a conductive weld is then made between the two leadframes. The weld can be made, for example, with energy applied by heat, electrical energy, ultrasonic energy, laser energy, and the like.
  • the electrical connections may be made between the two leadframes by providing conductive materials positioned within the via, such as a conductive paste that acts as an electrical connection and which connection may be completed using thermal or electrical energy.
  • the insulator may be formed of an anisotropically conductive material that initially acts as an insulator in all directions, but becomes selectively conductive in a vertical direction when pressure or thermal energy or both is applied in an area, while remaining an insulator in the planar directions.
  • a via is a region in which electrical conductivity is achieved between a conductor adjacent to the top surface of the insulator and a conductor adjacent to the bottom surface of the insulator.
  • the integrated circuit dies may be positioned overlying opposing surfaces of the insulator, such that the integrated circuit dies may be in back-to- back relation. Unlike the back-to-back arrangements of the prior art, no mirror die is required when using the invention, because the method of forming electrical connections through the insulator provided by the invention, allows the arbitrary connections of the terminals of the two devices. It is not required that the terminals of the two integrated circuit dies be aligned or mirrored, as for some of the prior art packages.
  • the integrated circuit dies may, in some embodiments, be identical as for DRAM, EEPROM, FLASH or other dynamic or nonvolatile memory devices, where a larger packaged device may be created by coupling multiple identical integrated circuit dies together.
  • the dies may have different functions such as a memory controller and a memory device, an analog circuit and a digital device, a sensor and a controller device, and the like, to provide for integrated functions in the completed packaged device.
  • the invention may provide an insulator with vias formed in selected locations, a first leadframe overlying one surface of the insulator layer, a second leadframe overlying the opposing insulator layer, a first integrated circuit coupled to the first leadframe using known flip chip technology, where the integrated circuit bond pads are positioned in physical proximity to the desired leads and balls or pads of solder are formed, which are then reflowed using energy to form a mechanical and electrical connection between the die pads and the interior of the leads; the second integrated circuit may likewise be coupled to the second leadframe using flip chip technology, as before the completed device has electrical connections made between the first and second integrated circuits through the vias in the insulator. Since the first and second dies in this preferred embodiment are both coupled to the leadframe using flip chip technology, the integrated circuit devices may be arranged in face-to-face relation.
  • a removable storage card is formed using the packaging apparatus and methods of the invention; an insulator layer is provided with vias formed in selected locations, a first leadframe is positioned overlying the insulator and having some leads overlying the vias in the insulator, a first integrated circuit, which is a nonvolatile memory device, is positioned in proximity to the first leadframe and at least one electrical connection is made between the nonvolatile integrated circuit and the leadframe, a second integrated circuit is provided in proximity to a second leadframe, which is positioned overlying the opposing surface of the insulator and having some leads, which overlie the vias in the insulator, the second integrated circuit being a controller circuit for operating the nonvolatile memory device, the second integrated circuit is electrically connected to the second leadframe.
  • Electrical connections are made between the memory controller circuit and the nonvolatile memory, by forming electrical connections between the first and second leadframes through the vias in the insulator using the methods of the present invention.
  • the storage card may be completed by overmolding or encapsulating the insulator, the first and second integrated circuit, and portions of the first and second leadframe, the remaining exterior portions of which are used to form the external connections for the completed storage card.
  • the insulator used in the preferred embodiments of the present invention may comprise a variety of known materials. Because no electrical connections, complex multilayer routing, or metallization patterns are required within or on the insulator, the insulator may be formed of any material which electrically insulates the first and second leadframe one from another and which also may have through-hole vias formed within it. Plastic, glass, ceramic, fiberglass, resin, PC board, tapes, films, papers and other insulators may be used. Chemical etching, photolithography, laser drilling, or mechanical drilling processes may form the vias. Plastic or resin molding may be used to form an insulator with vias formed in it. The insulator can be formed in a wide variety of thicknesses and may be rigid or flexible material as desired.
  • the insulator may be overmolded to complete the packaged device, alternatively the insulator, integrated circuit and leadframe assembly may be positioned in the cavity of a shell or within a preformed body structure, which is subsequently sealed with adhesives or sealants using lids or layers.
  • an integrated system may be provided in a single package by incorporating multiple integrated circuit dies on either side of an insulator, the multiple dies being wire bonded to leadframes, which are coupled through vias in the insulator to make arbitrary connections between- the integrated circuits, wherein the packaged assembly for the system includes passive elements, such as resistors, capacitors, or inductors. The entire assembly can then be overmolded into a completed packaged system being provided using the methods of the invention.
  • Advantages of embodiments of the present invention include providing apparatus and methods of forming multiple integrated circuit modules including multiple integrated circuit devices which are electrically coupled to each other without the need for the complex interposers, flex circuits, laminate substrates or patterned printed circuit boards of the prior art, using conventional wire bonding or flip chip technologies and package molding methods, which are compatible with existing tooling, and using materials compatible with the existing automated semiconductor packaging infrastructure.
  • Figure 1 depicts in a top view in Figure Ia and in a bottom view in Figure Ib a prior art removable storage card package
  • Figure 2 depicts a cross-sectional view of a prior art removable storage card such, as is illustrated in Figure 1, including a memory device and a controller device;
  • Figure 3 depicts a top view of an insulator layer with through-hole vias which may be incorporated into a preferred embodiment of the present invention
  • Figure 4 depicts a cross-sectional view of the insulator layer of Figure 3;
  • Figure 5 depicts a top view of an insulator layer such as in Figures 3, 4 and having a leadframe and an integrated circuit positioned on the insulator;
  • Figure 6 depicts in a cross-sectional view the device of Figure 5, following additional processing steps
  • Figures 7a, 7b depict in a cross-section additional preferred embodiments of the insulator layer of the present invention.
  • Figure 8 depicts a cross-sectional view of a completed packaged device, which is a preferred embodiment of the invention.
  • Figure 9 depicts a cross-sectional view of another completed packaged device, which is another preferred embodiment of the invention.
  • Figure 10 depicts a top view of the device of Figure 9, and [0046] Figure 11 depicts a cross-sectional view of another completed packaged device, which is another preferred embodiment of the invention.
  • Figure 3 depicts a top view of an insulator layer 300 for use in a preferred embodiment of the present invention.
  • the insulator layer 300 may comprise any of many insulating materials, which are compatible with semiconductor processing steps, such as Mylar, Upilex, Kapton, and other films, insulating papers, resins, polyimide, glass, fiberglass, and the like, which are known in the art.
  • Layer 300 is electrically insulating and preferably has physical characteristics compatible with certain thermal processes, such as transfer molding.
  • Through-hole vias 301 in the insulating layer are formed at predetermined locations as detailed below, and provide a through-hole formed in the insulating layer 300.
  • the through-hole vias can be of any size but in a preferred embodiment are around 3-10 mils in diameter and preferably about 5 mils in diameter.
  • the vias are open through-holes, in other embodiments described below the vias may be filled with conductive pastes, or adhesives.
  • Figure 4 depicts the insulating layer of Figure 3 in a cross-sectional view.
  • the through-hole vias 301 are shown extending through the insulating layer 300.
  • the through-hole vias 301 may be formed by, for example, laser drilling, mechanical drilling, etching, punching or using other means to form holes in materials, such as molding.
  • Photolithography may be used to pattern an etch resistant layer over the surface with positive or negative resists used to define the locations and dimensions of the holes, selective etch may be applied to remove the material, and then the pattern layers may be stripped away, as is known in the art.
  • Figure 5 depicts a top view of a preferred embodiment of the invention, after a number of assembly steps have been completed.
  • the insulator layer 300 has been provided with through-hole vias 301 formed in selected locations.
  • a leadframe is provided with leads 502 and includes certain leads that overlie through-hole via locations 301.
  • Integrated circuit die 303 is positioned in proximity to the interior ends of leads 502. Bond wires 505 are formed and electrically couple the bond pads 507 to the leads 502.
  • a symmetrical operation is performed to locate a second leadframe and a second integrated circuit die on the opposite surface of insulator layer 300, with some leads of the second leadframe located under the through-hole vias 301.
  • Figure 6 depicts a cross-sectional view of a preferred embodiment of the invention at an intermediate stage of assembly.
  • integrated circuit die 303 is shown positioned over a first surface of insulator layer 300.
  • Leadframe lead 502 is shown in cross-section, and bond wires 505 are shown connecting bond pads of the integrated circuit die to leadframe leads 502.
  • Through-hole vias 301 are shown formed in insulator layer 300 at selected locations.
  • Leadframe 601 is shown positioned beneath insulator layer 300 and extending beneath the through-hole vias 301.
  • Integrated circuit die 604 is coupled from the bond pads 603 to leadframe 601 leads using bond wires 605.
  • the leadframe leads may be coupled together to form a physical and electrical connection through the insulator within the through-hole via locations 301.
  • a welding tool 607 is used to press and deform the leads 502 and 602 together in a through-hole via 301, and energy is applied to cause the two leads to become welded together.
  • Ultrasonic, electrical and/or thermal energies may be used to form the weld, methods contemplated include using electrical resistance welding, capacitive discharge, or laser welding.
  • the leadframe leads may be coated with material before assembly to help form the weld, by spot plating or other methods. This coupling operation is performed in each through-hole via location 301.
  • electrical connections can be made at any desired location between the two integrated circuits as shown in Figures 5 and 6.
  • a tool such as 607 in Figure 6 is used to form the weld between the upper and lower leadframe leads and to simultaneously form the through-hole via 301 in the insulator layer 300, that is, the insulator has no holes formed in it initially, the leadframes are positioned on either side opposing one another, and at locations where it is desired to couple the leads from the upper and lower leadframe together.
  • welding tool 607 is used to apply energy, such as heat, to the leads at a location where a connection is desired, the insulator material melts or vaporizes in response to the energy and a through-hole via 301 is formed as the insulator material is removed, the leads are physically deformed into the through-hole via 301 and are then welded together in a single continuous operation.
  • energy such as heat
  • Figures 7a and 7b depict alternative methods for connecting the upper and lower leadframe leads at through-hole via locations 301 in the insulator layer 300.
  • a portion of an insulator layer 300 for use in a package of the invention is depicted with a through-hole via 301 filled with a conductive material 705.
  • Conductive material such as a conductive paste, is deposited in the through-hole vias 301 and is subsequently positioned between the leadframe leads as the assembly process continues. The conductive material completes the electrical connection between two integrated circuit devices as in Figure 6.
  • the conductive material may be a conductive paste screened into the vias as is known in the art, or a conductive ink, for example, a conductive ink material is available under the trade name Parmod VLT from Parelec of Rocky Hill, New Jersey; and this material may be applied by screen printing, laser mill and filling, or ink jet printing processes. Heat or other energy may be applied to complete the conductive path and to physically bond the leads to the conductive material.
  • Figure 7b depicts the use of an anisotropically conductive material as the insulator layer 300.
  • This material is initially insulating in the planar horizontal and in the vertical directions.
  • the material includes conductive filaments which, when subjected to pressure and/or heat or other energy, become conductive in a vertical direction in a selective region.
  • a conductive path is formed at a location which lies between two leadframe leads, one for an upper leadframe and one from a lower leadframe, this conductive path is used in place of the through-hole vias 301 of Figures 5 and 6 to connect the leadframe leads at arbitrarily selected locations.
  • 3M Corporation of St.
  • 3M Tape 9703 is an example product which may be used.
  • Anisotropic films and conductive pastes for use in embodiments such as Figure 7b (film) or Figure 7a (paste) are also available from other commercial vendors, such as Henkel Technologies, of D ⁇ sseldorf, Germany. These materials may be used with other films or alone to provide the insulator layer 300.
  • Figure 8 depicts an alternative preferred embodiment using flip chip technology to couple the integrated circuit dies to the leadframes.
  • a package 801 is formed with encapsulant 803 overlying either side of insulator layer 300 and protecting the devices and leadframes within.
  • Through-hole vias 301 are formed in insulator layer 300 and couple the leads 502 from the upper and lower leadframes as described above.
  • Integrated circuit die 303 which may be a memory controller device, is flip-chip bonded to the upper leadframe by first performing a well known die or wafer bumping process which forms solder bumps, balls or columns on the die pads of the integrated circuit, the solder bumped die is then aligned with the interior ends of the leadframe leads and positioned "face down" to couple the die pads to the leadframe leads, thermal energy is used to reflow the solder and complete the connection to the leadframe.
  • integrated circuit 809 which may be for example a nonvolatile memory, such as a FLASH memory device, is also flip-chip mounted to the lower leadframe, and welds, such as 807, are formed to couple the upper and lower leadframes together in the through-hole vias 301.
  • Figure 8 also depicts the ability of the invention to make arbitrarily located connections between two or more integrated circuits within the package, the dies need not be identical or even nearly the same size.
  • Figure 9 depicts a completed package 901 using an alternative preferred embodiment of wire bonding connections using a lead under chip or "LUC" leadframe for the upper and lower leadframes. Also in Figure 9, the leads extend through the encapsulant boundary and provide for external connections to the package.
  • Package 901 is depicted in cross-section with encapsulant 903 provided on either side of insulator layer 300 as before, again the encapsulant protects the integrated circuit dies, leadframes and bond wires from damage and moisture.
  • the integrated circuit die 303 is provided overlying the leads 502 of the upper leadframe and may be advantageously mounted to the leadframe using a tape or epoxy die attach 609.
  • Bond pads 605 of the upper and lower integrated circuits are wire bond connected to leadframe leads 502 using wire bonding as before, bond wires 505 extend and couple to the leadframe leads.
  • Weld 807 is shown in a through-hole via 301 coupling the upper and lower leadframe leads.
  • Leads 502 extend through the encapsulant boundary to forai external terminals and to enable external connections to the package 901, for example, by use of a socket device. In this embodiment, leads from the upper leadframe emerge on one side of the package and leads from the lower leadframe emerge on another side of the package.
  • Figure 10 depicts the package 901 of Figure 9 in a top view.
  • Insulator layer 300 is shown with encapsulant 903 formed on it.
  • Leads 502 are shown overlying insulator layer 300 and extending through the boundary of the encapsulated region 902.
  • Welds 807 are shown lying in vias formed underneath certain leads 502.
  • Integrated circuit die 303 is positioned over the leads 502, so that the leadframe is a LUC or lead under chip arrangement, the die may be attached by tape or epoxy to provide support. Bond pads on the integrated circuit are coupled to the leadframe leads 520 by bond wires 505. Not visible in this view is the second integrated circuit and leadframe assembly lying underneath the insulator layer 300 and coupled to the upper leadframe by welds 807.
  • Figure 11 shows another preferred embodiment, in which some of the leads 502 are formed downward on one side of the package and the encapsulant 903 surrounds the entire assembly, but allows a region on the bottom surface 101 of selected leads 502 to be exposed for external electrical connection.
  • These external connection regions may be positioned as shown in Figure 1, or in other similar patterns that will be apparent to those knowledgeable in the art.
  • the methods for practicing the invention may be varied and these variations are contemplated as within the scope of the invention and the appended claims.
  • the leadframes and insulator layer 300 may be assembled together as a pre-formed assembly and the integrated circuit dies positioned adjacent the corresponding leadframe, wire bonding or flip-chip coupling is used to complete the connection to the dies, and then overmolding or glop top encapsulation can be performed.
  • the leadframes may be provided in strip form, the integrated circuit dies may be positioned and wire bonding or flip-chip processing is performed to couple the integrated circuits to the leadframes with or without adhesives or tapes; the leadframe assemblies are then positioned over the respective opposing surfaces of the insulator layer 300, the through-hole vias 301 already provided by patterning the insulator layer 300 ahead of time, and then the leadframes are coupled together by welding, use of conductive pastes or solders, or anisotropic conductor connection as described above. Finally, the completed assembly may be overmolded or glob top encapsulated, completing the package.
  • the insulator layer 300 as described above, may in another alternative method be provided without through-hole vias 301 formed within it, and the tooling may be used to weld and simultaneously form the through-hole vias 301 in the insulator layer 300.

Abstract

La présente invention concerne un boîtier de puces multiples destiné à des circuits intégrés. Une couche d'isolation est prévue et un ou plusieurs orifices sont formés dedans. L'isolant peut être muni d'orifices et d'autres orifices être formés par la suite. Au moins un circuit intégré est prévu et électriquement raccordé à au moins un fil d'un premier cadre de montage recouvrant une surface de la couche isolante. Au moins un second circuit intégré est prévu et électriquement couplé à un second cadre de montage recouvrant une seconde surface de la couche isolante. Des connexions électriques entre les deux cadres de montage et les premier et second circuits intégrés sont réalisées via l'isolant, à des endroits choisis, en couplant au moins un fil du premier et du second cadre de montage l'un à l'autre. Les fils du premier et du second cadre de montage peuvent être physiquement couplés par un procédé de soudure dans les orifices de l'isolant. L'invention concerne également un boîtier de carte de stockage amovible.
PCT/US2006/042450 2005-11-01 2006-10-30 Boitier de circuit integre constitue de puces multiples WO2007053606A2 (fr)

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EP06827158A EP1949440A2 (fr) 2005-11-01 2006-10-30 Boitier de circuit integre constitue de puces multiples
CN2006800450011A CN101341593B (zh) 2005-11-01 2006-10-30 多晶片集成电路封装及形成其的方法

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US11/264,556 US7352058B2 (en) 2005-11-01 2005-11-01 Methods for a multiple die integrated circuit package
US11/264,112 US7511371B2 (en) 2005-11-01 2005-11-01 Multiple die integrated circuit package
US11/264,112 2005-11-01

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KR100996982B1 (ko) 2010-11-26
TW200746381A (en) 2007-12-16
WO2007053606A3 (fr) 2007-09-07
TW201003888A (en) 2010-01-16
TWI324385B (en) 2010-05-01
TWI475662B (zh) 2015-03-01
EP1949440A2 (fr) 2008-07-30

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