WO2007012992A1 - A package and manufacturing method for a microelectronic component - Google Patents
A package and manufacturing method for a microelectronic component Download PDFInfo
- Publication number
- WO2007012992A1 WO2007012992A1 PCT/IB2006/052385 IB2006052385W WO2007012992A1 WO 2007012992 A1 WO2007012992 A1 WO 2007012992A1 IB 2006052385 W IB2006052385 W IB 2006052385W WO 2007012992 A1 WO2007012992 A1 WO 2007012992A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- microelectronic component
- package
- encapsulation material
- dam
- carrier element
- Prior art date
Links
- 238000004377 microelectronic Methods 0.000 title claims abstract description 79
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000000463 material Substances 0.000 claims abstract description 67
- 238000005538 encapsulation Methods 0.000 claims abstract description 48
- 230000007704 transition Effects 0.000 claims abstract description 25
- 239000004020 conductor Substances 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims description 9
- 239000012530 fluid Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 52
- 239000004593 Epoxy Substances 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 8
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 230000003287 optical effect Effects 0.000 description 5
- 238000012545 processing Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 241001025261 Neoraja caerulea Species 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000012780 transparent material Substances 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000000518 rheometry Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00333—Aspects relating to packaging of MEMS devices, not covered by groups B81C1/00269 - B81C1/00325
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
- G01N27/02—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance
- G01N27/04—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance
- G01N27/12—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of a solid body in dependence upon absorption of a fluid; of a solid body in dependence upon reaction with a fluid, for detecting components in the fluid
- G01N27/128—Microapparatus
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
- G01P1/00—Details of instruments
- G01P1/02—Housings
- G01P1/023—Housings for acceleration measuring devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14618—Containers
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/52—Encapsulations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/52—Encapsulations
- H01L33/54—Encapsulations having a particular shape
Definitions
- the present invention relates to a package for an microelectronic component, comprising a carrier element having conductor lines, a microelectronic component mounted on the carrier element and connected to the conductor lines via bonding wires, and an encapsulation material encapsulating the wire bonds and exposing a central zone of a top surface of the microelectronic component.
- FIG. 1 shows a schematic cross-section of a package for a microelectronic component.
- the package 10 comprises a carrier element 12 having a first side 16 that comprises conductor lines 14.
- a microelectronic component 20 is mounted on a diepad 18 of the substrate through an adhesive 22, which usually is an electrically and/or thermally conductive adhesive.
- the diepad which preferably comprises a gold top layer, can act as heat sink and grounding area.
- the microelectronic component 20 has a first surface 24 and a second surface 23 facing away from the first surface. It is connected to the first side 16 of the carrier element 12 with its second surface 23.
- the microelectronic component 20 comprises contact terminals 26 or bond pads that are schematically indicated in the drawings.
- the contact terminals 26 are connected to respective conductor lines 14 via respective wire bonds 28, for instance thin gold wires, having one end attached to a conductor line 14 and having the other end attached to the microelectronic component 20.
- the conductor lines provide input and/or output terminals for the complete package that functions as a microelectronic device, to receive or provide input signals or output signals. Since the methods for attaching such bonds are known per se, it is not necessary here to explain such methods in greater detail.
- connection areas 34 are used to connect the microelectronic device to the outside world.
- the areas 34 can be soldered or connected otherwise with connectors or terminals of other electronic devices or components. Such connections are also commonly known and do not need further explanation here.
- the assembly of carrier element 12, microelectronic component 20 and bonding wires 28 is partially encapsulated by an encapsulation material 30.
- This encapsulation material typically comprises a polymeric material that is injected on the respective area by some sort of injection device. Usually an epoxy-based material is used that cures after injecting it and forms a closed loop of epoxy material around the microelectronic component.
- the injection device is positioned just above the first side and first surface respectively and moves in the desired pattern while dispensing the epoxy material, the epoxy material after hardening resulting in the loop mentioned.
- the encapsulation material 30 is sometimes referred to as top glob material or glob top ring. After curing the encapsulation material 30 determines an outer edge 36 at the first side 16 and an inner edge 38 at the first surface 24 respectively.
- the inner edge 38 determines a central zone 40 of the microelectronic component that is exposed.
- Many different types of microelectronic devices require an opening in the encapsulating plastic package that exposes a sensitive or active area to the surrounding environment.
- MEMS micro-electromechanical systems
- micro-sensors that have chemically sensitive, pressure-sensitive, or temperature sensitive areas must be exposed to the environment through an area on the surface of the sensor that is freely exposed.
- optically active microelectronic devices require optical access through an opening or an exposed zone in the plastic package.
- optically active devices are charged coupled devices (CCD), photocells, photodiodes, and vertical cavity surface emitting lasers (VCSEL's). While some of these devices emit light while others receive light; both are considered to be Optically active'. All devices have in common that they comprise sensor elements on a surface that must be freely exposed to the environment to provide or receive their respective input or output signals from the outside world. The functioning of these types of microelectronic devices is known per se and therefore not discussed here in greater detail. A problem of this microelectronic device as shown in Fig. 1 is that the total surface area of the central zone 40 is difficult to control. When the encapsulation material is injected it will flow in the direction indicated by arrows A, B and C in Fig. 1.
- the final shape of the encapsulation material is at least dependent on the parameters of the injection process, the material properties of the injected material, especially its rheo logy properties, the exact geometry of the package prior to injection, and the curing parameters. Regarding the many influencing factors it is very difficult to obtain high process reliability with respect to the total surface area of the central zone when injecting the encapsulation material. This can result in a reduced operating window for the sensor elements on the microelectronic component that must be freely exposed and thus correspondingly in high yield losses. When the central zone is restricted too much, the microelectronic component cannot function properly. Thus there is a need to influence or control the final shape of the encapsulation material, in particular with respect to the forming of the inner edge thereof.
- US patent 6,674,159 offers a solution for the problem mentioned in the previous paragraph by disclosing a package similar to the package from Fig. 1.
- This package is shown in Fig. 2; a package 50 comprises a dam 42 that is placed or otherwise fabricated on top of the first surface 24 of the microelectronic component 20.
- a package 50 comprises a dam 42 that is placed or otherwise fabricated on top of the first surface 24 of the microelectronic component 20.
- the actual microelectronic device disclosed in US 6,674,159 has a somewhat different design with respect to the construction of the connection of the microelectronic component on the carrier element and for example has no diepad but a window of optical transparent material instead. However this difference is not relevant with respect to the present invention.
- the package US 6,674,159 also has a microelectronic component with a central zone on a top surface that should be exposed with respect to incoming and outgoing signals from the outside world and that the component is mounted on a substrate or carrier element, both components being connected by bonding wires.
- a polymeric encapsulation material 30 is poured or otherwise dispensed into the region outside of dam 42 around the bonding wires 28 to encapsulate and protect them.
- the dam 42 encircles the central zone 40 and prevents encapsulation material 30 from flowing into the central zone 40.
- this surface comprises sensitive microelectronics that can be easily damaged when mounting the dam on the microelectronic component.
- mounting the dam to the surface of the microelectronic component for example by an adhesive layer might results in contamination of the bondpads that are located nearby.
- the present invention provides a package for a microelectronic component, comprising; a carrier element having a first side that comprises conductor lines; a microelectronic component having a first surface and a second surface facing away from the first surface; the microelectronic component with said second surface mounted on said first side and connected to the conductor lines via bonding wires; a polymeric encapsulation material encapsulating the bonding wires and exposing a central zone of said first surface, the encapsulation material comprising an outer edge at said first side and an inner edge at said first surface; - a dam abutting to the encapsulation material; wherein the dam comprises a step-shaped surface transition at said first side, the surface transition abutting on said outer edge.
- the present invention is based on the insight that having such a surface transition at the first side not only influences the creation of the outer edge of the encapsulation material but also its inner edge.
- a dam not only restricts the outward flow of the encapsulation material as indicated with direction B in Fig. 1 but surprisingly also restricts the inward flow indicated by direction C and with that enlarges the central zone.
- the dam influences the forming of the outer and the inner edge during manufacturing the encapsulation material. This allows an improved control of the total area of the central zone and ensures that this surface area is kept above a critical level. Therefore an improved process capability during injecting the encapsulation material is obtained.
- an outside layer is provided at the first side, said layer protecting parts of the conductor lines, wherein said surface transition is arranged between said outside layer on the one hand and said conductor lines and a lower layer at said first side on the other.
- the outside layer is a solder resist layer.
- the solder resist layer is specifically designed to both protect the conductive surface tracks and prevent solder bridges during soldering.
- Such layers are frequently applied on a carrier element before mounting the microelectronic component. Since normally some kind of surface transition between this outside layer and a first layer under it or the conductor lines already exists, the outside layer can advantageously be used to create the dam. In this case one should make sure that an edge of the outside layer creating the surface transition is placed correctly and it has sufficient thickness.
- the dam comprises a top layer disposed at said first side adjacent to said outer edge. It is preferred in particular that this top layer forms a strip with a rectangular shape. This allows applying existing carrier elements, which only need an additional top layer to make them suited for a package according to the invention. By applying the layer in the form of a rectangular strip it is ensured that a minimum amount of additional material is needed and that the encapsulation material adopts a preferred shape.
- the height of the dam is less than a tenth of the height of the encapsulation material. It has been found that only a little material creating a step-shaped surface transition at the first side satisfies to obtain the object of the present invention.
- the present invention also relates to a carrier element to be used in a package for a microelectronic component according to any of the inventive embodiments mentioned before.
- the present invention also relates to a microelectronic device comprising a package for a microelectronic component according to any of the inventive embodiments mentioned before.
- the present invention furthermore also relates to method of manufacturing a package for a microelectronic component, the method comprising; providing a carrier element having conductor lines at a first side; providing a dam comprising a step-shaped surface transition at the first side; mounting a microelectronic component having a first surface and a second surface facing away from the first surface, the second surface of the microelectronic component connecting to the first side of the carrier element; wirebonding the microelectronic component to the conductor lines; dispensing a fluid polymeric encapsulation material to the assembly of the carrier element and the microelectronic component to encapsulate the wire bonds while exposing a central zone of the first surface, the encapsulation material with an outer edge abutting on the surface transition; curing the encapsulation material in a furnace.
- the step of providing a dam at the first side comprises applying a top layer on the first side in the shape of a rectangular strip.
- US patents nos. 6,861,683 and 6,303,978 show a package for a microelectronic component with a dam provided at the first side of the carrier element, which dam abuts on the outer edge of the encapsulation material.
- the encapsulation material fills the space between the dam and the carrier element completely and does not leave a central zone that is exposed to the environment.
- the package indeed can be used for microelectronic devices requiring an Optically active area' for providing and receiving optical signals, but such a package clearly can not be used for microelectronic components such as for example MEMS systems or devices comprising sensor elements on a top surface that are sensitive to heat, pressure or chemical substances.
- Fig. 1 is a cross-sectional view showing a package for a microelectronic component according to the prior art
- Fig. 2 is a is a cross-sectional view showing another package for a microelectronic component according to the prior art
- Fig. 3 is a cross-sectional view showing a preferred embodiment of a package for a microelectronic component according to the invention
- Figs. 4a and b are perspective top views showing packages for a microelectronic component according to the prior art (Fig. 4a) and according to the invention (Fig. 4b) respectively.
- a cross-sectional view of a package 70 is shown, which is taken along line 3-3 in Fig. 4b.
- the package 70 comprises a dam 44 provided on the outside layer 32 of the first side 16.
- the dam comprises a step-shaped surface transition 46 that is arranged between the outside layer 32 and the conductor lines 14 or a layer 49 under the outside layer (see Figs 4a and b). It influences the shape of the glob top material 30 during its curing so as to enlarge the width L of the central zone 40 and thus enlarge the surface area thereof.
- Disposing a respective inner edge 48 see Fig.
- edge 48 of the outside layer is disposed more to the outside of the carrier element 12 while the additional layer is applied on top of the conductive tracks and a first lower layer, the strip shaped additional layer abutting on the outside layer 32 and the outer edge 36 respectively.
- the top layer is made somewhat thicker in this case, or at least thicker than outside layer 32.
- the outside layer 32 is a solder resist layer, which is usually applied for these types of packages to cover and protect the conductive surface tracks.
- An alternative to create a surface transition at the first side is to arrange a groove in the outside layer 32, a substantially vertical outer wall thereof acting as the required surface transition.
- the outside layer 32 should have sufficient thickness.
- Another possibility is starting from the embodiment in Fig. 1 and without applying any additional layers disposing the outside layer 32 such that the inner edge 48 (see Fig. 1) thereof is shifted to the outside of the carrier element 12 (direction B and C). In this way the inner edge 48 can form the surface transition, the encapsulation material 30 abutting on this edge.
- the outside layer 32 should have sufficient thickness.
- the layer thickness of the protective outside layer as it is used at present generally will not be sufficient.
- the step-shaped surface transition according to the invention should be such that it influences or rather increases the contact angle of the encapsulation material abutting on such a transition at the first side as compared to the situation wherein the first side in the area around the outer edge of the encapsulation material is flat. It does not necessarily require a straight vertical wall between the two surfaces adjacent to the transition.
- the height h of the dam preferably is much lower compared to the height H of the glob top ring 30, which is at least ten times as large. Typical dimensions are 400 ⁇ m height for the glob top and 20-30 ⁇ m height for the dam.
- the carrier element 12 can be any element comprising a conductive or metallic structure that is embedded in a non-conductive matrix material and that is suited to accommodate a microelectronic component.
- the creation of the dam 44 can be integrated with the manufacturing of the carrier element 12. Preferably one adds an additional top layer of solder resist, the top layer forming a strip with a rectangular shape. Together with the relatively small height of the dam this means that not only few additional material is needed but also that the additional processing is relatively little in order to create a working embodiment according to the present invention.
- the additional processing is in particular little compared to the additional manufacturing that is required to obtain the dam as disclosed in US patents 6,674,159. In these cases the additional work is part of the manufacturing process of the package itself and involves processing steps with the microelectronic component, while according to the present invention it only involves a small modification of the carrier element.
- the strip shaped dam can be formed on an existing carrier element or substrate in the following manner. First a layer of liquid solder resist material is screen printed on top of the outside solder resist layer at the first side. Then a mask that exposes a rectangular strip is placed over this layer, which strip is cured by means of UV light. Finally the unexposed parts are chemically stripped, leaving the required dam configuration.
- Figs. 4a and 4b show perspective top views showing a package 70 for a microelectronic component according to the invention and a package 10 according to the prior art respectively.
- Fig. 4b more clearly shows the dam 44 having the form of a rectangular strip, the encapsulation material 30 abutting the strip.
- the strip is square.
- the dam comprises a step-shaped surface transition between a top surface of the strip and the conductive tracks 14 or a first lower layer 49 (directly under the outside layer 32) respectively.
- the encapsulation material 30 exposes a central zone 40 to the environment of which the surface area is larger and better to control when curing the glob top material in case of the presence of dam 44. This is clearly illustrated by comparing the glob top material 30 from Fig. 4a and 4b respectively.
- an epoxy material such as Hysol®
- the encapsulation material is dispensed on the package with a CAMALOT 3700 epoxy dispenser, which has an injection needle operating with a dispensing speed of 10- 20 mm/s, an air pressure of 40-60 psi and a height of 0.7-0.8 mm from the microelectronic component. After dispensing the epoxy material it is cured in an oven at about 170 0 C for approximately 3 hours.
- the invention can be applied for all packages requiring an exposed central area on a top surface of a microelectronic component. These packages have been discussed before when discussing the prior art as shown in Figs. 1 and 2.
- a typical example is to apply the package for photodiode integrated circuits.
- a single optical pick-up IC for example can be used for read/write applications to make an optical processing unit that is suitable for all kinds of CD and DVD devices.
- the package according to the invention is furthermore applicable for ball grid array (BGA) type of packages and for bulk acoustic wave filters.
- BGA ball grid array
- the polymeric or epoxy materials known at present cannot withstand this type of laser radiation. This means that making use of an optically transparent material instead of leaving an exposed central zone is not an option for these blue-ray devices. Furthermore it is important that the central zone has a sufficient area ensuring that the laser radiation does not harm the encapsulation material.
- the microelectronic component can be any suitable component, such as integrated circuits, photocells or MEMS elements. Furthermore it is possible to combine several microelectronic components that are mutually connected within the package (also referred to as system in package). In case MEMS elements are present at a first surface of the microelectronic component it could be advantageous to cover the exposed area with some kind of lid (not shown in the drawings) that is connected to an outer area of the encapsulation material. Such elements in general must be able to rotate, translate, etc in a free space but for the rest are preferably protected from the surrounding environment. It should be clear to a person skilled in the art that the present invention is not limited to the exemplary embodiments discussed above, but that several variations and modifications are possible within the protective scope of the invention as defined in the appending claims.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Chemical & Material Sciences (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Analytical Chemistry (AREA)
- Biochemistry (AREA)
- General Health & Medical Sciences (AREA)
- Immunology (AREA)
- Pathology (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Life Sciences & Earth Sciences (AREA)
- Health & Medical Sciences (AREA)
- Electrochemistry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2006800274397A CN101233619B (zh) | 2005-07-28 | 2006-07-13 | 微电子部件的封装及其制造方法 |
EP06780068A EP1913641A1 (en) | 2005-07-28 | 2006-07-13 | A package and manufacturing method for a microelectronic component |
US11/996,331 US20090127690A1 (en) | 2005-07-28 | 2006-07-13 | Package and Manufacturing Method for a Microelectronic Component |
JP2008523497A JP2009503837A (ja) | 2005-07-28 | 2006-07-13 | マイクロエレクトロニクス部品用パッケージ及びその製造方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP05106971 | 2005-07-28 | ||
EP05106971.4 | 2005-07-28 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2007012992A1 true WO2007012992A1 (en) | 2007-02-01 |
Family
ID=37461405
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB2006/052385 WO2007012992A1 (en) | 2005-07-28 | 2006-07-13 | A package and manufacturing method for a microelectronic component |
Country Status (6)
Country | Link |
---|---|
US (1) | US20090127690A1 (ja) |
EP (1) | EP1913641A1 (ja) |
JP (1) | JP2009503837A (ja) |
CN (1) | CN101233619B (ja) |
TW (1) | TW200709363A (ja) |
WO (1) | WO2007012992A1 (ja) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2009113003A2 (en) * | 2008-03-13 | 2009-09-17 | Nxp B.V. | Luminescent component and manufacturing method |
EP2287596A1 (en) * | 2009-08-11 | 2011-02-23 | Sensirion AG | Sensor with glob-top and method for manufacturing the same |
WO2012010400A1 (de) * | 2010-07-22 | 2012-01-26 | Osram Opto Semiconductors Gmbh | Halbleiterbauelement und verfahren zur herstellung eines halbleiterbauelements |
WO2012041925A1 (de) * | 2010-09-30 | 2012-04-05 | Osram Opto Semiconductors Gmbh | Optoelektronisches bauelement und verfahren zur herstellung eines optoelektronischen bauelements |
FR2986902A1 (fr) * | 2012-02-09 | 2013-08-16 | Pixinbio | Procede d'assemblage d'un dispositif portable d'analyse d'echantillon biologique |
RU2521749C2 (ru) * | 2008-09-30 | 2014-07-10 | Бриджлюкс, Инк. | Осаждение фосфора для светодиода |
KR101864577B1 (ko) * | 2010-07-07 | 2018-07-13 | 로베르트 보쉬 게엠베하 | 센서 모듈 및 센서 모듈의 제조 방법 |
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US9230874B1 (en) * | 2009-07-13 | 2016-01-05 | Altera Corporation | Integrated circuit package with a heat conductor |
CN109411486B (zh) * | 2017-08-16 | 2020-12-08 | 胜丽国际股份有限公司 | 感测器封装结构 |
EP3450391A1 (en) | 2017-08-28 | 2019-03-06 | Indigo Diabetes N.V. | Encapsulation of sensing device |
JP2020047664A (ja) * | 2018-09-14 | 2020-03-26 | キオクシア株式会社 | 半導体装置および半導体装置の作製方法 |
CN113526449A (zh) * | 2020-04-14 | 2021-10-22 | 鹰克国际股份有限公司 | 芯片封装结构及其制法 |
DE102021113715A1 (de) * | 2021-05-27 | 2022-12-01 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Halbleiterbauelement und Verfahren zur Herstellung eines Halbleiterbauelements |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5219712A (en) * | 1987-11-28 | 1993-06-15 | Thorn Emi Plc | Method of forming a solid article |
DE19810060A1 (de) * | 1997-05-07 | 1998-11-12 | Fraunhofer Ges Forschung | Verfahren zur Verbindung eines Bauelements mit einem Substrat und eine damit hergestellte elektrische Schaltung |
WO2000047030A1 (en) * | 1999-02-08 | 2000-08-10 | Amkor Technology, Inc. | Electrostatic discharge protection package and method |
US20010015492A1 (en) * | 1996-05-24 | 2001-08-23 | Salman Akram | Packaged die on pcb with heat sink encapsulant |
EP1187207A2 (en) * | 2000-09-07 | 2002-03-13 | STMicroelectronics, Inc. | Surface mount package with integral electro-static charge dissipating ring using lead frame as ESD device |
US6379997B1 (en) * | 1993-12-06 | 2002-04-30 | Fujitsu Limited | Semiconductor device and method of producing the same and semiconductor device unit and method of producing the same |
US6566745B1 (en) * | 1999-03-29 | 2003-05-20 | Imec Vzw | Image sensor ball grid array package and the fabrication thereof |
US6603183B1 (en) * | 2001-09-04 | 2003-08-05 | Amkor Technology, Inc. | Quick sealing glass-lidded package |
US6707166B1 (en) | 2000-02-17 | 2004-03-16 | Oki Electric Industry Co., Ltd. | Semiconductor devices and manufacturing method thereof |
US6825551B1 (en) | 1999-09-02 | 2004-11-30 | Stmicroelectronics S.A. | Method for packaging a semiconductor chip containing sensors and resulting package |
US20050236685A1 (en) * | 2004-04-26 | 2005-10-27 | Matsushita Electric Industrial Co., Ltd. | Optical device and method for fabricating the same |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5175612A (en) * | 1989-12-19 | 1992-12-29 | Lsi Logic Corporation | Heat sink for semiconductor device assembly |
US6384473B1 (en) * | 2000-05-16 | 2002-05-07 | Sandia Corporation | Microelectronic device package with an integral window |
US6303978B1 (en) * | 2000-07-27 | 2001-10-16 | Motorola, Inc. | Optical semiconductor component and method of manufacture |
DE10118231A1 (de) * | 2001-04-11 | 2002-10-17 | Heidenhain Gmbh Dr Johannes | Optoelektronische Baulelmentanordnung und Verfahren zur Herstellun einer oploelektronischen Bauelementanordnung |
US6861750B2 (en) * | 2002-02-01 | 2005-03-01 | Broadcom Corporation | Ball grid array package with multiple interposers |
-
2006
- 2006-07-13 WO PCT/IB2006/052385 patent/WO2007012992A1/en active Application Filing
- 2006-07-13 US US11/996,331 patent/US20090127690A1/en not_active Abandoned
- 2006-07-13 EP EP06780068A patent/EP1913641A1/en not_active Withdrawn
- 2006-07-13 CN CN2006800274397A patent/CN101233619B/zh active Active
- 2006-07-13 JP JP2008523497A patent/JP2009503837A/ja not_active Withdrawn
- 2006-07-25 TW TW095127118A patent/TW200709363A/zh unknown
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5219712A (en) * | 1987-11-28 | 1993-06-15 | Thorn Emi Plc | Method of forming a solid article |
US6379997B1 (en) * | 1993-12-06 | 2002-04-30 | Fujitsu Limited | Semiconductor device and method of producing the same and semiconductor device unit and method of producing the same |
US20010015492A1 (en) * | 1996-05-24 | 2001-08-23 | Salman Akram | Packaged die on pcb with heat sink encapsulant |
DE19810060A1 (de) * | 1997-05-07 | 1998-11-12 | Fraunhofer Ges Forschung | Verfahren zur Verbindung eines Bauelements mit einem Substrat und eine damit hergestellte elektrische Schaltung |
WO2000047030A1 (en) * | 1999-02-08 | 2000-08-10 | Amkor Technology, Inc. | Electrostatic discharge protection package and method |
US6566745B1 (en) * | 1999-03-29 | 2003-05-20 | Imec Vzw | Image sensor ball grid array package and the fabrication thereof |
US6825551B1 (en) | 1999-09-02 | 2004-11-30 | Stmicroelectronics S.A. | Method for packaging a semiconductor chip containing sensors and resulting package |
US6707166B1 (en) | 2000-02-17 | 2004-03-16 | Oki Electric Industry Co., Ltd. | Semiconductor devices and manufacturing method thereof |
EP1187207A2 (en) * | 2000-09-07 | 2002-03-13 | STMicroelectronics, Inc. | Surface mount package with integral electro-static charge dissipating ring using lead frame as ESD device |
US6603183B1 (en) * | 2001-09-04 | 2003-08-05 | Amkor Technology, Inc. | Quick sealing glass-lidded package |
US20050236685A1 (en) * | 2004-04-26 | 2005-10-27 | Matsushita Electric Industrial Co., Ltd. | Optical device and method for fabricating the same |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009113003A2 (en) * | 2008-03-13 | 2009-09-17 | Nxp B.V. | Luminescent component and manufacturing method |
WO2009113003A3 (en) * | 2008-03-13 | 2009-11-05 | Nxp B.V. | Luminescent component and manufacturing method |
US8376801B2 (en) | 2008-03-13 | 2013-02-19 | Nxp B.V. | Luminescent component and manufacturing method |
RU2521749C2 (ru) * | 2008-09-30 | 2014-07-10 | Бриджлюкс, Инк. | Осаждение фосфора для светодиода |
EP2287596A1 (en) * | 2009-08-11 | 2011-02-23 | Sensirion AG | Sensor with glob-top and method for manufacturing the same |
KR101864577B1 (ko) * | 2010-07-07 | 2018-07-13 | 로베르트 보쉬 게엠베하 | 센서 모듈 및 센서 모듈의 제조 방법 |
WO2012010400A1 (de) * | 2010-07-22 | 2012-01-26 | Osram Opto Semiconductors Gmbh | Halbleiterbauelement und verfahren zur herstellung eines halbleiterbauelements |
US20130181247A1 (en) * | 2010-07-22 | 2013-07-18 | Osram Opto Semiconductors Gmbh | Semiconductor Component and Method for Producing a Semiconductor Component |
WO2012041925A1 (de) * | 2010-09-30 | 2012-04-05 | Osram Opto Semiconductors Gmbh | Optoelektronisches bauelement und verfahren zur herstellung eines optoelektronischen bauelements |
FR2986902A1 (fr) * | 2012-02-09 | 2013-08-16 | Pixinbio | Procede d'assemblage d'un dispositif portable d'analyse d'echantillon biologique |
Also Published As
Publication number | Publication date |
---|---|
CN101233619B (zh) | 2012-02-15 |
TW200709363A (en) | 2007-03-01 |
EP1913641A1 (en) | 2008-04-23 |
JP2009503837A (ja) | 2009-01-29 |
CN101233619A (zh) | 2008-07-30 |
US20090127690A1 (en) | 2009-05-21 |
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