WO2007011012A1 - Dispositif d’amplification de puissance - Google Patents

Dispositif d’amplification de puissance Download PDF

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Publication number
WO2007011012A1
WO2007011012A1 PCT/JP2006/314452 JP2006314452W WO2007011012A1 WO 2007011012 A1 WO2007011012 A1 WO 2007011012A1 JP 2006314452 W JP2006314452 W JP 2006314452W WO 2007011012 A1 WO2007011012 A1 WO 2007011012A1
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WO
WIPO (PCT)
Prior art keywords
signal
pulse width
clock
class
width modulation
Prior art date
Application number
PCT/JP2006/314452
Other languages
English (en)
Japanese (ja)
Inventor
Minoru Yoshida
Hiroyuki Ishihara
Original Assignee
Pioneer Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Corporation filed Critical Pioneer Corporation
Priority to JP2007526061A priority Critical patent/JP4688225B2/ja
Publication of WO2007011012A1 publication Critical patent/WO2007011012A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/181—Low-frequency amplifiers, e.g. audio preamplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/03—Indexing scheme relating to amplifiers the amplifier being designed for audio applications
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/342—Pulse code modulation being used in an amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/351—Pulse width modulation being used in an amplifying circuit

Definitions

  • the present invention belongs to a technical field of a power amplifying apparatus that performs nonlinear distortion correction.
  • mini-components are required to be miniaturized due to design problems, and miniaturization of each circuit is required.
  • the amplifying device especially the case is large and heavy.
  • miniaturization of power amplification devices that tend to be.
  • a signal input to a power amplifying device such as a PCM (Pulse Code Modulation) signal is applied to pulse width modulation (PWM).
  • PWM pulse width modulation
  • the signal is amplified after being converted to a digitally modulated signal by performing modulation processing such as pulse density modulation (PDM) and output to the analog signal via a low-pass filter.
  • modulation processing such as pulse density modulation (PDM) and output to the analog signal via a low-pass filter.
  • PDM pulse density modulation
  • class D power amplifying apparatus A power amplifying apparatus using this class D power amplifying method (hereinafter referred to as "class D power amplifying apparatus").
  • this power amplifying device corrects nonlinear distortion in the switching element.
  • a predetermined trapezoidal wave signal is generated as a reference signal, the edge width of the input pulse signal is adjusted by changing the slice level, and negative feedback control is performed! /, (For example, Patent Document 1).
  • Patent Document 1 Special Table 2001—517393 (International Publication W098Z44626 Pamphlet)
  • the edge width is adjusted based on the slice level, and therefore depends on the slope of the edge in the generated trapezoidal wave. Therefore, this class D power amplifying device ensures a sufficient amount of correction for edge width correction because the slope of the edge becomes steep when the clock frequency becomes high, and the generated trapezoidal wave becomes close to a rectangular wave. I can't.
  • the present invention solves an example of the above-mentioned problem by accurately preventing nonlinear distortion that occurs when switching processing is performed, and is applicable to high frequencies and can be downsized. It is to provide a class D power amplifier.
  • the invention according to claim 1 is a class D power amplifying device that performs pulse modulation on a sound signal, amplifies the pulse modulated sound signal, and outputs the amplified signal to a speaker
  • a second generation means for amplifying the signal level of the pulse width modulation signal to generate a loud sound signal, a detection means for detecting an error between the generated pulse width modulation signal and the loud sound signal, Generating means for generating a clock signal formed at a clock frequency that varies in accordance with the detected error signal.
  • the first generation means generates the received sound signal force and the pulse width modulation signal based on the clock signal generated by the generation means.
  • FIG. 1 is a block diagram showing a configuration in a first embodiment of a class D power amplifier according to the present application.
  • FIG. 2 is a graph showing a clock frequency range of a clock signal generated by a second clock signal generation unit corresponding to a detected error signal voltage value in the first embodiment.
  • FIG. 3 is a diagram showing signal waveforms at various parts when an error signal is larger than “0” in the generation process of the second clock signal of the first embodiment.
  • FIG. 4 is a diagram showing signal waveforms at various parts when an error signal is smaller than “0” in the generation process of the second clock signal of the first embodiment.
  • FIG. 5 is a timing chart in each part when an error signal is larger than “0” in the pulse width modulation operation of the first exemplary embodiment.
  • FIG. 6 is a timing chart in each part when the error signal is smaller than “0” in the pulse width modulation operation of the first exemplary embodiment.
  • FIG. 7 is another example of the block diagram showing the configuration of the first embodiment of the class D power amplifier according to the present application.
  • FIG. 8 is another example of a graph showing the clock frequency range of the clock signal generated by the second clock signal generation unit corresponding to the voltage value of the detected error signal in the first embodiment.
  • FIG. 9 is a block diagram showing a configuration in a second embodiment of a class D power amplifier according to the present application.
  • FIG. 10 is a diagram showing signal waveforms at various parts when an error signal is larger than “0” in the generation process of the second clock signal of the second embodiment.
  • FIG. 11 is a diagram showing signal waveforms at various parts when an error signal is smaller than “0” in the generation process of the second clock signal of the second embodiment.
  • FIG. 12 is a timing chart in each part when an error signal is larger than “0” in the pulse width modulation operation of the second exemplary embodiment. 13] FIG. 13 is a timing chart in 1--each o section when the error signal is smaller than “0” in the pulse width modulation operation of the second embodiment.
  • FIG. 15 is a block diagram showing a configuration in a third embodiment of a class D power amplifier according to the present application.
  • FIG. 16 is a diagram illustrating an example of signal waveforms in the asynchronous circuit according to the third embodiment. 17] Another example of a block diagram showing the configuration of the third embodiment of the class D power amplifier according to the present application.
  • a PCM signal read from a recording medium recorded as a digital signal such as a CD (Compact Disc) is input, and the signal of the input PCM signal is input.
  • the class D power amplifying apparatus of the present application is applied to a class D amplifying apparatus that amplifies the level and outputs it to a speaker.
  • the following description is also applicable to a class D power amplifying apparatus that uses a lch class D power amplifying apparatus, a stereo, a 5. lch or a 7. lch multi-channel speaker.
  • FIG. 1 is a block diagram showing the configuration of the class D power amplifying apparatus of this embodiment
  • FIG. 2 shows the second clock signal generator corresponding to the voltage value of the detected error signal in this embodiment
  • 5 is a graph showing a clock frequency range of a clock signal generated in response. Also, in the following explanation, an application example in the single sided PWM method is explained.
  • the class D power amplifying apparatus 100 of this embodiment performs pulse width modulation on a PCM signal input based on a predetermined clock signal, and generates a PWM signal.
  • the power supply voltage is switched according to the PWM signal (hereinafter referred to as “switching process”), and the PWM signal with the amplified signal level is output to the speaker.
  • the class D power amplifying apparatus 100 of the present embodiment calculates an error signal between the PWM signal before the switching process and the PWM signal after the switching process are performed as described later.
  • a clock signal whose clock frequency changes according to the change in the calculated error signal is generated.
  • the class D power amplifying apparatus 100 generates the generated clock in order to correct the nonlinear distortion that occurs when the switching process is performed. Based on the signal, pulse width modulation is applied to the PCM signal.
  • This class D power amplifying apparatus 100 includes an oversampling processing unit 101 and a noise shaving circuit 102 for performing over-sampling processing and noise-shaping pink processing as preprocessing on an input PCM signal,
  • a first clock signal generation unit 103 that generates a clock signal (hereinafter referred to as a “first clock signal”) for operating the processing unit 101 and the noise shaving circuit 102, and a preprocessed PCM signal are temporarily stored.
  • the output control unit 105 that controls the output of the PCM signal stored in the buffer 104, and the PCMZPWM conversion unit 106 that generates a PWM signal by performing pulse width modulation on the output-controlled PCM signal. And have.
  • the class D power amplifying apparatus 100 performs switching processing based on the generated PWM signal, and a switching amplification circuit 107 that amplifies the signal level of the PWM signal by k times, and a signal level
  • the first low-pass filter (hereinafter referred to as “first LPF”) 108 that filters the amplified PWM signal to generate an amplified signal, and an amplifier 109 that multiplies the signal level of the expanded signal by lZk.
  • a second low-pass filter (hereinafter referred to as “second LPF”) 110 that performs the same filtering process as the first low-pass filter on the PWM signal output from the PCMZPWM converter 106, and a loudspeaker multiplied by lZk
  • an error signal calculation unit 111 for calculating an error signal between the signal and the PWM signal output from the second low-pass filter.
  • this class D power amplifying apparatus 100 converts the calculated error signal into a DC voltage (DC), that is, an integrator 112 that performs averaging, and a voltage value of the error signal converted into a DC voltage.
  • DC DC voltage
  • a second clock signal generation unit 115 that generates a signal “)” and a waveform shaping circuit 116 that shapes the waveform of the generated second clock signal.
  • the buffer 104 of the present embodiment constitutes the reception means, the first generation means, and the storage means of the present invention
  • the output control unit 105 includes the first generation means and the control means of the present invention.
  • the PCMZPWM converter 106 of the present embodiment constitutes the first generation means and pulse width modulation signal generation means of the present invention
  • the switching amplifier circuit 107 This constitutes a clear second generation means.
  • the error signal calculation unit 111 of the present embodiment constitutes the detection means of the present invention
  • the second clock signal generation unit 115 constitutes the generation means of the present invention.
  • the PCM signal is input to the oversampling processing unit 101 via the input terminal T.
  • the oversampling processing unit 101 generates a first clock signal generated by the first clock signal generation unit 103. Based on one clock signal, an oversampling process is performed on the input PCM signal, and the PCM signal subjected to the oversampling process is output to the noise shaving circuit 102.
  • the oversampling processing unit 101 of the present embodiment executes a process of sampling an input PCM signal, such as 4 times or 8 times, at a sampling frequency that is a predetermined multiple of the sampling frequency of the PCM signal. It is like that.
  • An oversampled PCM signal is input to the noise shaving circuit 102, and the noise shaving circuit 102 receives the first clock signal generated by the first clock signal generator 103. Based on this, the noise PC pink processing is performed to reduce the input PCM signal power quantization bit number to a predetermined bit number (N bits) and shift the quantization noise to a high frequency band. Also, the noise shaving circuit 102 writes the PCM signal that has been subjected to the noise shaving pink process into the buffer 104.
  • the first clock signal generation unit 103 generates a first clock signal based on a predetermined clock frequency, and the oversampling processing unit 101 and the noise shaving circuit 102 generate the generated first clock signal. And output to the buffer 104.
  • the noffer 104 has a predetermined storage capacity, and can temporarily store a PCM signal that has been subjected to oversampling processing and noise shear pink processing. Further, in this buffer 104, input / output timing control is performed independently, and PCM signal writing and reading are performed. The time difference due to the difference is absorbed. [0028] Specifically, the PCM signals output from the noise shaving circuit 102 are sequentially written in the buffer 104 based on the first clock signal. As described later, under the control of the control unit 105, the stored PCM signal is output to the PCMZPWM conversion unit 106 based on a predetermined timing, that is, a clock signal generated based on the second clock signal. It has become.
  • the write rate in the buffer 104 is constant.
  • the storage capacity of the nother 104 of this embodiment is preferably a capacity capable of absorbing a time length equal to or greater than the switching frequency fluctuation width in the switching amplifier circuit 107 described later.
  • the output control section 105 has a frequency divider for the second clock signal output from the waveform shaping circuit 116 (NZ2 N) times, the period of the second clock signal input (NZ2 N)
  • the PCM signal stored in the PCMZPWM conversion unit 106 is output from the notch 104 based on the second clock signal multiplied by (NZ2 N ).
  • N indicates the number of bits of the PCM signal output from the noise shaving circuit 102.
  • the time resolution of the PCMZPWM converter 106 is (2 N ) times that of the PCM signal, (N / 2 N) of the second clock signal used in the PCM / PWM converter 106 described later. ) Read out at double timing!
  • the PCMZPWM converter 106 is configured to receive a PCM signal read at a predetermined timing and subjected to a predetermined pre-processing. Based on the clock signal, the input PCM signal is subjected to pulse width modulation, and a PWM signal is generated and output to the switching amplifier circuit 107 and the second LPF 110.
  • the second clock signal is changed based on the error signal, and the PCMZPWM converter 106 is input based on the changed second clock signal.
  • the pulse width modulation is applied to PCM signals.
  • the switching amplifier circuit 107 is input with a pulse width modulated PWM signal.
  • the switching amplifier circuit 107 is, for example, a MOS (Metal Oxide Semiconductor) transistor, which is a field effect transistor (hereinafter referred to as “FET: Field Effect”). TransistorJ is called. ) FET and DC power supply for applying drive voltage to drive the speaker, perform predetermined control such as switching control of the input PWM signal, and increase the signal level of the PWM signal k times In other words, the signal is amplified to a predetermined signal level.
  • the switching amplifier circuit 107 outputs the amplified PWM signal to the first LPF 108.
  • the switching amplifier circuit 107 may use a bipolar transistor instead of the FET.
  • a PWM signal amplified to a predetermined level is input to the first LPF 108.
  • the first LPF 108 is high in response to the PWM signal input to remove high-frequency noise.
  • the loudspeaker signal is generated by performing the band cut-off process, and the generated loudspeaker signal is output to the speaker and the amplifier 109.
  • Amplified signal generated by the first LPF 108 is input to the amplifier 109, and this amplifier 109 calculates one signal when calculating an error signal, that is, a PCM / PWM converter.
  • the signal level of the input loudspeak signal is amplified (lZk) times, and the loudspeak signal whose signal level is amplified (lZk) times is an error signal. It will be output to the calculation unit 111!
  • the PWM signal output from the PCMZPWM converter 106 is input to the second LPF 110, and this second LPF 110 receives the other signal, that is, the loudspeaker signal when calculating the error signal.
  • the high-frequency cutoff processing similar to that of the first LP F108 is performed on the input PWM signal for consistency, and the signal subjected to the high-frequency cutoff processing is output to the error signal calculation unit 111. Yes.
  • the error signal calculation unit 111 receives a loudspeaker signal whose signal level is multiplied by (lZk) and a signal from which the second LPF 110 force is also output. An error signal is calculated on the basis of each of the signals, and the calculated error signal is output to the integrator 112.
  • the error signal calculation unit 111 of the present embodiment is composed of a subtracter, and the loudness signal power with the signal level multiplied by (lZk) is also subtracted from the signal output from the second LPF 110, resulting in an error. A difference signal is generated! / Speak.
  • the error signal generated by the error signal generation unit is input to the integrator 112.
  • the integrator 112 performs an integration operation on the input error signal to obtain a DC voltage. Digitization (DC digitization), that is, the inputted error signal is averaged and output to the voltage detection unit 113 and the limiter circuit 114.
  • the integrator 112 has a low and low-pass time constant that is equal to or less than the sampling period (F) of the oversampled PCM signal shown in (Equation 1) and satisfies (Equation 2).
  • Fs indicates the sampling frequency of the PCM signal.
  • the voltage detection unit 113 is configured to receive an error signal whose DC value has been input by the integrator 112. The voltage detection unit 113 detects and detects the voltage value of the input error signal. The output of the limiter circuit 114 is controlled based on the voltage value!
  • the limiter circuit 114 is supplied with the averaged error signal output from the integrator 112 and the voltage value output from the voltage detection unit 113. Is an upper limit voltage value (hereinafter, referred to as “upper limit voltage value”) determined based on the voltage value detected by the voltage detection unit 113, and a predetermined lower limit voltage value (hereinafter, “ When the following voltage value is input from the integrator 112 as an error signal, the upper limit voltage value or the lower limit voltage value is output.
  • upper limit voltage value hereinafter, referred to as “upper limit voltage value”
  • the variation range of the clock frequency in the clock signal generated by the second clock signal generation unit 115 is determined in advance, and belongs to this variation range. Based on the voltage value detected by the voltage detector 113, the upper and lower thresholds in the limiter circuit 114 are appropriately determined so as to generate a clock signal formed at the clock frequency. .
  • the limiter circuit 114 may limit the input error signal based on a predetermined upper limit voltage value and lower limit voltage value and output a predetermined voltage value. Good. In this case, the voltage detection unit 113 described above is not necessary.
  • the voltage value output from the limiter circuit 114 is input to the second clock signal generation unit 115.
  • the second clock signal generation unit 115 is generated by the PCMZPWM conversion unit 106.
  • a predetermined clock frequency is generated according to the input voltage value, and the second clock signal formed at the generated clock frequency is sent to the waveform shaping circuit 116. It is designed to output.
  • the second clock signal generator 115 generates a clock signal formed at a clock frequency belonging to a predetermined frequency range in advance by the limiter circuit 114 at the upper limit voltage value and the lower limit voltage value. I'm going to let you go.
  • the second clock signal generator 115 generates a clock frequency within a frequency range from a lower limit frequency F11 to an upper limit frequency F12, When the voltage value is “0” or more, the generated clock frequency is increased. When the voltage value in the error signal is “0” or less, the generated clock frequency is decreased.
  • the second clock signal generation unit 115 generates the clock frequency within the fluctuation range having the center frequency Fc calculated as in (Expression 3) based on (Expression 1). Is starting to occur. However, N in (Equation 3) indicates the number of output bits in the noise shaving circuit 102.
  • the upper limit frequency F12 is a pulse width force of the PWM signal modulated based on the second clock signal formed at the clock frequency F12 in order to prevent malfunction in the switching amplifier circuit 107.
  • the clock frequency F12 is set in advance so that it is larger than the minimum pulse width that can be used by the device!
  • the lower limit frequency F11 is a frequency axis target for the center frequency fc so that the deviation between the center frequency fc, which is the center during operation, and the upper limit frequency fl2, ie, I fl2-fc I or more is satisfied.
  • the second clock signal By configuring the second clock signal in this way, a highly stable configuration is possible.
  • the waveform shaping circuit 116 is supplied with the second clock signal generated by the second clock signal generator 115, and the waveform shaping circuit 116 receives the input second clock.
  • the signal waveform is converted from a sine wave to a rectangular wave, and the second clock signal converted to the rectangular wave is output to the PCMZPWM converter 106 and the output controller 105.
  • FIG. 3 is a diagram showing signal waveforms at various portions when the error signal is larger than “0” in the generation process of the second clock signal of the present embodiment
  • FIG. 4 is a diagram of the first embodiment of the present embodiment
  • FIG. 5 is a diagram showing signal waveforms in respective parts when an error signal is smaller than “0” during the generation process of the two clock signals.
  • FIG. 5 is a timing chart in each part when the error signal is larger than “0” in the pulse width modulation operation of the present embodiment.
  • FIG. 6 shows the nors width modulation of the present embodiment. 6 is a timing chart in each part when the error signal is smaller than “0”.
  • the reproduction signal amplified in the class D power amplifier 100 is input as a PCM signal having a 4-bit PCM value of "0101", and the error signal is larger than "0". If it is smaller than “0”, the case will be described separately.
  • the number of output bits in the noise shaving circuit 102 is 4 bits, and the clock frequency of the first clock signal is 4 Hz. As described above, the number of PWM steps is “16” from each of the conditions, and the center frequency of the clock frequency of the second clock signal is 16 Hz.
  • the reproduction signal shown in FIG. 3 (a) when the reproduction signal shown in FIG. 3 (a) is loudened, if the amplification factor in the switching amplifier circuit 107 is “1”, a predetermined value in each part such as the switching amplifier is given. Based on the processing, the loudspeaker signal containing the noise component shown in Fig. 3 (b) is output to the speaker.
  • the integrator 112 detects the error signal shown in FIG.
  • the limiter circuit 114 outputs the signal shown in (d), and the limiter circuit 114 is based on the upper limit voltage value and the lower limit voltage value determined as described above. Outputs the signal shown in Fig. 3 (e).
  • the second clock signal generation unit 115 generates a sine wave clock signal with a variable clock frequency as shown in FIG. 3 (f) based on the signal shown in FIG. Output to the shaping circuit 116.
  • the waveform shaping circuit 116 shapes the sine wave clock signal into a rectangular wave as described above.
  • error signal calculation section 111 detects the error signal ("0") shown in Fig. 4 (a)
  • integrator 112 shows the error signal shown in Fig. 4 (b) based on the error signal.
  • the limiter circuit 114 outputs a signal shown in FIG. 4 (c) based on the upper limit voltage value and the lower limit voltage value determined as described above.
  • the second clock signal generation unit 115 generates a sine wave clock signal with a variable clock frequency, as shown in FIG. 4 (d), based on the signal in FIG. Output to the shaping circuit 116.
  • the waveform shaping circuit 116 shapes the sine wave clock signal into a rectangular wave as described above.
  • a 4-bit PCM signal having a PCM value of “0101” is input to the input terminal, and oversampling processing and noise are performed based on the first clock signal shown in FIG.
  • the PCM signal written to the notch 104 is generated based on the calculated error signal (> "O"), and the clock frequency shown in FIG.
  • the variable (NZ2 N) multiplied second clock signal is used to read out from PC 104 as the PCM signal shown in Fig. 5 (d)
  • the read PCM signal is shown in Fig. 5 (e).
  • the second clock signal with variable clock frequency shown in Fig. 5 it is converted to the PWM signal shown in Fig. 5 (f).
  • the PCM signal written to the nother 104 is generated based on the calculated error signal ( ⁇ "0"), and the clock frequency shown in Fig. 6 (a) is variable.
  • the second clock signal multiplied by (NZ2 N ) is used to read out from PC 104 as the PCM signal shown in Fig. 6 (b)
  • the read PCM signal is shown in Fig. 6 (c).
  • the second clock signal with variable clock frequency it is converted to the PWM signal shown in Fig. 6 (d).
  • the clock frequency of the second clock signal can be varied based on the error signal! Therefore, the second clock signal with the variable clock frequency can be changed.
  • Output control from the buffer 104 and PCMZPWM conversion based on the The pulse width of the PWM signal amplified by the pushing amplifier circuit 107 can be varied.
  • nonlinear distortion that occurs when switching processing is performed in the switching amplifier circuit 107 that is, nonlinear distortion that occurs due to switching of the DC power supply in the switching amplifier circuit 107.
  • since the clock frequency of the second clock signal varies, the generation of high frequency noise based on the clock frequency can be reduced.
  • the class D power amplifying apparatus 100 of the present embodiment is a class D power amplifying apparatus 100 that performs pulse modulation on a PCM signal, amplifies the pulse modulated PWM signal, and outputs the amplified PWM signal to a speaker.
  • a buffer 104 that receives a PCM signal, which is a digital signal, a PCMZPWM converter 106 that generates a PWM signal by pulse-modulating the received PCM signal, and a power supply voltage that is switched according to the generated PWM signal.
  • a switching amplifier circuit 107 that amplifies the signal level of the signal to generate a loud sound signal, an error signal calculation unit 111 that detects an error between the generated PWM signal and the loud sound signal, and a detected error signal.
  • a second clock signal generation unit 115 for generating a second clock signal formed at a clock frequency that varies with the second clock signal generation unit 1 15.
  • Clock signal Ru has been, a configuration for generating a PCM signal power PWM signal received based on.
  • the class D power amplifying apparatus 100 generates the second clock signal formed at the clock frequency that changes according to the detected error signal, and the generated second clock signal is generated. Using the clock signal, the received PCM signal power also generates a PWM signal.
  • the class D power amplifying apparatus 100 of the present embodiment can also generate a PWM signal from the received PCM signal power using the generated second clock signal, and is amplified by the switching amplifier circuit 107. Since the PWM signal pulse width can be varied, nonlinear distortion that occurs when switching processing is performed in the switching amplifier circuit 107, that is, switching the DC power supply on and off in the switching amplifier circuit 107. As a result, the nonlinear distortion generated by the It is possible to reduce the circuit scale and the dedicated circuit with high accuracy required to make the width of the circuit variable.
  • the clock frequency of the second clock signal fluctuates in the class D power amplifying device 100 of the present embodiment, generation of high frequency noise such as unnecessary radiation based on the clock frequency can be reduced. It becomes an EMI countermeasure (Electro Magnetic Interference) taka when receiving radio waves close to the high-frequency noise, for example, broadcast waves of 500 kHz to 1600 kHz.
  • EMI countermeasure Electro Magnetic Interference
  • the error signal calculation unit 111 is generated when the amplified signal is generated by smoothing the PWM signal whose signal level is amplified. Since the error from the loudspeaker signal is detected while smoothing the PWM signal, the second clock signal can be generated accurately, so that the pulse width modulation must be accurately performed on the PCM signal.
  • the switching amplifier circuit 107 can accurately prevent nonlinear distortion caused by switching the DC power supply on and off.
  • the class D power amplifying apparatus 100 of the present embodiment has an integrator 112 that calculates the average value of the detected error signal, and is formed at a different clock frequency according to the calculated average value.
  • the second clock signal can be generated.
  • the class D power amplifying apparatus 100 of the present embodiment can accurately generate the second clock signal, the overshoot that the waveform temporarily exceeds the specified level, and the waveform that is the specified level. This can prevent tracking of waveform distortion components such as undershoot that temporarily falls below, so that pulse width modulation can be performed accurately on the PCM signal. Nonlinear distortion caused by switching off can be accurately prevented.
  • the class D power amplifying apparatus 100 of the present embodiment since the class D power amplifying apparatus 100 of the present embodiment generates the second clock signal belonging to the frequency range determined in advance by the limiter circuit 114, the second clock signal can be generated stably. It is possible to accurately perform pulse width modulation on PCM signals.
  • the error signal calculation unit performs smoothing processing by the second LPF 110 on the (lZk) -multiplied sound signal and the PWM signal output from the PCMZ PWM conversion unit 106.
  • the error signal is calculated based on the signal that has been subjected to the processing.
  • the PWM signal amplified by the switching amplifier circuit 107 multiplied by (lZk) and the PCMZ PWM converter 106 The error signal may be calculated based on the PWM signal output from. In this case, similar to the above, each signal input to the error signal can be matched, so that the same effect as described above can be obtained.
  • the first clock signal having the same clock frequency is used for the oversampling processing unit 101 and the noise-shaping circuit. You can use different clock signals.
  • a limiter circuit 114 is provided, and the voltage value detected by the voltage detection unit 113 is input to the second clock signal generation unit 115 based on the upper limit voltage value and the lower limit voltage value.
  • the power to control the voltage value is not provided, the limiter circuit 114 is not provided, and the detected voltage value is held and input to the second clock signal generator 115 as shown in FIG. You can do it!
  • the single sided PWM method is described as an example of the PWM modulation method.
  • N in (Expression 1) to (Expression 3) is replaced with (N + 1).
  • the force applied to the single-ended configuration that is, the binary PWM modulation may be applied to the ternary PWM modulation. In this case, if the configuration of the present embodiment is applied to each PWM signal.
  • the oversampling processing unit 101 and the noise shaving circuit 102 of the present embodiment operate based on the first clock signal generated by the first clock signal generation unit 103.
  • Each oversampling processing unit 101 and noise shaping circuit 102 should be provided with a frequency dividing circuit so that it operates based on the divided first clock signal.
  • the PCM signal stored in the buffer in the first embodiment is clocked.
  • a PWM signal is generated with a clock signal having a predetermined clock frequency, written to the buffer, and the second clock signal is generated.
  • the feature is that the written PWM signal is read based on the signal.
  • FIG. 9 is a block diagram showing a configuration of the class D power amplifying apparatus of the present embodiment.
  • this class D power amplifying apparatus 200 performs pulse width modulation on the oversampling processing unit 101 and noise shaving circuit 102 and the noise-shaved PCM signal to generate a PWM signal.
  • PCMZPWM conversion unit 210 that generates the first clock signal generation unit 103 that generates the first clock signal for operating the oversampling processing unit 101, the noise shaving circuit 102, and the PCMZPWM conversion unit 210.
  • a buffer 211 for temporarily storing the PWM signal.
  • this class D power amplifying apparatus 200 includes a switching amplification circuit 107, a first LPF 108, an amplifier 109, a second LPF 110, an error signal calculation unit 111, an integrator 112, a voltage detection unit 113, a limiter circuit 114, a second clock signal generation unit 115, and a waveform shaping circuit 116.
  • the buffer 211 of this embodiment constitutes a receiving means, a first generating means, a storage means, and a control means of the present invention.
  • the PCMZPWM converter 210 of the present embodiment constitutes the receiving means, the first generating means and the pulse width modulation signal generating means of the present invention, and the amplifier circuit constitutes the second generating means of the present invention.
  • the error signal calculation unit 111 of the present embodiment constitutes the detection means of the present invention
  • the second clock signal generation unit 115 constitutes the generation means of the present invention.
  • the PCMZPWM converter 210 is configured to receive the PCM signal that has been subjected to the predetermined preprocessing output from the noise shaving circuit 102, and the PCMZPWM converter 210 receives the first clock signal. Based on the pulse width for the input PCM signal Modulation is performed, and a PWM signal is generated and output to the buffer 211.
  • the nother 211 has a predetermined storage capacity, and can temporarily store a PCM signal that has been subjected to oversampling processing and noise shear pink processing.
  • the input / output timing control is performed independently, and the PWM signal is written and read out. Due to the difference in timing and read timing, the pulse width of the PWM signal that is memorized is changed.
  • the buffer 211 sequentially writes the PWM signals output from the PCMZPWM converter 210 based on the first clock signal.
  • the buffer 211 has a predetermined value. Based on the timing, that is, based on the second clock signal output from the output control circuit 116, the stored PWM signal is output to the switching amplifier circuit 107 and the second LPF 110 based on the second clock signal. ing.
  • the first clock signal generator 103 has the same configuration as that of the first embodiment except that the first clock signal is output to the PCMZPWM converter 210.
  • FIG. 10 is a diagram showing signal waveforms at various parts when the error signal is larger than “0” in the generation process of the second clock signal of the present embodiment
  • FIG. FIG. 7 is a diagram showing signal waveforms in various parts when an error signal is smaller than “0” during the process of generating a two-clock signal.
  • FIG. 12 is a timing chart in each part when the error signal is larger than “0” in the pulse width modulation operation of the present embodiment.
  • FIG. 13 shows the pulse width modulation of the present embodiment. In operation, this is a timing chart in each part when the error signal is smaller than “0”.
  • the reproduction signal power bit amplified by the class D power amplifier 109 is input as a PCM signal having a PCM value of "0101" with bit
  • the error signal is larger than “0” and smaller than “0” will be described separately.
  • the number of output bits in the noise shaving circuit 102 is 4 bits, and the clock frequency of the first clock signal is 2.5 Hz. As described above, the number of PWM steps is “16” from each of the conditions, and the center frequency of the clock frequency of the second clock signal is 10 Hz.
  • the reproduction signal similar to that in the first embodiment is amplified, if the amplification factor in the switching amplifier circuit 107 is “1”, predetermined processing in each unit such as the switching amplifier unit is performed. Based on the above, a loudspeaker signal including a noise component is output to the speaker as in the first embodiment.
  • the integrator 112 when the error signal calculation unit 111 detects the error signal (> “0”) shown in FIG. 10 (&), the integrator 112 generates the error signal shown in FIG. 10 (b) based on the error signal.
  • the limiter circuit 114 outputs the signal shown in FIG. 10 (c) based on the determined upper limit voltage value and lower limit voltage value, as in the first embodiment.
  • the second clock signal generation unit 115 generates a sine wave clock signal with a variable clock frequency based on the signal of FIG. 10 (c), and generates a waveform shaping circuit. Output to 116. Note that the waveform shaping circuit 116 shapes the sine wave clock signal into a rectangular wave as described above.
  • error signal calculation section 111 detects the error signal ("0") shown in Fig. 11 (a)
  • integrator 112 shows the error signal shown in Fig. 11 (b) based on the error signal.
  • the limiter circuit 114 outputs a signal shown in FIG. 11 (c) based on the upper limit voltage value and the lower limit voltage value determined as described above.
  • the second clock signal generation unit 115 generates a sine wave clock signal whose clock frequency is variable based on the signal of FIG. 11 (c), and generates a waveform shaping circuit. Output to 116.
  • the waveform shaping circuit 116 shapes the sine wave clock signal into a rectangular wave as described above.
  • a 4-bit PCM signal having a PCM value of “0101” is input to the input terminal, and the PWM signal is based on the first clock signal shown in FIG. Is generated, the PWM signal shown in FIG.
  • the PWM signal written to the buffer 211 is generated based on the calculated error signal (>"0"), as in the first embodiment, and the clock frequency shown in Fig. 12 (c). Have When the second clock signal is read from the buffer 211, the PWM signal shown in FIG.
  • the PWM signal written to the buffer 211 is generated based on the calculated error signal ( ⁇ 0>) as in the first embodiment, and the clock frequency shown in FIG.
  • the PWM signal shown in FIG. 12 (d) is output to the switching amplifier circuit 107.
  • the clock frequency of the second clock signal can be varied based on the error signal! Therefore, the pulse width of the PWM signal output from the buffer 211 can be changed. It can be made variable. Therefore, in this embodiment, as in the first embodiment, nonlinear distortion that occurs when switching processing is performed in the switching amplifier circuit 107, that is, the DC power supply is turned on and off in the switching amplifier circuit 107. Non-linear distortion caused by switching can be accurately prevented, and the accuracy for making the pulse width of the PWM signal variable is high! No dedicated circuit is required, and the circuit scale can be reduced. . In the present embodiment, since the clock frequency of the second clock signal varies, generation of high frequency noise based on the clock frequency can also be reduced.
  • the class D power amplifying apparatus 200 of the present embodiment is a class D power amplifying apparatus 200 that performs pulse modulation on a PCM signal, amplifies the pulse modulated PWM signal, and outputs the amplified PWM signal to a speaker.
  • receives the PCM signal is a digital signal, the received PCM signal pulse-modulated, 1 ⁇ ⁇ [signal to generate a 1 ⁇ 1 ⁇ 7? 1 ⁇ ⁇ [converting unit 210 Oyobi buffer 211
  • Switching amplifier circuit 107 that switches the power supply voltage according to the generated PWM signal, amplifies the signal level of the PWM signal to generate a loud sound signal, and detects an error between the generated PWM signal and the loud sound signal.
  • the class D power amplifying device 200 of the present embodiment is similar to that of the first embodiment.
  • a second clock signal is generated with a clock frequency that changes according to the detected error signal, and a PWM signal is generated from the PCM signal using the generated second clock signal.
  • the class D power amplifying apparatus 200 of the present embodiment can generate a PWM signal using the generated second clock signal as well as the received PCM signal power, and is amplified by the switching amplifier circuit 107. Since the PWM signal pulse width can be varied, nonlinear distortion that occurs when switching processing is performed in the switching amplifier circuit 107, that is, switching the DC power supply on and off in the switching amplifier circuit 107. In addition to accurately preventing non-linear distortion caused by this, a dedicated circuit with high accuracy for making the pulse width of the PWM signal variable is also reduced, and the circuit scale required is also reduced.
  • the clock frequency of the second clock signal fluctuates in the class D power amplifying apparatus 200 of the present embodiment, generation of high-frequency noise such as unnecessary radiation based on the clock frequency can be reduced.
  • EMI countermeasures are also effective when receiving radio broadcasts close to the high-frequency noise, for example, broadcast waves of 500 kHz to 1600 kHz.
  • the error signal calculation unit is based on the (lZk) -magnified loudspeaker signal and the signal that has been subjected to the smoothing process in the second LPF 110 in the PWM signal output from the buffer 211.
  • the error signal is calculated based on the PWM signal output from the PWM signal buffer 211 amplified by the switching amplifier circuit 107 multiplied by (lZk).
  • An error signal may be calculated. In this case, similar to the above, each signal input to the error signal can be matched, so that the same effect as described above can be obtained.
  • the first sampling signal having the same clock frequency is used for the oversampling processing unit 101 and the noise-shaping circuit.
  • the oversampling processing unit 101 and the noise-shaping circuit are used for the oversampling processing unit 101 and the noise-shaping circuit.
  • a limiter circuit 114 is provided, and is input to the second clock signal generation unit 115 based on the upper limit voltage value and the lower limit voltage value with respect to the voltage value detected by the voltage detection unit 113.
  • the force that controls the voltage value Instead of providing it, keep the detected voltage value and input it to the second clock signal generator 115.
  • the power applied to the single-ended configuration that is, the binary PWM modulation may be applied to the ternary PWM modulation. In this case, if the configuration of the present embodiment is applied to each PWM signal.
  • the oversampling processing unit 101 and the noise shaving circuit 102 operate based on the first clock signal generated by the first clock signal generation unit 103.
  • a frequency dividing circuit may be provided to operate based on the frequency-divided first clock signal.
  • the first clock signal is used when signal processing of the PCM signal and the PWM signal is performed, so that a frequency dividing circuit is required.
  • the single sided PWM method is used as the PWM modulation method
  • the division ratio in (Equation 1) to (Equation 3) of the first embodiment is used, and the Doubly Sided PWM method is used as the PWM modulation method.
  • N the frequency division ratio obtained by replacing N in (Equation 1) to (Equation 3) with (N + 1), that is, N / (2 (N + 1) ) is used.
  • the present embodiment is characterized in that an asynchronous circuit is used instead of the buffer in the first embodiment, and the other points are the same as in the first embodiment, and the same reference numerals are used for the same members. The description is omitted.
  • FIG. 15 is a block diagram showing the configuration of the class D power amplifier of this embodiment
  • FIG. 16 is a diagram showing an example of signal waveforms in the asynchronous circuit of this embodiment.
  • application examples in the single sided PWM method will be described.
  • the class D power amplifying apparatus 300 is preprocessed with an oversampling processing unit 101, a noise shaving circuit 102, and a first clock signal generating unit 103.
  • this class D power amplifying apparatus 300 includes a switching amplification circuit 107, a first LPF 108, an amplifier 109, a second LPF 110, an error signal calculation unit 111, an integrator, as in the first embodiment. 112, a voltage detection unit 113, a limiter circuit 114, a second clock signal generation unit 115, and a waveform shaping circuit 116.
  • the output control unit 311 has a frequency dividing circuit that multiplies the second clock signal output from the waveform shaping circuit 116 by (N / 2 N ), and the first clock signal If, multiplies the second clock signal input (NZ2 N), and the (NZ2 N) multiplied by a second clock signal, based on, and controls the asynchronous circuit 310.
  • Asynchronous circuit 310 is constituted by, for example, a D (Delay) flip-flop or a latch, and as shown in FIG. 16, the PCM output from noise shaving circuit 102 under the control of output control unit 311. The signal is synchronized again and output to the PCMZPWM converter 312.
  • FIG. 16 shows that the width of the input PCM signal, the first clock signal, the output PCM signal, and the second clock signal multiplied by (NZ2 N ) are different in the switching cycle of the asynchronous circuit 310. Is shown. However, MSB (Most Significan Digit) indicates the most significant bit, and LSB (Least Significant Bit) indicates the least significant bit. Further, the write rate in the asynchronous circuit 310 is constant.
  • the class D power amplifying apparatus 300 of the present embodiment is a class D power amplifying apparatus 300 that performs pulse modulation on the PCM signal, amplifies the pulse modulated PWM signal, and outputs the amplified PWM signal to the speaker.
  • Asynchronous circuit 310 that receives the PCM signal, which is a digital signal, and 1 ⁇ ⁇ [ 1 ⁇ [conversion unit 312 that generates a 1 ⁇ ⁇ [signal by pulse-modulating the received PCM signal
  • the switching amplifier circuit 107 that switches the power supply voltage according to the generated PWM signal, amplifies the signal level of the PWM signal to generate a loud sound signal, and calculates an error signal that detects an error between the generated PWM signal and the loud sound signal 111 and a second clock for generating a second clock signal formed at a clock frequency that varies according to the detected error signal.
  • Lock signal generator 115, and PCMZPWM converter 312 receives a PCM signal from the received PCM signal based on the second clock signal generated by second clock signal generator 115. It has a configuration to generate.
  • the class D power amplifying apparatus 300 as in the first embodiment, generates the second clock signal formed at the clock frequency that changes according to the detected error signal. Generate a PWM signal from the received PCM signal using the generated second clock signal.
  • the class D power amplifying apparatus 300 of the present embodiment can generate a PWM signal using the generated second clock signal, and the received PCM signal power can be amplified by the switching amplifier circuit 107. Since the PWM signal pulse width can be varied, nonlinear distortion that occurs when switching processing is performed in the switching amplifier circuit 107, that is, switching the DC power supply on and off in the switching amplifier circuit 107. In addition to accurately preventing non-linear distortion caused by this, a dedicated circuit with high accuracy for making the pulse width of the PWM signal variable is also reduced, and the circuit scale required is also reduced.
  • the class D power amplifying apparatus 300 of the present embodiment varies the clock frequency of the second clock signal, generation of high frequency noise such as unwanted radiation based on the clock frequency can be reduced.
  • EMI countermeasures are also effective when receiving radio broadcasts close to the high-frequency noise, for example, broadcast waves of 500 kHz to 1600 kHz.
  • the error signal calculation unit converts the sound signal multiplied by (lZk) and the signal smoothed by the second LPF 110 in the PWM signal output from the PCMZ PWM conversion unit 312.
  • the error signal is calculated based on the PWM signal amplified by the switching amplifier circuit 107 multiplied by (lZk) and the PWM signal output from the PCMZ PWM converter 312 as shown in FIG.
  • the error signal may be calculated based on the above. In this case, similar to the above, each signal input to the error signal can be matched, so that the same effect as described above can be obtained.
  • the first clock signal having the same clock frequency is used for the oversampling processing unit 101 and the noise shaping circuit. If it can be synchronized, use different clock signals.
  • a limiter circuit 114 is provided, and the voltage value detected by the voltage detection unit 113 is input to the second clock signal generation unit 115 based on the upper limit voltage value and the lower limit voltage value.
  • the force to control the voltage value to be controlled is not provided, and the second clock signal generation unit 115 is made to hold the detected voltage value as in the first embodiment without providing the limiter circuit 114. You can enter it!
  • the single sided PWM method is described as an example of the PWM modulation method.
  • N in (Expression 1) to (Expression 3) is set to (N + Instead of 1), it is also possible to apply the double sided PWM method by setting the frequency division ratio in the output control unit 311 of this embodiment to NZ (2 (N + 1) ).
  • the power applied to the single-ended configuration that is, the binary PWM modulation may be applied to the ternary PWM modulation. In this case, if the configuration of the present embodiment is applied to each PWM signal.
  • the oversampling processing unit 101 and the noise shaving circuit 102 of the present embodiment operate based on the first clock signal generated by the first clock signal generation unit 103.
  • Each oversampling processing unit 101 and noise shaping circuit 102 should be provided with a frequency dividing circuit so that it operates based on the divided first clock signal.

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  • Power Engineering (AREA)
  • Multimedia (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Amplifiers (AREA)

Abstract

La présente invention concerne un dispositif d’amplification de puissance de classe D de petite taille permettant d’éviter une distorsion non linéaire générée lors de l’exécution d’un processus de commutation en matière de haute fréquence. Le dispositif d’amplification de puissance (100) calcule un signal d’erreur entre un signal MID avant l’exécution d’un processus de commutation et le signal MID après celle-ci, et génère un signal d’horloge à fréquence variable selon le changement du signal d’erreur calculé. Selon le signal d’horloge généré, une modulation d’impulsions en durée (MID) est réalisée pour le signal MIC.
PCT/JP2006/314452 2005-07-21 2006-07-21 Dispositif d’amplification de puissance WO2007011012A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011121954A1 (fr) * 2010-03-31 2011-10-06 パナソニック株式会社 Amplificateur numérique

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06152269A (ja) * 1992-11-05 1994-05-31 Fujitsu Ten Ltd スイッチングアンプ
JP2001517393A (ja) * 1997-04-02 2001-10-02 ニールセン，カールステン パルス変調信号の強化されたパワー増幅用パルス基準制御方法
JP2003032054A (ja) * 2001-07-03 2003-01-31 Kyokuko Tsujin Kofun Yugenkoshi 低ひずみ電力増幅方法及びそのシステム
JP2003110376A (ja) * 2001-09-28 2003-04-11 Sony Corp 信号増幅装置
JP2006191250A (ja) * 2005-01-05 2006-07-20 Nagoya Institute Of Technology 増幅器およびボリューム機能付き増幅器

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DK28398A (da) * 1998-03-03 1999-09-04 Toccata Technology Aps Fremgangsmåde ved kompensering af ulineariteter i en forstærker, en forstærker, samt anvendelser af fremgangsmåden og forst
US6476673B2 (en) * 2000-07-12 2002-11-05 Monolithic Power Systems, Inc. Class D audio amplifier
KR100508062B1 (ko) * 2002-10-10 2005-08-17 주식회사 디엠비테크놀로지 자기 발진 주파수를 높이기 위한 위상 진상-지상 보상기를구비하는 디지털 오디오 증폭기

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06152269A (ja) * 1992-11-05 1994-05-31 Fujitsu Ten Ltd スイッチングアンプ
JP2001517393A (ja) * 1997-04-02 2001-10-02 ニールセン，カールステン パルス変調信号の強化されたパワー増幅用パルス基準制御方法
JP2003032054A (ja) * 2001-07-03 2003-01-31 Kyokuko Tsujin Kofun Yugenkoshi 低ひずみ電力増幅方法及びそのシステム
JP2003110376A (ja) * 2001-09-28 2003-04-11 Sony Corp 信号増幅装置
JP2006191250A (ja) * 2005-01-05 2006-07-20 Nagoya Institute Of Technology 増幅器およびボリューム機能付き増幅器

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011121954A1 (fr) * 2010-03-31 2011-10-06 パナソニック株式会社 Amplificateur numérique
CN102823128A (zh) * 2010-03-31 2012-12-12 松下电器产业株式会社 数字放大器
JP5613672B2 (ja) * 2010-03-31 2014-10-29 パナソニック株式会社 デジタルアンプ
US8896376B2 (en) 2010-03-31 2014-11-25 Panasonic Corporation Digital amplifier

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